28/3/2020 Electromigration: Causes and Fixes – sarvangsanghavi

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Electromigration: Causes and Fixes

Signal EM
Excessive current density within interconnects – which if not effectively mitigated
causes electromigration (EM) .

Electromigration (EM) is the gradual displacement of metal atoms in a

semiconductor. It occurs when the current density through the conductor is high
enough to cause the drift of metal ions .

Failure Mechanism

1. Non-uniformity in lattice structure of Interconnects: There exists a non-

uniformity of metal interconect structures during fabrication which may results in
either void or hillocks. This non-uniformity is more dominant at vias/contacts as there
is a sudden change in conductor area through which current is flowing and ultimately
it affects the current density (J= I/A). If the current density is too high, it results void
that cause breaking of line or hillocks that causes short-circuits to adjacent lines.

2. Thermal Accelerating Effects: Once the void is formed on a line, the current density
increases as the area of conductor tends to reduce. This hampers the uniform
temperature that was established along the interconnect and increases the local
temperature which further accelerates the void growth ultimately breaking the line.
This increase in temperature due to current density is termed as Joule Heating which is
directly proportional to the square of the current density. This further widens the void
ultimately
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3. The Self-Heating Effect: Self heating refers to the the heat generated by current
carrying element. Moreover the heat dissipation mechanism of Silicon On Insulator -
FINFETs is poor as the only way to dissipate heat is through gate because oxide layer
beneath the channel is a poor conductor of heat compared to silicon that is used in
bulk-FINFETs. So in addition to the wire self-heating, FINFETs also contributes in the
heat transfer to this signal nets which increases the local temperature making wire
more prone to electromigration.

Important Terms related to signal-EM

1. Irms/Ilimit ratio: When we are analysing AC signal-em on signal nets and on clock
nets; we are generally interested in rms current check rather than peak and average
current because the principle concern is overheating of wire that causes voids and/or
hillocks that grows with time and it’s not an one-time event. Current limit (Ilimit) is
specified by foundaries and it is mentioned in LEFs for each metal layer and via. A
piece-wise linear model of metal layer width (cut-area in case of vias) and effective
frequency is specified to calculate current limit (Ilimit). The calculated rms current
(Irms) should be within this limit to avoid electromigration.

2.Effective Frequency: Electromigration also depends on slew rate; faster the

transition, the more signal net will be prone to EM violation. Hence it is necessary to
know how fast the signal/clock net is changing. Effective frequency represents the
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input clock frequency as data only changes at half rate of input clock. Similarly, the

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28/3/2020 Electromigration: Causes and Fixes – sarvangsanghavi

toggle factor for clock nets will be 200%. Alternatively, we can specify signal net
frequency (toggle rate) using VCD/TCF/SAIF file also.

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3. DeltaTemp: Another important factor affecting electromigration is temperature rise.

This value specifies the allowed temperature rise along the net. This temperature rise is
due to the current (Irms) flowing through the net which will causes power(heat)
dissipation (P = I²R). DeltaT limit is calculated from Irms limit specified in LEF. It’s unit
is specified in °C.

Causes of Signal EM

1. High Fanout Net: When multiple fanout switches together, a high current is drawn
from the driver. This high current generates considerable heat that may displace the
metal atoms resulting in either voids or hillocks.

2. Driver size: A cell size of x16 and x12 unnecessarily induces a large current in the
interconnects which heats up the wire. This large drivers causes a high Irms value and
a high DeltaT value. Moreover, FINFETs due to its 3D structure has high channel
volume that conducts more current for the same driver size compared to planar
transistor.

3. Fast Transition: Fast transition of data is the requirement in high speed chips but it
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interconnect causes them to break
from the lattice structure and causing voids and hillocks. Clock nets have the highest
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probability of suffering from this issue as it has high frequency signal passing through

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28/3/2020 Electromigration: Causes and Fixes – sarvangsanghavi

it, with very high fanout and moreover they are global nets (long nets) that spans
across the chip.

4. Long Net: Sometimes, EM may arise with a single fanout also. The reason being long
resistive interconnect. As the length of the interconnect increases, it’s resistance
increases (R=ρl/A). This high resistance causes a high localized temperature along the
net which further increases the resistance resulting metal reliability problems and
increase in Delta Temp value.

Signal EM Fixes

Manual Fixes:

1. Driver Downsizing: Downsizng the driver cell will reduce the current density in the
interconnects and reduces the risk of EM failure. Though we have to make sure that
downsizing the driver is not affecting the timing or transition time in that path. We can
check the timing of the EM affected path before & after down-sizing the driver using
STA tools like prime time, tempus.

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2. Non-Default Rule (NDR) on the victim nets: Applying NDR will increase the metal
width which will in-turn increase it’s current carrying capability. Safest way is to apply
NDR
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affect timing. Alternatively, we can apply NDR on only those segments (layers) of the
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net which have high Irms.

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28/3/2020 Electromigration: Causes and Fixes – sarvangsanghavi

3. Insert Buffer: Inserting a buffer or a pair-of-inverters will break the long nets and
reduces the resistance. We have to make sure that the EM affected path has enough
timing margin so that adding a buffer won’t degrade the timing. We can check that in
STA tool but adding a buffer will add a new net whose extraction value will be absent
and STA tools will not show the correct delay(it will only include cell delay but net
delay will be zero) of that path after adding a buffer.

4. Routing on Higher Layers: Higher routing layers are less resistive and have higher
current carrying capabilities making nets less prone to electromigration. Though we
have to make sure that before routing on higher layer, the routing congestion of those
higher layers should be less or else it will result in shorts and detouring.

5. Use multi-cut Via or NDR via: Electromigration is more dominant on vias as there is
sudden change in area through which current is flowing. Usage of multi-cut via will
increase the via area, reduces the resistance and also increases the reliability of the
wire. NDR-via are larger in size with larger contact area.

6. Break the Fanout: High fanout causes a high current to be drawn from the driver.
This can be avoided by splitting the fanout using buffers. Generally, the buffer we add
should be of same size or one size lower than the driver so that timing is not much
affected. Though this is not a strict rule.

Automatic Fixes:

1. NDR aware PnR: During global routing at placement, placement engine will occupy
more tracks for the nets wherever possible so that the net can be applied with NDR at
routing stage. This method is very effective if design is less congested.

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2. Hold Fixing: Enabling hold fixing during PnR or fixing hold timing prior to EM
fixing at sign-off considerably reduces the EM violating nets as hold fixing will add
buffers that will ultimately break the nets. Morover, in most of the PnR tools, adding
buffer will be timing-aware in a sense that it will make sure that the setup time will not
get deteriorate.

3. Making high-driving cells as Don’t Use: If EM violation is high in number, we can

run an experiment with setting high driving cell (x16 and x12) as don’t use. Setting
them as don’t use will avoid the usage of those cells throughout the PnR flow. Though
doing so, it may affect the transition time and performance.

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Sarvang
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 October 29, 2016  Sarvang  ASIC, backend, electromigration, PD, signalEM, signoff, vlsi

5 thoughts on “Electromigration: Causes and Fixes”

Devang
October 31, 2016 at 12:11 pm

Only glimpse of information is there. Please provide some detailed understanding.

Overall blog is good.

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Manish
November 17, 2016 at 12:42 pm

excellent Explanation.
Good work.

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Prabhat Tiwari
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June 8, 2018 at 10:41 am

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28/3/2020 Electromigration: Causes and Fixes – sarvangsanghavi

superb !!!!

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unknown god
October 31, 2017 at 10:32 pm

good , implemetation is important if any explaination with cmds and reports will be
nice

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Shankar
August 16, 2018 at 5:07 pm

great explainations………..Godspeed

 Liked by 1 person

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