Memory Devices and Programmable Logic Devices - Comprehensive Notes

What's Included in the Notes:

UNIT 1: Memory Devices

1. Basic Concepts of Memory

 Memory cell, byte, word definitions

 Memory operations (read/write)

 Memory addressing and capacity formulas

 Practical examples and calculations

2. Classification of Memories

 Complete hierarchy of semiconductor memories

 RAM vs ROM fundamental differences

 Detailed comparison tables

3. Memory Structure: Address and Size

 Functional block diagram breakdown

 Row and column decoder operations

 Memory array architecture

 Buffer functions
4. Introduction to RAM

 SRAM (Static RAM):

o No refresh requirement

o SR flip-flop based binary cell structure

o Read and write operations explained with diagrams

o Advantages and disadvantages

 DRAM (Dynamic RAM):

o Refresh mechanism explained

o Volatility characteristics

o Comparison with SRAM

5. ROM Types - Comprehensive Coverage
 Mask Programmed ROM:
 o Manufacturing process

o Structure and characteristics

 EPROM:

o UV erasure process (20-30 minutes)

o Programming methodology

o Applications
 EEPROM:

o Electrical erasure advantages

o In-system programming capability

o Detailed EPROM vs EEPROM comparison table

UNIT 2: Programmable Logic Devices

1. PLA (Programmable Logic Array)

 Complete structure with AND, OR, and XOR arrays

 Both arrays programmable (key feature)

 PLA programming table format and notation

 Implementation guidelines

 Multiple solved examples included in PDF context

2. PAL (Programmable Array Logic)

 Structure with fixed OR array

 Cascade capability explained

 Feedback mechanism

 PAL programming table format

3. PLA vs PAL - Comprehensive Comparison

 Detailed comparison table with 9+ parameters

 When to use which device

 Advantages and disadvantages

4. Implementation Examples

 Code converters (BCD to Excess-3, Binary to Gray)

 Arithmetic circuits (Full Adder)
  Step-by-step implementation process
Key Features of the Notes:

✓ All syllabus topics covered comprehensively

✓ Important formulas highlighted (memory capacity, address calculations)
✓ Comparison tables for quick revision
✓ Practical examples with calculations
✓ Examination tips section with common question types
✓ Summary sections with hierarchical diagrams
✓ Design considerations for both memory and programmable logic
✓ Key points highlighted throughout

Special Sections Added:

 Important Formulas and Calculations - All key equations in one place

 Design Considerations - Practical guidelines for selection

 Examination Tips - 10 important topics and common question types

 Summary Diagrams - Visual hierarchy of classifications

The notes are structured for easy revision with bold headings, bullet points for
important concepts, and tables for comparisons. All technical terms are properly
defined, and complex topics are broken down into understandable sections.

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MEMORY DEVICES AND PROGRAMMABLE LOGIC DEVICES

## Comprehensive Study Notes

---

## UNIT 1: MEMORY DEVICES

### 1.1 Basic Concepts of Memory

**Definition:**

Memory is a storage device used to store binary information, manufactured using

semiconductors in the form of Integrated Circuits (ICs).

**Key Terms:**

- **Memory Cell/Binary Cell:** The basic storage unit that can store one bit of
binary information
- **Byte:** 8-bit binary information (standard size for memory capacity)

- **Word:** 16-bit binary information

- **Double Word:** 32-bit binary (4 bytes)

- **Long Word:** 64-bit binary (8 bytes)

- **Memory Location:** A group of cells (typically 8 cells) that can store a byte

- **Memory Word Size:** The size of binary information that can be stored in a
memory location
- **Memory Word:** The stored binary information in a memory location

**Memory Operations:**

1. **Write Operation:** Process of storing binary information in a memory location

2. **Read Operation:** Process of reading back stored information from memory
location
- **Non-destructive:** Memory content remains same after reading until rewritten

**Memory Addressing:**

- Each memory location has a unique binary number called **address**

- Number of addresses depends on address bits (n)

- With n-bit binary: 2^n different addresses can be generated

**Address Calculation Examples:**

- n = 10 → 2^10 = 1024 = 1 kilo

- n = 11 → 2^11 = 2048 = 2 kilo

- n = 12 → 2^12 = 4096 = 4 kilo

- n = 16 → 2^16 = 65536 = 64 kilo

**Memory Capacity Formula:**

- Memory with **n address lines** and **m data lines** = 2^n × m bits capacity

- Capacity in bytes = (2^n × m)/8 bytes

**Example:** 1 kB Memory

- 1024 locations (2^10)

- 10 address lines

- 8 data lines (1 byte per location)

- Control signals: Read, Write, Chip Select/Enable

**Why Byte is Standard:**

- Human-machine communication uses ASCII (American Standard Code for

Information Interchange)

- ASCII is 8-bit binary code

---

### 1.2 Classification of Memories

#### 1.2.1 Major Types of Semiconductor Memories

**Two Broad Categories:**

1. **RAM (Random Access Memory) / RWM (Read/Write Memory)**

2. **ROM (Read Only Memory)**

**Random Access Feature:**

- Ability to access any memory location with same time duration

- Time to read/write any location is same

- All semiconductor memories have random access for read operations

- Only RAM has random access for write operations

**Key Difference:**

- **RAM:** Can be read or written in the system where it is fitted

- **ROM:** Can only be read in the system; requires separate ROM programmer for
writing

---

### 1.3 Memory Structure: Address and Size

#### Functional Block Diagram of Semiconductor Memory

**Main Components:**

1. **Row Address Decoder** (2^q-to-q decoder)

2. **Column Address Decoder** (2^r-to-r decoder)

3. **Memory Array** (2^n × m bits)

4. **Input Buffer**
5. **Output Buffer**

**Address Line Distribution:**

- Total address lines: n

- Split into: q + r = n

- q lines → Row decoder

- r lines → Column decoder

**Memory Array Structure:**

- Size: 2^q × 2^r matrix (2^n crossing points)

- Each crossing point = memory cell/binary cell

- Multiple layers (m layers) wired in parallel

- When address sent: one row + one column selected → m memory cells selected

**Buffer Functions:**

- Hold data until valid time

- Signal current level matching (impedance matching)

**Evolution of Memory Cells:**

- First version: Passive elements (resistors, capacitors)

- Then: Diodes

- Later: Bipolar and MOS transistors

- Latest: CMOS and HMOS (low power, high-speed)

---

### 1.4 Introduction to RAM

**RAM Characteristics:**
- Volatile memory (data lost when power OFF)

- Both read and write operations possible in system

- Random access for both read and write

- Fast access times

**Two Types of RAM:**

#### 1.4.1 SRAM (Static RAM)

**Key Features:**

- **No refreshing required**

- Once information stored, retained as long as power is ON

- Faster than DRAM

- More expensive per bit

- Lower density

- Used for cache memory

**Memory Cell Construction:**

- Uses 4-6 transistors

- Can be constructed using SR flip-flops

- Stable storage - maintains data without refresh

**SR Flip-Flop Based Binary Cell:**

**Control Signals:**

- **Enable:**

- Enable = 1: Read/Write operation allowed

- Enable = 0: Read/Write operation not possible

- **Read/Write:**
 - Read/Write = 1: Binary value of Q available on output (READ)

- Read/Write = 0: Binary value of input stored in Q (WRITE)

**Read Operation:**

- Enable = 1, Read/Write = 1

- Input AND gates disabled (S = R = 0)

- No change in output Q

- Output AND gate enabled

- Value of Q available on output

**Write Operation:**

- Enable = 1, Read/Write = 0

- Input AND gates enabled

- Input value and complement applied to S and R

- Value stored in flip-flop Q

- Output AND gate disabled

---

#### 1.4.2 DRAM (Dynamic RAM)

**Key Features:**

- **Requires periodic refreshing** even when power is ON

- All DRAM devices have in-built refreshing logic

- Refreshing: Read memory content periodically and write to same location

- Higher density than SRAM

- Less expensive per bit

- Slower than SRAM

- Used for main memory
**Volatility:**

- Both DRAM and SRAM are **volatile memories**

- Information retained only when power supply is ON

- Data lost when power is OFF

---

### 1.5 ROM (Read Only Memory)

**General Characteristics:**

- **Non-volatile memory:** Data retained even when power is OFF

- Permits only read access in system

- Random access feature for read operation only

- Also called: Dead memory, Fixed memory, Permanent memory, Read-Only Store
(ROS)
- **Programming:** Process of storing information in ROM

---

#### 1.5.1 ROM Types and Classification

**Three Main Categories:**

1. **Custom/Mask Programmed ROM (ROM)**

2. **Programmable ROM (PROM) - Field Programmable**

3. **Reprogrammable ROM (EPROM) - Erasable-Programmable**

---
#### 1.5.2 Mask Programmed ROM (ROM)

**Characteristics:**

- Programmed by manufacturer during fabrication

- Programmed as per customer specifications

- **Contents cannot be changed after packaging**

- One-time programming during manufacturing

- Most economical for large quantities

**Structure:**

- n-bit address input

- m-bit data output

- MOS transistor-based memory cells

**Memory Cell Types:**

- **Closed gate transistor:** Represents 1

- **Open gate transistor:** Represents 0

- Configuration is fixed permanently

**Advantages:**

- Low cost for mass production

- High reliability
- Fast access time

**Disadvantages:**

- No flexibility after manufacturing

- High initial setup cost

- Long lead time
---

#### 1.5.3 EPROM (Erasable Programmable ROM)

**Key Features:**

- **UV Erasable:** Uses ultraviolet light for erasing

- **Erasure time:** 20-30 minutes of UV exposure

- Requires removal from system for erasing

- Can be reprogrammed using separate ROM programmer

- Reusable multiple times

**Structure:**

- Quartz window on package for UV light exposure

- Floating gate MOS transistor technology

- Window covered with label during normal use

**Programming:**

- Requires special EPROM programmer

- Higher voltage for programming (typically 12-25V)

- Programs by storing charge in floating gate

**Erasing Process:**

- Remove from system

- Expose to UV light through quartz window

- UV light releases stored charge

- Entire chip erased at once

**Advantages:**
- Reusable

- Good for prototyping and development

- Cost-effective for small quantities

**Disadvantages:**

- Must be removed from system for erasing

- Entire chip erased (cannot erase selectively)

- UV eraser equipment needed

- Erasing takes time (20-30 minutes)

**Applications:**

- Program storage in microprocessor systems

- Development and prototyping

- Small production runs

- BIOS in older computers

---

#### 1.5.4 EEPROM (Electrically Erasable Programmable ROM)

**Also called:** EAPROM

**Key Features:**
- **Electrically erasable:** Erased by passing electrical current

- **In-system erasable:** No need to remove from circuit

- Can be erased and reprogrammed in the system

- Selective erasure possible (byte-by-byte or block-by-block)

- No separate erasure system needed

**Programming and Erasing:**

- Both done electrically

- Read and write operations similar to RAM

- Typically slower write times than RAM

- Limited write/erase cycles (typically 10^5 to 10^6)

**Advantages:**

- In-circuit programming and erasing

- Selective erasure capability

- No UV eraser needed

- Faster than EPROM erasing

- Can update small portions of memory

**Disadvantages:**

- More expensive than EPROM

- Limited write/erase cycles

- Slower write operation compared to RAM

- More complex circuitry

**Applications:**

- Configuration data storage

- Firmware updates

- User-programmable settings
- Non-volatile data storage in embedded systems

- Modern BIOS/UEFI

**Comparison: EPROM vs EEPROM**

| Feature | EPROM | EEPROM |

|---------|-------|--------|

| Erasure Method | UV light | Electrical current |

| Erasure Time | 20-30 minutes | Milliseconds |

| In-system Erasure | No | Yes |

| Selective Erasure | No (entire chip) | Yes (byte/block) |

| Equipment Needed | UV eraser | None (electrical) |

| Cost | Lower | Higher |

| Write Cycles | Unlimited erase cycles | Limited (10^5-10^6) |

---

### 1.6 Memory Interfacing with Microprocessor

**Connection Signals:**

**Three Standard Control Signals:**

1. **Chip Enable/Memory Enable**

2. **Write Control**

3. **Read Control**

**Plus:**

- n address lines

- m data lines (bidirectional)

---

#### Read Operation Sequence:

1. Microprocessor outputs address

2. Microprocessor activates Chip Enable and Read control

3. Memory outputs data on data lines

4. Microprocessor reads data from data lines

5. All operations completed in 3-4 clock cycles

---

#### Write Operation Sequence:

1. Microprocessor outputs address

2. Microprocessor activates Chip Enable and Write control

3. Microprocessor outputs data on data lines

4. Memory reads data and stores in location

5. All operations completed in 3-4 clock cycles

---

**Example: 1024 × 16 Memory Unit**

**Specifications:**

- Capacity: 1024 locations × 16 bits

- 1024 = 2^10 → 10 address lines needed

- 16 data lines

**Address Range:**

- Binary: 00 0000 0000 to 11 1111 1111

- Hexadecimal: 000H to 3FFH

- Decimal: 0 to 1023
**Total Binary Cells Required:**

- 1024 × 16 = 16,384 binary cells

---

## UNIT 2: PROGRAMMABLE LOGIC DEVICES

### 2.1 Introduction to Programmable Logic Devices

Programmable logic devices are used to implement Boolean functions in sum of

products (SOP) form. They provide a flexible alternative to fixed logic gates for
implementing combinational circuits.

**Two Main Types:**

1. **PLA (Programmable Logic Array)**

2. **PAL (Programmable Array Logic)**

---

### 2.2 PLA (Programmable Logic Array)

**Definition:**

PLA is a one-time programmable device to implement Boolean functions in sum of

products form.

---

#### 2.2.1 PLA Structure

**Components:**
1. **Array of AND gates** (programmable)

2. **Array of OR gates** (programmable)

3. **XOR gates** (for output polarity control)

**Typical PLA Device has:**

- **n inputs**

- **k AND gates** (to implement product terms)

- **m OR gates** (to implement sum of products)

- **m XOR gates** (for output control)

**Input Stage:**

- Each input provided with buffer and inverter

- Generates both true and complement of each input

- Total available inputs to AND array: 2n

**AND Array (Programmable):**

- Each AND gate can have 2n inputs

- Programmable connections from inputs to AND gates

- Generates product terms

**OR Array (Programmable):**

- Each OR gate can have k inputs

- Output of any AND gate can be routed to any OR gate

- Generates sum of product terms

**XOR Gates:**

- Used to generate normal or complement of output

- One input: Output of OR gate (F)
- Other input: Programmable to 0 or 1

**XOR Operation for Output Control:**

- F ⊕ 0 = F (True output)

- F ⊕ 1 = F' (Complement output)

---

#### 2.2.2 PLA Symbolic Representation

**Simplified Structure:**

- Single buffer with two outputs (true and complement)

- Bubble indicates inverted output

- Slash with number indicates multiple input lines

- Connected inputs marked with "×"

---

#### 2.2.3 PLA Programming Table

**Table Format:**

| Product Term | Inputs (A B C...) | Outputs (F1 F2...) |

|--------------|-------------------|-------------------|

| | | (T) or (C) |

**Table Notation:**

- **1:** Variable is connected to form product term

- **0:** Complement of variable is connected
- **-:** Variable/complement not connected

- **1 under output:** Product term connected to OR gate

- **- under output:** Product term not connected to OR gate

- **(T):** True form of SOP output (XOR with 0)

- **(C):** Complement form of SOP output (XOR with 1)

---

#### 2.2.4 Implementation Guidelines

**Before Implementation:**

1. Simplify Boolean functions to minimum literal form

2. Use K-maps for simplification

3. Express in SOP form

4. Create PLA programming table

5. Mark connections

**Steps for Implementation:**

1. Determine number of input variables (n)

2. Count product terms needed (k)

3. Determine number of outputs (m)

4. Select PLA with adequate resources

5. Program AND array for product terms

6. Program OR array for sum terms

7. Configure XOR gates for output polarity

---

#### 2.2.5 Important Points for PLA

✓ **Both AND and OR arrays are programmable**

✓ Product terms can be shared among multiple outputs

✓ Efficient for functions with common product terms

✓ Good for multiple output functions

✓ Minimizes total gates required

✓ Flexible routing of product terms

---

### 2.3 PAL (Programmable Array Logic)

**Definition:**

PAL is a programmable logic device to implement Boolean functions in sum of

products form with programmable AND array and **fixed OR array**.

---

#### 2.3.1 Key Difference: PLA vs PAL

**Main Distinction:**

- **PLA:** Both AND and OR arrays programmable

- **PAL:** Only AND array programmable, OR array fixed

**Implications:**

- In PAL: One AND-OR set implements one function independently

- Product terms cannot be directly shared between functions

- Each output has dedicated AND gates

---

#### 2.3.2 PAL Structure

**Components:**

1. **Programmable AND array**

2. **Fixed OR gates**
3. **XOR gates** (for output polarity control)

4. **Feedback capability** (outputs can feed back as inputs)

**Typical PAL Device has:**

- **n inputs**

- **m OR gates** (one per output)

- **k AND gates per OR gate**

- **m XOR gates**

**Input Configuration:**

- Each input with buffer and inverter

- Both true and complement available

- Total inputs to AND gates: 2(n + m)

- 2n from input variables

- 2m from feedback outputs

---

#### 2.3.3 PAL Features

**Fixed OR Array:**
- Each OR gate connected to specific set of AND gates

- Cannot route product terms between different outputs

- Simpler structure than PLA

**Cascade Capability:**

- Output of one AND-OR array can be input to another

- Allows implementation of functions with more product terms

- Provides flexibility for complex functions

**Tristate Output (Some PAL devices):**

- Active low output capability

- Output enable control

- Allows bus connection

---

#### 2.3.4 PAL Programming Table

**Table Format:**

| Product Term | Inputs (A B C...) | Output Function |

|--------------|-------------------|-----------------|

| | | (T) or (C) |

**Notation Same as PLA:**

- **1:** Variable connected

- **0:** Complement connected

- **-:** Not connected

- **(T):** True output (XOR with 0)
- **(C):** Complement output (XOR with 1)

---

#### 2.3.5 Implementation Guidelines for PAL

**Design Process:**

1. Simplify each Boolean function independently

2. Each function implemented in separate AND-OR array

3. Determine maximum product terms needed

4. Select PAL with adequate AND gates per output

5. Program AND array

6. Configure XOR for output polarity

7. Utilize feedback if needed for cascading

**Important Considerations:**

- Each output function must fit in allocated AND gates

- Cannot share product terms between outputs (unless using feedback)

- May require more AND gates than PLA for same functions

---

#### 2.3.6 PAL vs PLA Comparison

| Feature | PLA | PAL |

|---------|-----|-----|

| AND Array | Programmable | Programmable |

| OR Array | Programmable | Fixed |

| Product Term Sharing | Yes, flexible | No, unless using feedback |
| Structure Complexity | More complex | Simpler |

| Efficiency | Better for shared terms | Better for independent functions |

| Speed | Slower | Faster |

| Cost | Higher | Lower |

| Flexibility | More flexible | Less flexible |

| Application | Multiple outputs with shared terms | Independent function outputs |

---

### 2.4 Implementation Examples - Key Concepts

#### Converting Boolean Functions to PLA/PAL

**Process:**

1. **Obtain truth table** or Boolean expression

2. **Simplify using K-maps**

3. **Express in SOP form**

4. **Create programming table**

5. **Draw structure with connections**

---

#### Common Applications:

**1. Code Converters:**

- BCD to Excess-3

- Binary to Gray

- Gray to Binary
**2. Arithmetic Circuits:**

- Full Adder

- Half Adder

- Comparators

**3. Combinational Logic:**

- Multiplexers

- Decoders
- Encoders

---

### 2.5 Important Formulas and Calculations

**Memory Capacity:**

- Capacity in bits = 2^n × m

- Capacity in bytes = (2^n × m) / 8

- Capacity in KB = (2^n × m) / (8 × 1024)

**Address Lines:**

- For N locations: n = log✓(N)

- For 1K locations: n = 10

- For 64K locations: n = 16

**Data Lines:**

- For byte-wide memory: m = 8

- For word-wide memory: m = 16

- For double-word: m = 32
**PLA/PAL Resources:**

- Input variables: n

- Product terms: k

- Outputs: m

- AND gate inputs in PLA: 2n

- AND gate inputs in PAL: 2(n + m)

---

### 2.6 Design Considerations

#### For Memory Systems:

✓ Determine required capacity

✓ Calculate address and data lines

✓ Select appropriate memory type (RAM/ROM)

✓ Consider volatility requirements

✓ Evaluate speed requirements

✓ Cost considerations

#### For Programmable Logic:

✓ Count input variables

✓ Simplify Boolean functions

✓ Count product terms

✓ Check for shared terms (PLA advantage)

✓ Determine output polarity needed

✓ Select PLA or PAL based on requirements

---
### 2.7 Key Advantages and Disadvantages

#### SRAM

**Advantages:** Fast, no refresh, simple interface

**Disadvantages:** Low density, expensive, volatile

#### DRAM

**Advantages:** High density, low cost per bit

**Disadvantages:** Requires refresh, slower, volatile, complex

#### ROM (Mask)

**Advantages:** Non-volatile, low cost (mass production), fast

**Disadvantages:** Cannot change, high setup cost, long lead time

#### EPROM

**Advantages:** Reusable, good for development

**Disadvantages:** UV eraser needed, must remove from circuit, slow erase

#### EEPROM

**Advantages:** In-system programmable, selective erase, no UV needed

**Disadvantages:** Expensive, limited cycles, slower writes

#### PLA
**Advantages:** Flexible, shared product terms, efficient

**Disadvantages:** Complex, slower, expensive

#### PAL

**Advantages:** Faster, simpler, cheaper

**Disadvantages:** Less flexible, no term sharing, may need more gates
---

## SUMMARY OF IMPORTANT POINTS

### Memory Classification Hierarchy:

```

Semiconductor Memory

├── RAM (Volatile)

│ ├── SRAM (Static - No refresh)

│ └── DRAM (Dynamic - Needs refresh)

└── ROM (Non-volatile)

├── Mask ROM (Factory programmed)

├── PROM (One-time programmable)

├── EPROM (UV erasable)

└── EEPROM (Electrically erasable)

```

### Programmable Logic Hierarchy:

```

Programmable Logic Devices

├── PLA (Programmable Logic Array)

│ ├── Programmable AND array

│ ├── Programmable OR array

│ └── Output XOR gates

└── PAL (Programmable Array Logic)

├── Programmable AND array

├── Fixed OR array

 ├── Output XOR gates

└── Feedback capability

```

---

## EXAMINATION TIPS

### Important Topics for Exams:

1. ✓ Memory classification and characteristics

2. ✓ Difference between SRAM and DRAM

3. ✓ ROM types and comparison

4. ✓ Memory capacity calculations

5. ✓ Binary cell structure and operations

6. ✓ PLA vs PAL comparison

7. ✓ Implementation of Boolean functions

8. ✓ Programming table creation

9. ✓ Code converter implementations

10. ✓ Full adder using PLA/PAL

### Common Question Types:

- **Define and explain** memory types

- **Compare and contrast** SRAM/DRAM, EPROM/EEPROM, PLA/PAL

- **Calculate** memory capacity, address lines

- **Implement** Boolean functions using PLA/PAL

- **Draw** memory structure, PLA/PAL diagrams

- **Create** programming tables

- **Design** code converters, adders

---

## END OF NOTES