OR Gate Microproject — Design and Verify Truth Table
Title
Design and Verify the Truth Table of the OR Logic Gate
Objective
1. Understand the behavior of a 2-input OR gate.
2. Design the circuit and construct its truth table.
3. Verify the truth table by simulation and simple logical checks.
Introduction
An OR gate is a basic digital logic gate that outputs 1 when at least one of its inputs is 1. For
two inputs A and B, the Boolean expression is:
Y = A + B (where + denotes logical OR)
This microproject focuses on the 2-input OR gate: theory, truth table, circuit diagram, and
verification.
Materials (for practical verification)
• Breadboard (optional, for physical build)
• 2 × SPDT switches or jumper wires to supply logic 0/1
• 1 × OR gate IC (e.g., 7432 for TTL) or equivalent CMOS part
• LEDs (with current-limiting resistors) to observe output
• Power supply: +5V for TTL or appropriate supply for CMOS
• Multimeter (optional)
If doing purely simulation, use any logic simulator (Logisim, Proteus, Multisim, Falstad
circuit simulator, or Python simulation).
Circuit Diagram (2-input OR)
A ----| |---- Y = A OR B
| OR |------> OUTPUT
B ----| |
(Or use the standard OR gate symbol in your simulator.)
Truth Table (2-input OR gate)
A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1
Explanation: output is 1 whenever at least one input is 1.
Verification Methods
1) Logical verification (by Boolean expression)
Using Y = A + B: - If A=0 and B=0 → Y = 0 + 0 = 0 - If A=0 and B=1 → Y = 0 + 1 = 1 - If A=1 and
B=0 → Y = 1 + 0 = 1 - If A=1 and B=1 → Y = 1 + 1 = 1 (in Boolean algebra 1+1 = 1)
Matches the truth table above.
2) Karnaugh Map (K-map) sanity-check
K-map for A (rows) and B (columns):
B=0 B=1
A=0 0 1
A=1 1 1
Grouping shows a single group covering all 1s; simplified expression is A + B — consistent.
3) Simulation using Python (digital logic simulation)
You can run this small snippet to verify all combinations:
# 2-input OR truth table verification
combinations = [(0,0),(0,1),(1,0),(1,1)]
print('A B | Y')
for a,b in combinations:
y = int(bool(a or b))
print(f'{a} {b} | {y}')
Output will be:
A B | Y
0 0 | 0
0 1 | 1
1 0 | 1
1 1 | 1
4) Physical verification (if building the circuit)
1. Wire the OR gate IC on the breadboard; connect Vcc and GND.
2. Connect input A and B to switches that toggle 0/1.
3. Attach output to an LED with resistor.
4. Test the four input combinations and record observations — they should match the
truth table.
Observations (expected)
• LED is OFF only when both A and B are 0.
• LED is ON for all other combinations.
Conclusion
The OR gate outputs logical 1 when any of its inputs is 1. The truth table, Boolean
expression, K-map, simulation, and (if performed) physical experiment all confirm the
same behaviour.
Extensions (optional, for extra credit)
• Design and verify a 3-input OR gate (Y = A + B + C) and write its 8-row truth table.
• Implement OR using basic gates: A + B = (A \cdot B)'? (Note: De Morgan form is
A + B = (A'·B')'.) Verify with truth table.
• Compare OR behaviour across TTL vs CMOS in terms of voltage thresholds and
power consumption.
Marks / Rubric (suggested)
• Theory & Objective: 10 marks
• Circuit Diagram & Components: 10 marks
• Truth Table: 10 marks
• Verification (simulation/physical): 40 marks
• Observations & Conclusion: 20 marks
• Neatness & Presentation: 10 marks
References / Resources
• Basic digital logic textbooks or online tutorials (Logisim, Falstad circuits).
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