8086 Microprocessor

By
Dr. Raqibul Hasan

Lecture 3
Intel Microprocessor Evolution Table

Name Year Transistors Data Width Clock Speed

8080 1974 6,000 8 bits 2 MHz
8085 1976 6,500 8 bits 5 MHz
8086 1978 29,000 16 bits 5 MHz
8088 1979 29,000 8 bits 5 MHz
80286 1982 134,000 16 bits 6 MHz
80386 1985 275,000 32 bits 16 MHz
80486 1989 1,200,000 32 bits 25 MHz
Pentium 1993 3,100,000 32/64 bits 60 MHz
Pentium II 1997 7,500,000 64 bits 233 MHz
Pentium III 1999 9,500,000 64 bits 450 MHz
Pentium IV 2000 42,000,000 64 bits 1.5 GHz

2
 Overview: Intel 8086
• Introduced in 1978
• Performance < 0.5 MIPS
• 16-bit architecture
• “Assembly language” compatible with 8080
• Designed using HMOS technology
• 29,000 transistors
• Includes memory protection
• 1MB memory (20 bits address)
• In 1981, IBM introduces PC
• Based on 8088--8-bit bus version of 8086
 8086 Features
• Manufacturing process 3 micron N-channel, silicon gate technology (HMOS)
• 29,000 transistors
• Data bus width: 16 bit
• Address bus width: 20 bit
• Physical memory: 1MB
• Package 40-pin side-brazed ceramic DIP
• Speed: 5 MHz
• Core Voltage (V): 5 ± 10%
• Min/Max operating temperature (°C): 0 – 70
 8086 Features
• 20-bit address bus
220 addresses
Each address represents 1 byte memory
Total addressable memory = 220 bytes = 1 MB
• The address refers to a byte in memory.

• In the 8086, bytes at even addresses come in on the low half of the data bus (bits 0-7)
and bytes at odd addresses come in on the upper half of the data bus (bits 8-15).

• The 8086 can read a 16-bit word at an even address in one operation and at an odd
address in two operations.

The least significant byte of a word on an 8086 family microprocessor is at the lower
address.
 Address
000 8 bits
001
010
Address 011
(row number)
01010101
100 01010101
100 Data (40 bits)
101
110
111
Memory
Memory

Address line width = log2(# of rows in the memory) bits

# of rows in the memory = 2(address line width in bits)
 8086 Pins and Signals
Pin No. Signal Direction Function / Description
2–16 AD0–AD15 Bidirectional Time-multiplexed lines: act as address bus during T1 (address
output) and data bus during T2–T4 (data input/output).

35–39 A16/S3 – A19/S6 Output Time-multiplexed lines: A16–A19 during T1 (address output),
and status signals (S3–S6) during T2–T4.

34 BHE/S7 Output BHE (Bus High Enable) selects high byte (D8–D15) during data
transfer; in max mode, gives status signal S7.

Status bit S6 is always a logic 0, bit S5 indicates

the condition of the IF flag bit, and S4 and S3
show which segment is accessed during the
current bus cycle.
8
Pin No. Signal Direction Function / Description
21 RD Output Read signal: Indicates that the processor wants to read data
from memory or I/O.
22 READY Input The READY input is controlled to insert wait states into the
timing of the microprocessor. If the READY pin is placed at a
logic 0 level, the microprocessor enters into wait states and
remains idle. If the READY pin is placed at a logic 1 level, it has
no effect on the operation of the microprocessor.
23 INTR Input Maskable interrupt request signal.
24 NMI Input Non-maskable interrupt.
25 TEST Input The Test pin is an input that is tested by the WAIT instruction. If
logic 0, the WAIT instruction functions as an NOP and if TEST is
a logic 1, the WAIT instruction waits for TEST to become a
logic 0. The is most often connected to the 8087 numeric 9
coprocessor.
26 CLK Input System clock input.
27 RESET Input Resets CPU, clears IP, disables interrupts, sets segment
registers to F000H.
Pin No. Signal Direction Function / Description
28 MN/MX Input HIGH: single processor system (minimum mode).
LOW: multi-processor system (maximum mode).
29 GND Ground reference.
40 VCC +5V power supply.
 Minimum Mode Pins:

Pin No. Signal Direction Function / Description

24 INTA Output Interrupt Acknowledge: Used to acknowledge interrupt request.
28 ALE Output Can be used to demultiplex the ADO-AD 15 into A0-A 15 and DO-D 15
at the falling edge of ALE.
29 DEN Output Activates external data bus buffers.
30 DT/R Output The data transmit/receive signal shows that the microprocessor data
bus is transmitting (1) or receiving (0).
31 M/IO Output Low for I/O operations, high for memory operations.
32 WR Output Write signal: Indicates write to memory or I/O.
33 HLDA Output Hold acknowledge indicates that the 8086 has entered the hold state.
34 HOLD Input The hold input requests a direct memory access (DMA). If the HOLD
signal is a logic 1, the microprocessor stops executing software and
places its address, data, and control bus at the high-impedance
state. If the HOLD pin is a logic 0, the microprocessor executes
software normally.
Maximum Mode Pins:

Instruction queue status

QS1 QS0 Queue Status Meaning
No operation — Queue is idle (no
0 0
fetch in progress).
First byte of an opcode fetched
0 1
into the queue.
Queue is empty — Execution unit
1 0
has consumed all queued bytes.
Subsequent byte fetched (not the
1 1
first one) into the queue.
Maximum Mode Pins:

Signal Direction Function

RQ/GT0̅ Bidirectional Bus Request / Grant line 0
RQ/GT1̅ Bidirectional Bus Request / Grant line 1
The 8086 outputs LOW on the LOCK pin to
LOCK Output prevent other bus masters from gaining
control of the system bus.
14
8086 Architecture
 8086 Architecture

• The 8086 has two parts, the Bus Interface Unit (BIU) and the
Execution Unit (EU).

• The BIU fetches instructions, reads and writes data, and computes
the 20-bit address.

• The EU decodes and executes the instructions using the 16-bit ALU.
 Bus Interface Unit (BIU)

• A register stores a data/address.

• The BIU contains the following registers:
• IP - the Instruction Pointer
• CS - the Code Segment Register
• DS - the Data Segment Register
• SS - the Stack Segment Register
• ES - the Extra Segment Register
• The BIU fetches instructions using the CS and IP, written CS:IP, to
construct the 20-bit address.
• Data is fetched using a segment register (usually the DS) and an
effective address (EA) computed by the EU depending on the
addressing mode.
•Instruction Queue
• The BIU’s instruction queue is a First-In-First-Out (FIFO) group of
registers, in which up to six bytes of instruction can be pre-fetched
from memory ahead of execution.
• This mechanism is called pipelining.
• If the queue is not full and empty by two bytes, the BIU may
pre-fetch instructions.
• The queue allows the BIU to keep the EU supplied with
pre-fetched instructions without engaging the system bus.
 Execution Unit

The EU contains the following 16-bit registers:

AX - the Accumulator
BX - the Base Register
CX - the Count Register
DX - the Data Register
SP - the Stack Pointer \ defaults to stack segment
BP - the Base Pointer /
SI - the Source Index Register
DI - the Destination Index Register

These are referred to as general-purpose registers.

 General purpose Registers of 8086

•The AX, BX, CX, and DX registers can be considered

as two 8-bit registers, a High byte and a Low byte.
•The 8-bit registers are:
• AX --> AH,AL
• BX --> BH,BL
• CX --> CH,CL
• DX --> DH,DL
8086 Registers

21
22
23
Real Mode Memory Addressing
• 1MB memory, 20 bit memory address.
• Each memory byte has an unique address.
• In real mode the memory address is based on segment and
offset registers.
• Segment register indicates the beginning address of the
segment in memory.
• Segment: 1000H
– Segment starts at memory address: 10000H
• Offset indicates byte position in the segment (byte number
within a segment)
• Memory address = (segment) *10H + offset
• Segment 1000H; offset F000H
– Memory address: 10000H + F00H or 1F000H
8086/88 internal registers 16 bits (2 bytes each)
AX, BX, CX and DX are
two
bytes wide and each byte can
be accessed separately

These registers are used as

memory pointers.

Flags will be discussed later

Segment registers are used

as base address for a
segment
in the 1 M byte of memory