Pin Diagram and Pin description of 8085

The 8085 microprocessor is available on a 40-pin Dual-in-Line package (DIP). The

A8 – A15 (Output 3 State): Address Bus

The most significant 8 bits of the memory address or the 8 bits of the I/0 addresses, 3 stated
during Hold and Halt modes.

AD0 - AD7 (Input/ Output 3 state): Multiplexed Address/Data Bus

Lower 8 bits of the memory address (or I/0 address) appear on the bus during the first clock
cycle of a machine state. It then becomes the data bus during the second and third clock cycles.
3 stated during Hold and Halt modes.

ALE (Output): Address Latch Enable

SO, S1 (Output): Data Bus Status

Encoded status of the bus cycle:

S1 S0 status
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
RD (Output 3state): READ

Indicates the selected memory or 1/0 device is to be read and that the Data Bus is available
or the data transfer.

WR (Output 3state): WRITE

Indicates the data on the Data Bus is to be written into the selected memory or 1/0 location.

READY (Input):

If Ready is high during a read or write cycle, it indicates that the memory or peripheral is
ready to send or receive data. If Ready is low, the CPU will wait for Ready to go high
before completing the read or write cycle.

HOLD (Input):

Indicates that another Master is requesting the use of the Address and Data Buses. The CPU,
upon receiving the Hold request. will relinquish the use of buses as soon as the completion of
the current machine cycle. Internal processing can continue. The processor can regain the
buses only after the Hold is removed. When the Hold is acknowledged, the Address, Data,
RD, WR, and IO/M lines are 3stated.

HLDA (Output): HOLD ACKNOWLEDGE

Indicates that the CPU has received the Hold request and that it will relinquish the buses in
the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the
buses one half clock cycle after HLDA goes low.

INTR (Input): INTERRUPT REQUEST

It is used as a general purpose interrupt. It is sampled only during the next to the last clock
cycle of the instruction. If it is active, the Program Counter (PC) will be inhibited from
incrementing and an INTA will be issued. During this cycle a RESTART or CALL
instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and
disabled by software. It is disabled by Reset and immediately after an interrupt is accepted.

INTA (Output): INTERRUPT ACKNOWLEDGE

It is used instead of (and has the same timing as) RD during the Instruction cycle after an
INTR is accepted. It can be used to activate the 8259 Interrupt chip or some other interrupt
port.

RST 5.5, RST 6.5, RST 7.5 (Inputs): RESTART INTERRUPTS

These three inputs have the same timing as INTR except they cause an internal RESTART
to be automatically inserted.

RST 7.5 --------- Highest Priority

RST 6.5

RST 5.5--------Lowest Priority

The priority of these interrupts is ordered as shown above. These interrupts have a higher
priority than the INTR.

TRAP (Input):

Trap interrupt is a non-maskable restart interrupt. It is recognized at the same time as INTR.
It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt.
RESET IN (Input):

Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops.
None of the other flags or registers (except the instruction register) are affected The CPU is
held in the reset condition as long as Reset is applied.

RESET OUT (Output):

Indicates CPU is being reset. Can be used as a system RESET. The signal is synchronized to
the processor clock.

X1, X2 (Input):

Crystal or RC network connections to set the internal clock generator X1 can also be an
external clock input instead of a crystal. The input frequency is divided by 2 to give the
internal operating frequency.

CLK (Output):

Clock Output for use as a system clock when a crystal or R/ C network is used as an input to
the CPU. The period of CLK is twice the X1, X2 input period.

IO/M (Output):

IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold

and Halt modes.

SID (Input): Serial input data line

The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed.

SOD (output): Serial output data line

The output SOD is set or reset as specified by the SIM instruction.

Vcc:

+5 volts supply.

Vss:

Ground Reference.

Microcontroller: A highly integrated chip that contains all the components comprising a controller.
• Typically this includes a CPU, RAM, some form of ROM, I/O ports, and timers.
• Unlike a general-purpose computer, which also includes all of these components, a microcontroller is
designed for a very specific task - to control a particular system.