DP83TC817S-Q1

SNLS767A – APRIL 2024 – REVISED OCTOBER 2024

DP83TC817S-Q1 Precise and Secure 100BASE-T1 Automotive Ethernet with

IEEE802.1AE MACsec, IEEE802.1AS and TC10 Sleep-Wake
1 Features 2 Applications
• IEEE 802.1AE MACsec • ADAS
– MACsec frame expansion: Inbuilt buffering and – Radar Synchronization
flow control support to handle 12 byte IPG • Body Electronics & Lighting
Ethernet frames – Body Control Module
– Authentication, encryption at line rate – Zone Control Module
– Cipher suites: GCM-AES-XPN-128/256, GCM- • Telematics
AES-128/256
– Secure Channel: Total 16 SAK enabling 8 3 Description
Tx/Rx SC The DP83TC817S-Q1 is an IEEE 802.3bw and
– Auto rollover support for SAK Open Alliance (OA) compliant automotive qualified
– Ingress/Egress classification for Ethertype, 100Base-T1 Ethernet physical layer transceiver. The
VLAN, DMAC: up to 8 parallel rules device provides all physical layer functions needed
– Window replay protection to transmit and receive data over unshielded/shielded
• IEEE 802.1AS time synchronization single twisted-pair cables with xMII interface flexibility.
– Highly accurate 1pps signal
The DP83TC817S-Q1 integrates IEEE 802.1AE
• Synchronization Jitter: < ±15ns (options to
line rate security with authentication and optional
reduce to ±1ns)
encryption support to secure communication over
• Synchronization Offset: < ±30ns
the network. The PHY supports up to 16 secure
– Precise time stamping for MACsec encoded
association (SA) channels with automatic SAK
PTP packets
rollover and extended packet numbering support.
– Multiple IOs for event capture and trigger
DP83TC817S-Q1 offers ingress classification to filter
• IEEE 802.3bw, OA 100BASE-T1 and TC-10
the unwanted packets & supports WAN MACsec for
compliant
end-to-end security.
– < 18μA sleep current
– Fast wake from sleep by retaining PHY The DP83TC817S-Q1 integrates IEEE802.1AS /
configuration during sleep (optional) IEEE1588v2 to enable highly accurate time
• Robust EMC Performance synchronization and hardware time stamping for
– IEC62228-5, OA EMC compliant time-sensitive, real-time controlled applications, with
– SAE J2962-3 EMC compliant support for encrypted PTP packets.
– 39dBm DPI Immunity with ±5% assymetry The DP83TC817S-Q1 supports OA TC-10 low power
– <4dBμV radiated emissions in GPS and sleep feature with wake forwarding for reduced
Glonass bands system power consumption when communication is
– Stripline Emissions: Class-II compliant not required.
• MAC Interfaces: MII, RMII, RGMII, SGMII
• Footprint compatible with TI's 1000BASE-T1 PHY The DP83TC817S-Q1 is footprint compatible to
– Single board design for 100BASE-T1 and TI's 100BASE-T1 PHYs and 1000BASE-T1 PHYs
1000BASE-T1 with required BOM change enabling design scalability with a single board for
• Diagnostic tool kit different speeds and features.
– Signal Quality Indication (SQI) & Time Domain Device Information
Reflectometry (TDR) PART NUMBER PACKAGE (1) BODY SIZE (NOM) (2)
– Voltage, Temperature & ESD sensors DP83TC817S-Q1 VQFN (36) 6.00mm × 6.00mm
– PPM monitor: Provides external clock ppm drift
(up to ±100ppb accuracy) (1) For all available packages, see Mechanical, Packaging and
• AEC-Q100 qualified for Automotive Applications: Orderable Information.
(2) The package size (length × width) is a nominal value and
– Temperature Grade 1: –40°C to +125 °C includes pins, where applicable.
– IEC61000-4-2 ESD level 4 MDI: ±8kV CD

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DP83TC817S-Q1
SNLS767A – APRIL 2024 – REVISED OCTOBER 2024 www.ti.com

25 MHz XTAL/Ref
Clock
Clk Out

DP83TC817 100Base-T1

TC-10 sleep/wake
Analog Front End
100BASE-T1

RGMII/SGMII
MACsec -TSN capable IEEE 802.3bw

DSP Engine
INT

MII/RMII
M CMC
Automotive
A MDC/MDIO
Connector
C Wake 802.1AS Time Stamp

CM
Termina on

(op
onal)
INH EN DVDD:1V
Vsleep: 3V3
Vreg AVDD=3.3V GND

VIO:3V3,2V5,1V8

Simplified Schematics

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4 Device Comparison Table

AVB CLOCK
PART FOOTPRINT
TC10 SUPPORT MACsec SUPPORT 802.1AS SUPPORT GENERATION
NUMBER COMPATIBLE
SUPPORT
DP83TC812x-Q1 Yes No No No Yes
DP83TC814x-Q1 No No No No Yes
DP83TC817S-Q1 Yes Yes Yes No Yes
DP83TC818S-Q1 Yes Yes Yes Yes Yes

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5 Application Information
The is a single-port 100Mbps Automotive Ethernet PHY. It supports IEEE 802.3bw and allows for connections
to an Ethernet MAC through MII, RMII, RGMII, or SGMII. When using the device for Ethernet applications, it is
necessary to meet certain requirements for normal operation. The following subsections are intended to assist in
appropriate component selection and required connections.

Note
Refer to SNLA453 Application Note for more information about the register settings used for
compliance testing. It is necessary to use these register settings to achieve the same performance as
observed during compliance testing.

5.1 MAC Security

DP83TC817S-Q1 integrates MAC Security, or MACsec (IEEE 802.1AE) hardware engine to perform line-rate
security (encryption and authentication) on both egress and ingress data paths. IEEE802.1AE is a Layer 2
network security protocol that prevents a range of attacks including: denial of service, intrusion, man-in-the-
middle, and eavesdropping. The block diagram below shows the major MACsec blocks within the PHY.

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Host SoC/MAC
Supplicant Secured db
( MKA Client/802.1x) · CAN
· CKN

MDIO/MDC for
MACsec, SAK config xMII

xMII
Uncontrolled
DP83TC817 PHY Rx Port

Buffering
Classication for IPG Flow Control Buffer
Expansion

Egress Ingress

· SecTAG · Validate SecTAG

· Encrypt Payload · Authenticate
· Integrity (ICV) · Decrypt Payload

Flow Control Classication

Uncontrolled
Tx Port
Egress Ingress

Figure 5-1. MACsec Block Diagram

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5.2 Time Syncronization

The DP83TC817S-Q1 integrates IEEE 1588v2/802.1AS timestamping and other additional hardware engines to
offer +/-5ns synchronization accuracy.
The DP83TC817S-Q1 is also capable of providing a high quality time synchronized clock signal to achieve
system level synchronization for ADAS sensor data synchronisation, Corner RADAR Chirp synchronisation, 1
pps signal for LiDAR, V2X, etc.

Real Time Acons

Microcontroller
or Microprocessor GPIO

Clock
Applica
on IEEE 802.1AS Clock
Code

MDIO
802.1AS Code 802.1AS Control

OS

MAC

MII / RMII/ RGMII / SGMIII

IEEE 802.1AS
Packet Detec on
and Processing

PHY

DP83TC817/818

LAN

Figure 5-2. DP83TC817 Example PTP System Application

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5.3 TC10 Sleep Wake-up

DP83TC817 is a 100BASE-T1 Ethernet PHY with TC-10 power saving feature with the following features.
• Open Alliance TC10 compliant
• Sleep request feature to shut down Ethernet network to save power
• 8µA (Typical, 27 °C), 20μA (Maximum, 125 °C) sleep current
• Wake forwarding feature for Ethernet network wake-up
• Fast Wake-up
This block diagram shows an example of how TC10 can be implemented in an automotive system. First, the
wake up request originates over active link and then the wake up pulse is forwarded over passive link. The wake
up request and pulses are exchanged over the Ethernet cable without needing dedicated wake up wire.

Figure 5-3. TC10 ADAS System Use Case Example

This block diagram shows the system level integration of DP83TC817 to support the TC10 sleep/wake-up
feature.

VBAT VREG
CORE
EN

PMIC
VREG VSLEEP (3.3V) VDDA
SLEEP VDDIO/MAC
10k

EN
VDD1P0
GND
INH
(3.3V) MII/RGMII/ MAC
RMII/SGMII Voltage
MDI DP83TC81x-Q1 MDC/MDIO
100BASE-T1 CPU/MPU
Ethernet PHY MAC
WAKE
Remote wake (3.3V)
over MDI

10k

GND
To other PHYs for
WAKE forwarding

Figure 5-4. System Block Diagram

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5.4 DP83TC817EVM-MC and Software Support

DP83TC817EVM-MC

The DP83TC817EVM-MCsupports 100-Mbps speed and is IEEE 802.3bw compliant. This evaluation board
is a media converter from 100Base-TX to 100Base-T1. There is an onboard MSP430F5529 for MDIO/MDC
register access with the USB2MDIO and DIEP graphical user interface tools. DP83867 is provided for copper
(100BASE-TX) support using RGMII MAC interface.

Figure 5-5. DP83TC817EVM-MC

Features:
• TC10 Support
• Jumpers to customize PHY strap settings
• Option to supply external reference clock
• Additional test points for debug
• Status LEDs
– Link
– Link + Activity
– Power-On
• EVM User's Guide for reference

New DIEP Debug Interface Experience

DIEP offers all your Ethernet PHY debug needs in one place including MDIO bus serial management, device
control registers, access to both extended registers and standard registers, and the ability to save data read
and run script text files.
• NEW restructured navigation and register display
• NEW improved text script execution
Debug Interface for Ethernet PHY's (DIEP)

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6 Device and Documentation Support

TI is transitioning to use more inclusive terminology. Some language may be different than what you would
expect to see for certain technology areas.

6.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
6.3 Community Resources
6.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
6.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

6.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

7 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (April 2024) to Revision A (October 2024) Page

• Production Data Release....................................................................................................................................1

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8 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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8.1 Package Option Addendum

8.1.1 Packaging Information
Package Package Package Lead/Ball
Orderable Device Status 1 Pins Eco Plan 2 MSL Peak Temp 3 Op Temp (°C) Device Marking5 6
Type Drawing Qty Finish4
DP83TC817SRHARQ1 ACTIVE VQFN RHA 36 2500 RoHS & Green NIPDAU Level-3-260C-168 HR 40 to 125 817S

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 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

DP83TC817SRHARQ1 Active Production VQFN (RHA) | 36 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 817S
DP83TC817SRHARQ1.A Active Production VQFN (RHA) | 36 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 817S

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Nov-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DP83TC817SRHARQ1 VQFN RHA 36 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Nov-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DP83TC817SRHARQ1 VQFN RHA 36 2500 367.0 367.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
RHA 36 VQFN - 1 mm max height
6 x 6, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4228438/A

www.ti.com
 PACKAGE OUTLINE
RHA0036A SCALE 2.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

6.1
B A
5.9

PIN 1 INDEX AREA

6.1
5.9

0.1 MIN

(0.13)

SECTION A-A
A-A 40.000

1.0 TYPICAL
0.8
C

SEATING PLANE
0.05 0.08 C
0.00
2X 4
SYMM (0.2) TYP
EXPOSED
THERMAL PAD 10 18

9
19
(0.16)
TYP

SYMM 37
A A
2X 4 3.7 0.1

32X 0.5
1 27

0.31
PIN 1 ID 36 28 36X
0.19
0.5 0.1 C A B
36X
0.3 0.05
4225089/A 06/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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 EXAMPLE BOARD LAYOUT
RHA0036A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 3.7)
SYMM
SEE SOLDER MASK
36 28 DETAIL
36X (0.6)

36X (0.25) 1 27

(1.6)
32X (0.5) TYP

(0.625)
SYMM 37 TYP

(R0.05) TYP
(5.8)

( 0.2) TYP
VIA

9 19

10 18
(0.625) TYP
(1.6) TYP
(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X
0.07 MIN
0.07 MAX ALL AROUND
ALL AROUND
METAL UNDER
METAL EDGE SOLDER MASK

EXPOSED METAL
SOLDER MASK EXPOSED SOLDER MASK
OPENING METAL OPENING

NON SOLDER MASK

DEFINED SOLDER MASK DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4225089/A 06/2019
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

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 EXAMPLE STENCIL DESIGN
RHA0036A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(1.25)
TYP
36 28

36X (0.6)

36X (0.25) 1 27

32X (0.5)
(1.25) TYP

SYMM 37
(5.8)

(R0.05) TYP

9 19
9X ( 1.05)

10 18
SYMM

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL
SCALE: 15X

EXPOSED PAD 37
72% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4225089/A 06/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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