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Dte Model Answersheets Combined

The document outlines the syllabus and examination structure for the Digital Techniques subject in the Diploma in AIML Engineering program at Zeal Polytechnic, Pune. It includes model answers and marking schemes for various MSBTE examinations from Winter 2018 to Summer 2024. Key topics covered include logic gates, Boolean expressions, multiplexers, flip-flops, and various digital circuit designs.

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Dte Model Answersheets Combined

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Zeal Education Society’s

ZEAL POLYTECHNIC, PUNE.

NARHE │PUNE -41 │ INDIA

SECOND YEAR (SY)

DIPLOMA IN AIML ENGINEERING

SCHEME: K SEMESTER: III

NAME OF SUBJECT: DIGITAL TECHNIQUES

SUBJECT CODE: 313302

MSBTE QUESTION PAPERS & MODEL ANSWERS

1. MSBTE WINTER- 18 EXAMINATION
2. MSBTE SUMMER- 19 EXAMINATION
3. MSBTE SUMMER -23 EXAMINATION
4. MSBTE WINTER -23 EXAMINATION
5. MSBTE SUMMER-24 EXAMINATION
MAHARASHTRASTATE BOARD OF TECHNICAL EDUCATION
(Autonomous)
(ISO/IEC - 27001 2013 Certified)

MODEL ANSWER
WINTER 18 EXAMINATION
Subject Title: Digital Techniques Subject Code:

Important Instructions to examiners:

1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme.
2) The model answer and the answer written by candidate may vary but the examiner may try to assess the
understanding level of the candidate.
3) The language errors such as grammatical, spelling errors should not be given more Importance (Not applicable for
subject English and Communication Skills.
4) While assessing figures, examiner may give credit for principal components indicated in the figure. The figures
drawn by candidate and model answer may vary. The examiner may give credit for any equivalent figure drawn.
5) Credits may be given step wise for numerical problems. In some cases, the assumed constant values may vary and

6) In case of some questions credit may be given by judgement on part of examiner of relevant answer based on

7) For programming language papers, credit may be given to any other program based on equivalent concept.

Q. Sub Answer Marking

No. Q.N. Scheme
Q.1 Attempt any FIVE of the following : Total Marks
10
a) Write the radix of binary,octal,decimal and hexadecimal number system. 2M
Ans: Radix of: Binary 2 ½ M each

Octal - 8

Decimal - 10

Hexadecimal -16

b) Draw the circuit diagram for AND and OR gates using diodes. 2M

Ans: 1 M each
Diode AND gate :Diode OR gate :

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c) Write simple example of Boolean expression for SOP and POS. 2M

Ans: SOP form: 1 M each

(any proper
example can
be
considered)
POS form:

d) State the necessity of multiplexer. 2M

Ans: Necessity of Multiplexer:

2 M(any two
It reduces the number of wires required to pass data from source to proper
destination. points)

For minimizing the hardware circuit.

For simplifying logic design.

In most digital circuits, many signals or channels are to be transmitted,

and then it becomes necessary to send the data on a single line
simultaneously.

Reduces the cost as sending many signals separately is expensive and

requires more wires to send.

e) Draw logic diagram of T flip-flop and give its truth table. 2M

Ans: Note: Diagram Using logic gates with proper connection also can be 1M (any one
consider. diagram)
Logic Diagram:

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Truth Table:

Input Output Operation Performed

Tn Qn+1
0 Qn No change

1 Qn Toggle

f) Define modulus of a counter. Write the numbers of flip flops required for 2M
Mod-6 counter.

Ans: Modulus of counter is defined as number of states/clock the counter Definition:

countes. 1M
The numbers of flip flops required for Mod-6 counter is 3. No. of FF-
1M
g) State function of preset and clear in flip flop. 2M

Ans: In the flip flop , when the power is switched on, the state of the circuit 1 M for each
is uncertain i.e. may be Q = 1 or Q = 0. function (
Hence, the function of preset is to set a flip flop i.e. Q = 1andthe table is
optional)
function of clear is to clear a flip flop i.e. Q = 0.

Page
MAHARASHTRASTATE BOARD OF TECHNICAL EDUCATION
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Q2 Attempt any THREE of the following : 12-Total

Marks
4M
a) Draw the block diagram of Programmable Logic Array.
Ans: Diagram :- 4M

Block diagram of Programmable Logic Array

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b) Convert 4M
(255)10 = (?)16 = (?)8
(157)10 = (?)BCD = (?) Excess3
Ans: (i) (255)10 = (FF)16 = (377)8

(255)10 = (FF)16 1M

(255)10 = (377)8
1M

(ii) (157)10 = (000101010111)BCD = (010010001010) Excess3

(157)10 = (000101010111)BCD

(000101010111)BCD = (010010001010) Excess3

c) Draw the symbol, truth table and logic expression of any one universal 4M
logic gate. Write reason why it is called universal gate.
Ans: (Note: Any one universal gate has to be considered.)
Universal Gates: NAND or NORSymbol:
1M

Truth table:
1M

Logic expression:
1M

NAND and NOR ga

implement any Boolean expression using these gates. 1M

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d) Minimize the following expression using K-Map. 4M

Ans: 1M
drawing k
map
1M
Representin
g function in
k map
1M
Grouping
1M Final
expression

Page
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Q. 3 Attempt any THREE: 12-Total

Marks
a) Compare TTL and CMOS logic families on the basis of following: 4M
(i) Propagation delay
(ii) Power Dissipation
(iii) Fan-out
(iv) Basic gate

Ans: NOTE :- ( Relevant points of comparison- 1 M for each point) 1 Marks

each point
Parameter CMOS TTL
Propagation delay 70-105 nsec/more than 10 nsec/Less than
TTL CMOS
Power Dissipation Less 0.1 mW/Less than More 10 mW/ More
TTL than CMOS
Fan-out 50/More than TTL 10/Less than CMOS

Basic gate NAND/NOR NAND

b) Describe the function of full Adder Circuit using its truth table, K-Map 4M
simplification and logic diagram.
Ans: ( Diagram- 1M,Truth table-1M, K-map- 1M,Logic diagram-1 M)

A full adder is a combinational logic circuit that performs addition between

three bits, the two input bits A and B, and carry C from the previous bit.

Block diagram : 1M

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Truth Table :

K-Map :-

Logic Diagram:

(Note: Logic Diagram using basic or universal gate also can be consider)

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c) Realize the basic logic gates, NOT, OR and AND gates using NOR gates 4M
only.
Ans:
( NOT GATE USING NOR GATE:1 M ) 1M

where, X = A NOR A
x=

(AND GATE USING NOR GATE:1.5 MARKS)

1.5M
___

___
________________

=A.B
= A.B

(OR GATE USING NOR GATE:1.5 MARKS)

1.5 M

Q=A+B
=A+B

d) Describe the working of JK flip-flop with its truth table and logic diagram. 4M
Ans: (Diagram-2 M,Working-1M,Truth table-1M)

Truth Table :- 1M

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Diagram :-

Working :-

The JK flip flop is basically a gated SR flip-flop with the addition of a clock
input circuitry that prevents the illegal or invalid output condition that can

additional clocked input, a JK flip-flop has four possible input combinations, 1M

J
of Q through the lower NAND K input is
Q through the upper NAND gate. As Q and Q are
always different we can use them to control the input. When both
inputs J and K gles

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Q. 4 A) Attempt any THREE of the following: 12-Total

Marks
a) Draw and explain working of 4 bit serial Input parallel Output shift 4M
register.
Ans: (Diagram:2M,Explaination:2M)

Diagram :-
2M

Explaination :-
DATA input pin of FFA then on the first
clock pulse the output of FFA and therefore the resulting QA will be set HIGH
2M
Assume now that the DATA input pin of FFA has returned LOW again to logic
-1-0.
The second clock pulse will change the output of FFA
output of FFBand QB D
on it from QA
the register to the right as it is now at QA.

of FFC ( QC ) and so on until the arrival of the fifth clock pulse which sets all
the outputs QA to QD
to FFA
The effect of each clock pulse is to shift the data contents of each stage one
place to the right, and this is shown in the following table until the complete
data value of 0-0-0-1 is stored in the register. This data value can now be read
directly from the outputs of QA to QD.
Then the data has been converted from a serial data input signal to a parallel
data output. The truth table and following waveforms show the propagation of
r from left to right as follows.

Basic Data Movement Through A Shift Register

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Clock Pulse No QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 0 0 0 0

b) Draw 16:1 MUX tree using 4:1 MUX. 4M

Ans: Diagram :-

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c) Calculate analog output of 4 bit DAC for digital input 1101. 4M

Assume VFS = 5V.
Ans: (Formula- 1M, Correct problem solving- 3M)

Formula :- 1M

VR = VFS

= 5(1x2-1 + 1x2-2+0x2-3+1x2-4)
= 5(0.5+O.25+0+0.0625)
= 4.0625 Volts

VFS = VR .
2 Marks for
Note (Since VR is not given find VR) VR and 2
marks for
Full Scale o/p mean Vo
b3 b2 b1 b0 = 1111

VFS = 5V

5 = VR .

VR = 5.33

For digital i/p b3 b2 b1 b0 = 1101

V0 = 5.33

V0 = 4.33V

d) 4M

Ans: (Each State and proof using table- 2M each)

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e) Design one digit BCD Adder using IC 7483

Ans: (Diagram:4M)

(Note: Labeled combinational circuit can be drawn using universal gate 4M

also)

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Q.5 Attempt any TWO of the following : Total Marks

12
a) 6M
(35)10 (5)10
Ans: Each step 3
Step 1 Obtain binary equivalent of (35)10& (5)10 Marks
of (5)10 .
i.e. (35)10 = (100011)2
(5)10 = (101)2

(5)10 = (000101)2 = 111010

+ 1
----------------------------------
(111011)2

Step -2 :

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Now add (100011)2 and (111011)2

100011
+ 111011
----------------------------
011110
Carry is generated so answer is in positive form, so will
discard the carry generated
Therefore final answer will be (011110)2 = (30)2

b) Design a 4 bit synchronous counter and draw its logic diagram. 6M

Ans: State Table:

2M-State
table

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Kmap:
2M-Kmap

2M-Logic
Logic Diagram:
Diagram

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c) Describe the working of Successive Approximation ADC. Define 6M

Resolution and conversion time associate with ADC.
Ans: Circuit Diagram:

2 Marks
Diagram

When the start signal goes low the successive approximation register
SAR is cleared and output voltage of DAC will be 0V. When start goes high 2 Marks
Explanation
the conversion starts.
After starts, during first clock pulse the control circuit set MSB bit so
SAR output will be 1000 0000. This is connected as input to DAC so output of
DAC is (analog output) compared with Vin input voltage. If VDAC is more than
Vin the comparator output Vsat, if VDAC is less than Vin, the comparator output
is +Vsat.
1 Marks
If output of DAC i.e. VDAC is + Vsat (i.e unknown analog input Each
voltage Vin> VDAC) then MSB bit is kept set, otherwise it is reset.
Consider MSB is set so SAR will contain 1000 0000.
The next clock pulse will set next bit i.e D6 a digital output of 1100 0000. The
output voltage of DAC i.e VDAC is compared with Vin, if it is + Vsatthe D6 bit is
kept as it is, but if it is Vsat the D6 bit reset.
The process of checking and taking decision to keep bit set or to reset is
continued upto D0.
Then the DAC input will be digital data equal to analog input.
When the conversation if finished the control circuits sends out an end
of conversion signal and data is locked in buffer register

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Resolution: The voltage input change necessary for a one bit change in the
output is called resolution.
Conversion Time: The conversion time is the time required for conversion
from an analog input voltage to the stable digital output

Circuit Diagram:

2 Marks
Diagram

Explanation:

DAC= Digital to Analog converter

EOC= End of conversion
SAR =Succesive approximation register
S/H= Sample and hold circuit
Vin= input voltage
Vref= reference voltage
The successive approximation Analog to Digital converter circuit typically
consisting of four sub circuits-
1. A sample and hold circuit to acquire the input voltage Vin.
2. An analog voltage comparator that compares Vin to the output of internal
DAC and outputs the result of comparison to successive approximation
register(SAR).
3. SAR sub circuits designed to supply an approximate digital code of Vin to
the internal DAC.
4. An internal reference DAC that supplies the comparator with an analog
voltage equivalent of digital code output of SAR for comparison with Vin.

The successive approximation register is initialized so that most significant bit

(MSB) is equal to digital 1. This code is fed into DAC which the supplies the
analog equivalent of this digital code Vref/2 into the comparator circuit for the
comparison with sampled input voltage. If this analog voltage exceeds Vin the
comparator causes the SAR to reset the bit, otherwise a bit is left as 1. Then the

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next bit is set to 1 and the same test is done continuing this binary search until
every bit in the SAR has been tested. The resulting code is the digital
approximation of the sampled input voltage and is finally output by DAC at
end of the conversion (EOC).

Resolution and conversion time associate with ADC-

Resolution:
It is the maximum number of digital output codes.
Resolution= 2^n
(OR) 1 Marks
It is defined as the ratio of change in the value of input analog voltage required each
to change the digital output by 1 LSB.

Conversion time:
The time difference between two instants i.e. 'to' where SOC signal is given as
input to the ADC and 't1' where EOC signal we get as output from ADC. it
should be small as possible.

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Q.6 Attempt any TWO of the following: Total Marks

12
a) Design 4 bit Binary to Gray code converter. 6M
Ans: 2M for truth
Truth Table for 4 bit Binary to Gray code converter table
Binary Input Gray output
B3 B2 B1 B0 G3 G2 G1 G0 1/2m for
0 0 0 0 0 0 0 0 each output
0 0 0 1 0 0 0 1 equation
0 0 1 0 0 0 1 1 2M for
0 0 1 1 0 0 1 0 realization
0 1 0 0 0 1 1 0 using gates
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-MAP FOR G3:

G3=B3

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K-MAP FOR G2:

= B3 XOR B2

K-MAP FOR G1:

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= B1 XOR B2

K-MAP FOR G0:

= B1 XOR B0

Diagram for 4 bit Binary to Gray code converter:

Note: Realization of output equations can be done using Basic or Universal

gates

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b) Compare the following (Any three points) 6M

i) Volatile with Non-volatile memory
ii) SRAM with DRAM memory

Ans:
Parameter Volatile memory Non-Volatile memory
definition Memory required Memory that will keep Any 3points
electrical power to keep storing its information (each 1
information stored is without the need of mark)
called volatile memory electrical power is
called nonvolatile
memory.
classification All RAMs ROMs, EPROM,
magnetic memories
Effect of power Stored information No effect of power
is retained only as on stored
long as power is on. information
applications For temporary For permanent
storage storage of
information

2. SRAM with DRAM memory

Parameter SRAM DRAM

Circuit configuration Each SRAM cell is Each cell is one
a flip flop MOSFET & a capacitor
Bits stored In the form of In the form of charges
voltage
No of components per More Less
cell
Storage capacity Less More
Refreshing It does not require It require refreshing.
refreshing
Cost It is expensive It is cheaper
Speed It is faster It is slower
comparatively

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c) Give block schematic of decade counter IC 7490. Design Mod-7 counter 6M

using this IC.
Ans:
1. block schematic of decade counter IC 7490-
2M block
schematic

Mod-7 means states are from o,1,2,3,4,5,6,0

Therefore we have to reset counter IC 7490 when QD,QC,QB,QA=0111
Design reset logic:
Output of reset circuit should be HIGH because R0(1) and R0(2) are active high inputs.
Therefore reset logic output should be low for states 0 to 6.

Output should be HIGH for states 7 onwards.

Truth table & K-map:

Truth
Table-1M
Kmap-1M
Logical Dig-
2M

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Expression for Y:

Y= QC QB QA + QD

Circuit is-

Logic Diagram:

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Important Instructions to examiners:

1) The answers should be examined by key words and not as word-to-word as given in themodel answer
scheme.
2) The model answer and the answer written by candidate may vary but the examiner may tryto assess the
understanding level of the candidate.
3) The language errors such as grammatical, spelling errors should not be given moreImportance (Not
applicable for subject English and Communication Skills.
4) While assessing figures, examiner may give credit for principal components indicated in thefigure. The
figures drawn by candidate and model answer may vary. The examiner may give credit for anyequivalent
figure drawn.
5) Credits may be given step wise for numerical problems. In some cases, the assumed constantvalues

In case of some questions credit may be given by judgement on part of examiner of relevant answer

7) For programming language papers, credit may be given to any other program based on equivalent
concept.
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
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Solution:

(11011)2 (11100)2
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Final
Answer-
1M
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Each
Gate
Design
1 Marks
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Truth
Table
2M
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Logic
Diagram
2M
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Fig 1:
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__________________________________________________________________________________________________
WINTER 19EXAMINATIONS

10-Total
Q.1 Attempt any FIVE of the following:
Marks

a) Convert (D8F) 16into binary and octal. 2M

Ans: 1M

b) Draw symbol, Truth table and logic equation of Ex-OR gate. 2M

Ans: ½M

½M
Logic Equation = A + B OR
Truth Table:
Inputs Output 1M
A B Y

0 0 0
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0 1 1

1 0 1

1 1 0

c) 2M
st
Ans: 1st-1M
Theorem complement of sum is equal to product of their individual complements. 2nd -1M
OR =
nd
theorem
Complement of product is equal to sum of their individual complements.
OR = +
d) Convert the following expression into standard SOP form. 2M
Y= AB+ A + BC
Ans: Y = AB+ A + BC 2M
Total variable ABC
1st Product term = AB ( C is missing)
2nd Product term = A ( B is missing)
3rd Product term = BC ( A is missing)

Y= AB(C+ ) A (B+ ) + BC(A+ )

Y= ABC + AB + AB + A +ABC + BC
Y= ABC + AB + A + BC Standard SOP Form
e) Draw symbol and write truth table of D and T Flip Flop. 2M

Ans: (Note: Symbol with other triggering method also can be consider) 1M
Symbol

1M
Truth
table

f) Write down number of flip flops are required to count 16 clock pulses. 2M

Ans: No of states= no.of clock pulses = 16 2M

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2n =m
n = no.of flip flops requried
m= no.of states
2n = 16
n=4
4 flip flops are required to count 16 clock pulse.
g) List the types of DAC 2M

Ans: 1) Binary weighted DAC 1M each

2) R 2R ladder network DAC

12-Total
Q.2 Attempt any THREE of the following:
Marks

a) 4M
(52)10 (65)10
Ans: Conversio
n-1M each

Complime
nt-1M

Final
answer-
1M

b) Simplify the following Boolean Expressionand Implement using logic gate. 4M

AB + AB D + ABC + ABCD
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Ans: 2M

c) Minimize the four variable logic function using K map. 4M

F(A,B,C,D)
Ans: Kmap
with place
value-1M

Pair-1M

Answer-
2M

Implement the following function using demultiplexer.

d) f1 4M
f2
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Ans: 4M

12-Total
Q.3 Attempt any THREE of the following:
Marks

Realize the following logic expression using only NAND gates.

a) (i) OR 4M
(ii) AND
(iii)NOT
Ans: (i)OR 1½ M

(ii)AND

1½ M

(ii)NOT
1M

(out put A bar)

Ans: Truth Table for 4 bit Binary to Gray code converter 2M Truth
Binary Input Gray Output table
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1 Note:
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0 Kmap is
1 0 0 0 1 1 0 0 optional
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
K-MAP FOR G3:

2M
Logical
diagram

G3=B3
K-MAP FOR G2

G2 = B2 + B3
=B3 XOR B2
K-MAP FOR G1:
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G0 = B0+B1
= B1 XOR BO

(Note: Realization of output equation can be done Basic or Universal)

c) Describe the working of JK flip flop with truth table and logic Diagram. 4M

Ans: logic Diagram: 1M

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Working:
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry 2M
that prevents the illegal or invalid output condition that can occur when both inputs S and R
input, a JK flip-flop has four

Both the S and the R inputs of the previous SR bistable have now been replaced by two
inputs called the J and K inputs, respectively after its inventor Jack Kilby. Then this equates
to: J = S and K = R.
The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-
input NAND gates with the third input of each gate connected to the outputs at Q and Q.
This cross coupling of the SR flip-flop allows the previously invalid condition of S
and R
interlocked.
J
Of Q through the lower NAND K input is inhibited by
Q through the upper NAND gate. As Q and Q are always different we can
use them to control the input. When both
inputs J and K
Describe the working of 4 bit SISO (serial in serial out) shift register with diagram
d) 4M
and waveform if input is 01101.

Ans: Diagram:(use SR or JK or D type flip flop) 1M

Working:
The DATA leaves the shift register one bit at a time in a serial pattern, hence the 1½ M
name Serial-in to Serial-Out Shift Register or SISO.
The SISO shift register is one of the simplest of the four configurations as it has only three
connections, the serial input (SI) which determines what enters the left hand flip-flop, the
serial output (SO) which is taken from the output of the right hand flip-flop and the
sequencing clock signal (Clk). The logic circuit diagram below shows a generalized serial-
in serial-out shift register, Output of FFA is Q4,FFB Q3,FFC Q2 and FFD is Q1
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Waveform:(Input is 01101) 1½ M

Q.4 Attempt any THREE of the following : 12-Total

Marks

a) Design a full Adder using Truth Table and K-map. 4M

Ans: A full adder is a combinational logic circuit that performs addition between three bits, the
two input bits A and B, and carry C from the previous bit.

Truth Table:

Truth
table 1½
M
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Logical diagram:

1½ M

b) Describe the working of ring counter using D flip flop with diagram and waveforms. 4M

Ans: Diagram:1
Diagram:
½M

Waveforms:
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Waveform
:1½ M

Working:
The ring counter is a cascaded connection of flip flops, in which the output of last flip flop
is connected to input of first flip flop. In ring counter if the output of any stage is 1, then its
reminder is 0. The Ring counters transfers the same output throughout the circuit.
That means if the output of the first flip flop is 1, then this is transferred to its next stage i.e.
2nd flip flop. By transferring the output to its next stage, the output of first flip flop
becomes 0. And this process continues for all the stages of a ring counter. If we use n flip

Explainati
on:1 M
c) Draw block diagram of programmable logic Array. 4M

Ans: Diagram: 4M

d) Compare the following:

(i) Volatile with Non Volatile. 4M
(ii) EPROM with EEPROM.
(i)Volatile with Non Volatile. 2M (Any
Parameter Volatile memory Non-Volatile memory two point
definition Memory required electrical power to Memory that will keep 1 M each)
keep information stored is called storing its information
Ans: volatile memory without the need of
electrical power is called
nonvolatile memory.
classification All RAMs ROMs, EPROM, magnetic
memories
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Effect of power Stored information is retained only as No effect of power on stored
long as power is on. information
applications For temporary storage For permanent storage of
information
1M(Any
ii)EPROM with EEPROM.
Parameter EPROM EEPROM. two point
Stands for Erasable Programable Read- Electrically Erasable each)
Only Memory. Programmable Read-Only
Memory.
Basic Ultraviolet Light is used to EEPROM contents are
erase the content of erased using electrical
EPROM. signal.
Appearance EPROM has a transparent EEPROM are totally
quartz crystal window at the encased in an opaque plastic
top. case.
Technology EPROM is modern version EEPROM is the modern
of PROM. version of EPROM.
e) Describe the working principal of successive approximation ADC. 4M
Ans: Note: Other relevant diagram and explanation also can be considered.
Diagram:

Working:
The successive approximation A/D converter is as shown in fig. An analog voltage (Va) is
constantly compared with voltage Vi, using a comparator. The output produced by
comparator (Vo) is applied to an electronic Programmer. If Va=Vi, then Vo=0 & then no
conversion is required. The programmer displays the value of Vi in the form of digital O/P.
But if Va Vi, then the O/P is changed by the programmer. If Va> Vi, then value of Vi is
increased by 50% of earlier value. But if Va< Vi, then value of Vi is decreased by 50% of
earlier value. 2M
This new value is converted into analog form, by D/A converter so as to compare it with Va
again. This procedure is repeated till we get Va=Vi. As the value of Vi is changed
successively, this method is called as successive-approximation A/D converter.
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When the starts signal goes low the successive approximation register SAR is cleared and
output voltage of DAC will be 0v. When start goes high the conversion starts.
After starts, during first clock pulse the control circuit set MSB bit so SAR output wiil be
1000 0000. This is connected as input to DAC so output of DAC is compared with Vin
input voltage. If VDAC is more than Vin the comparator output Vsat, if VDAC is less than
Vin, the comparator output is +Vsat.
If output of DAC i.e. VDAC is +Vsat (i.e. unknown analog input voltage Vin> VDAC) then
MSB bit is kept set, otherwise it is reset.
Consider MSB is set so SAR will contain 1000 0000.
The next clock pulse will set next bit i.e. D6 bit is kept as it is, but if it Vsat the D6 bit
reset. The process of checking and taking decision to keep bit set or to reset is continued
upto D0. Then the DAC input will be digital data equal to analog input.
When the conversion is finished the control circuits sends out an end of conversion signal
and data is locked in buffer register.

Q.5 Attempt any TWO of the following : 12- M

(i)Convert the following binary number (11001101)2 into Gray Code and Excess-3
(a) 2M
Code.
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Ans: 1M each
conversion

(ii)Perform the BCD Addition. 2M

(17)10 + (57)10
Ans: (17)10 0001 0111
(57)10 + 0101 0111 -------(1/2 M)
0110 1110
Valid Invalid
BCD BCD ----------(1/2 M)
ADD 0110 TO Invalid BCD
½ Each
1 11
step
0110 1110
+ 0000 0110
01110100 -----------(1/2 M)
7 4
-----------(1/2 M)

(iii)Perform the binary addition.

2M
2 2

Ans: 10110.110)2 (1001.10)2 = (100000.010)2 2M

11111
10110.110
+ 1001.10
100000.010
(b) Design a 4bit ripple counter using JK flip flop, with truth table and waveforms. 6M

Ans: 2M
Circuit Diagram:
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Truth Table:
2M

Timing Diagram / Waveforms:

Calculate the analog output for 4 bit weighted register type DAC for inputs
(c) (i) 1011 6M
(ii) 1001
Assume (Vfs) full scale range of voltage is 5V
Ans: Given: 3M each
VR = Vfs = 5V
Formula Used:
Vo = - VR (B1.2-1 + B2.2-2 + B3.2-3 + B4.2-4 )
1. 1011
Vo = - VR (B1.2-1 + B2.2-2 + B3.2-3 + B4.2-4 )
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= - 5 (1*1/2 + 0 + 1*1/23 + 1 *1/24 )
= - 5 (1*1/2 + 1*1/8 + 1 *1/16)
= - 5 (0.5 + 0.125 + 0.0625) = 3.4375V
Vo = 3.4375 V
2. 1001
Vo = - VR (B1.2-1 + B2.2-2 + B3.2-3 + B4.2-4 )
= - 10 (1*1/2 + 0 + 0 + 1 *1/24 )
= - 10 (1*1/2 + 0 + 0 + 1 *1/16)
= - 10 (0.5 + 0.0625) = 2.8125V
Vo = 2.8125 V
12-Total
Q.6 Attempt any TWO of the following:
Marks

Compare TTL, CMOS and ECL logic family on the following points.
(i) Basic Gates
(ii) Propogation dealy
(a) (iii)Fan out 6M
(iv) Power Dissipation
(v) Noise immunity
(vi) Speed power product
Ans:
1M Each
Parameter TTL CMOS ECL
parameter

Basic gates NAND NOR/NAND OR/NOR

Propagation delay 10 70-105 2

Fan out 10 50 25

Power Dissipation 10mW 1.01mW 40-55mW

Noise Immunity 0.2V 5V 0.25V

Speed Power 100 0.7 100

Product

(b) Design a BCD adder using IC 7483. 6M

Ans: (Note: Labeled combinational circuit can be drawn using universal gate also)
1) To implement BCD adder we require:
-bit binary adder for initial addition

-bit adder to add 0110201102 in the sum if sum is greater than 9 or carry is 1
2) The logic circuit to detect sum greater than 9 can be determined by simplifying the
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Boolean expression of given truth Table.

Truth
Table: 2M

K-Map:
1M

3) Y=1 indicates sum is greater than 9. We can put one more term, C_out in the above
expression to check whether carry is one.
4) If any one condition is satisfied we add 6(0110) in the sum.
5) With this design information we can draw the block diagram of BCD adder, as shown in
figure below.

Circuit
Diagram:
3M
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(c) Design a 3 bit synchronous counter using JK Flip Flop. 6M

Ans: 1) Step1: 2M
Construct JK state table with corresponding excitation table:
Output State Transitions

Present Next state

State
Q2 Q1 Q0 Flip-flop inputs
Q2 Q1 Q0
J2 K2 J1 K1 J0 K0
000 001 0X 0X 1X

001 010 0X 1X X1

010 011 0X X0 1X

011 100 1X X1 X1

100 101 X0 0X 1X

101 110 X0 1X X1

110 111 X0 X0 1X

111 000 X1 X1 X1

State Table and Corresponding Excitation Table (d=don't care)

Step3:
Draw the complete design as below:
2M

Note: It can also be designed using any other Flip Flop.

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SUMMER 2023 EXAMINATION

Model Answer Only for the Use of RAC Assessors
Subject Name: DIGITAL TECHNIQUES Subject Code: 22320
Important Instructions to examiners:
1) The answers should be examined by key words and not as word-to-word as given in the model answer
scheme.
2) The model answer and the answer written by candidate may vary but the examiner may try to assess the
understanding level of the candidate.
3) The language errors such as grammatical, spelling errors should not be given more Importance (Not
applicable for subject English and Communication Skills.
4) While assessing figures, examiner may give credit for principal components indicated in the figure. The
figures drawn by candidate and model answer may vary. The examiner may give credit for any equivalent
figure drawn.
5) Credits may be given step wise for numerical problems. In some cases, the assumed constant values may

6) In case of some questions credit may be given by judgement on part of examiner of relevant answer based

7) For programming language papers, credit may be given to any other program based on equivalent concept.
8) As per the policy decision of Maharashtra State Government, teaching in English/Marathi and Bilingual
(English + Marathi) medium is introduced at first year of AICTE diploma Programme from academic year
2021-2022. Hence if the students write answers in Marathi or bilingual language (English +Marathi), the
Examiner shall consider the same and assess the answer based on matching of concepts with model
answer.

Q. Sub Answer Markin

No. Q.No g
Scheme
1. Attempt any FIVE of the following: 10M

a) State the base of following number system: 2M

Decimal , binary, octal, hexadecimal
ANS Decimal has base : 10 ½M
each
Binary has base: 2
Octal has base : 8
Hexadecimal has base : 16

b) Define counter: 2M

ANS Counter is a device which stores and sometimes displays the number of times a
particular event or process has occurred in relationship to a clock.

c) Give any two application of comparator. 2M

ANS 1. Comparators are used in first central processing unit and micro controllers.
2. Ti is used in ADC to major digitize analog signals.
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3. It is used threshold detector zero processing detector.

d) Draw the symbol of D flipflop and write its truth table. 2M

ANS 1M
Symbol
, 1M
Truth
Table

e) Name the types of RAM 2M

ANS There are two main types of RAM: 1M

each
1. Dynamic RAM (DRAM)
2. Static RAM (SRAM)

f) Define and draw logic symbol of demultiplexer. 2M

ANS Demultiplexer is combinational logic circuit and it does exactly the opposite to that of a 1M
Multiplexer. definition
OR
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Demux is a one-to-many circuit. 1M
OR symbol
A Demultiplexer is a combinational logic circuit that receives the information on a

lines.
Logic symbol of demultiplexer :

g) List the basic types of shift register. 2M

ANS Basic shift registers are classified as: ½ M

each
1. Left shift Register ,
2. Right shift register,
3. Universal shift register
4. Bidirectional shift register
OR
1. Serial-in/serial-out.
2. Parallel-in/serial-out.
3. Serial-in/parallel-out.
4. Parallel-in/parallel-out.

2. Attempt any THREE of the following: 12M

a) Convert the given binary into decimal, octal, hexadecimal and gray code 4M
(10110101)2

ANS i) (10110101)2 = (?)10 1M

each
= 1*27 + 0*26 +1*25+1*24 + 0*23 +1*22 + 0*21 +1*20 convers
ion
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= 128 + 0 + 32 + 16 + 0 + 4 + 0 + 1
(10110101)2 = ( 181)10
ii) (10110101)2 = (?)8
01 0 1 1 0 1 0 1 = (265)8

iii) (10110101)2 = (?)16

1 0 1 1 0 1 0 1 = (B5) 16
iv) (10110101)2 = (?)gray
(1 0 1 1 0 1 0 1)2
(1 1 1 0 1 1 1 1)gray

b) 4M
Draw the block diagram of BCD to 7 segment decoder using IC 7447. Write
truth table of it.
ANS 2M
Block
diagra
m , 2M
Truth
Table
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c) Define PLA. Draw its block diagram. 4M

ANS Programmable Logic Array PLA: 2M

PLA is a programmable logic device that has both Programmable AND array & Explan
Programmable OR array. Hence, it is the most flexible PLD. ation &

The block diagram of PLA is shown in the following figure.

2M
block
diagra
m

Here, the inputs of AND gates are programmable. That means each AND gate has both
normal and complemented inputs of variables. So, based on the requirement, we can
program any of those inputs. So, we can generate only the required product terms by
using these AND gates.

d) Implement full adder using two half adder. 4M

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ANS 4M

Figure: Full adder using two half adder.

3. Attempt any THREE of the following: 12M

a) 4M
Draw the OR gate and NOR gate using NAND gate only.
ANS OR gate using NAND gate 2m for
each
diagra
m

b) 4M
Compare TTL, ECL and CMOS logic families. (any four points)
ANS 1 m for
Parameter TTL CMOS ECL each
comparis
Basic gates NAND NOR/NAND OR/NOR on

Propagation delay 10 70-105 2

Fan out 10 50 25

Power Dissipation 10mW 1.01mW 40-55mW

Noise Immunity 0.2V 5V 0.25V

c) 4M
Draw 4 bit twisted ring counter and explain working with truth table and
waveforms.
ANS The Twisted Ring Counter refers to as a switch-tail ring Counter. The complimented 1 m
diagram
output of last flip flop is connected to the input of first flip-flop
1m
explanati
on

1m truth
table

1m
wavefor
m

A 4-
thereby producing an 8-bit pattern. As the inverted output Q is connected to the input D
this 8-
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d) 4M
A combinational circuit is defined as F1 = Em (3, 5, 7) and F2 = Em(4, 5, 7).
Implement the circuit with a PLA having 3 inputs, 3 product terms and 2
outputs.

ANS 1m truth
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F2 can be drawn as: table

2m K
map

1m
diagram

Solving using the K-Map

a) 4M
Define following terms:
i) Fan-in

ii) Fan-out
iii) Power dissipation
iv) Noise margin

ANS 1 m for
i)Fan in each
definatio
Fan in is the number of inputs to a gate. For a two-input gate, fan in is 2 and for a n
3-input gate, fan in is 3 and so on.
ii) Fan out
Fan out is the maximum number of gates that can be driven by a logic gate.
iii)Power Dissipation
For operation of every electronic circuit, a certain amount of electric power is
required.
Out of supplied power, some power is dissipated in electronic circuits. This is due
to wastage of power across electronic components. i.e. Power dissipation is
nothing but wastage of power across electronic components or devices within a
Circuit. Power dissipation of a circuit is expressed in terms of milliwatt (mW).

iv)Noise margin
Unwanted signal is called noise. Stray electric or magnetic fields may induce noise in
the input to the digital circuits. Due to noise, input voltage may drop below VIH or
may rise above VIL. Both the circumstances will result in undesired operations of the
digital circuit.
Every circuit should have the ability to tolerate the noise signal. This ability of
tolerating noise signals is called noise immunity. Measure of noise immunity is called
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b) 4M
Draw the block diagram of digital comparator IC 7485 and explain with the
help of truth table.
ANS Diagra
m- 2M

Truth
table-
2M

2-bit comparator compares two binary numbers, each of two bits and produces their
relation such as one number is equal or greater than or less than the other. The first
number A is designated as A = A1A0 and the second number is designated as B = B1B0. Explana
This comparator produces three outputs as A>B.A = B and A<B tion
1M
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c) Design 32: 1 multiplexer using 8: 1 multiplexer. 4M

ANS 4M for
Correct
design

n:1=32:1
therefore n=32
2m = n = 32 therefore m=5, so number of select inputs are A,B,C,D,E
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d) 4M
Explain the working of master salve JK flipflop with truth table and logic
diagram.
ANS The Master-Slave JK Flip Flop 2M-
DIAGR
AM

the in

p now responds to

-to-
-to-Lo

flip flop edge or pulse-triggered.

to the output on the falling-edge of the clock signal. In other words, the Master-Slave JK

signal.

the input conditi

nds to
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-to-
-to-
transiti
flip flop edge or pulse-triggered.

1M-
to the output on the falling-edge of the clock signal. In other words, the Master-Slave JK EXPLA
NATIO
signal. N

1M-
TRUTH
TABLE

e) 4M
Write applications of ADC and DAC.,
ANS Applications of ADC converter 2M

They are used in Audio/Video devices. ANY

They are used in Cell Phones. TWO

They are used in RADAR processing, digital oscilloscopes.

They are widely used in CMOS Image sensors for mobile applications.

They are used in Medical Instrumentation and medical imaging

Applications of DAC converter 2M

ANY
To convert digital command signal into analog example motor speed control TWO
As counter ADC or successive approximation type ADC
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For displaying information on CRT or XY plotter
In computers
In electronic equipment such as curve tracer

5. Attempt any TWO of the following: 12M

a) 6M
Design mod-6 counter using IC 7490 and explain its design
with working.

ANS Clock is given to clock input A. Output QA is connected to clock input B. To reset the 3M for
counter after counting the first six states from 0 to 5, the counter outputs Qc and QB MOD 6
counter
should be connected to the reset inputs. using IC
7490
Diagram

3M
working

b) Explain classification of memories. What is flash memory? 6M

3M for
flash
memory

Flash Memory is nonvolatile RAM memory

2. It can be Electrically erased and reprogrammed
3. Flash memory can be written into blocks size rather than byte. It is easy to update.
4. It is faster than EEPROM as EEPROM edit the data at Byte level.
5. As large block of data can be erased at one time (or flash)thus called as flash memory.
6. Features: High speed, low operating voltage and low power consumption

i) State the rules of BCD addition. 6M

c) ii) Perform BCD addition of:
(972)10 + (348)10

ANS Rules of BCD Addition: 3M for

rules of
1. If sum is less than or equal to 9 with carry equal to 0, then the sum is in proper BCD BCD
form and requires no correction. addition

to add decimal 6 or BCD 0110 to get the correct BCD.

a) 6M
Design synchronous decade counter using D' flipflop.
ANS 1M for
each
step (4
steps:4
Marks)
2M for
circuit
using D
Flip
Flop
(Step 5)
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Subject Name: DIGITAL TECHNIQUES Subject Code: 22320
___________________________________________________________________________________________
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
(Autonomous)
(ISO/IEC - 27001 - 2013 Certified)
Subject Name: DIGITAL TECHNIQUES Subject Code: 22320
___________________________________________________________________________________________
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
(Autonomous)
(ISO/IEC - 27001 - 2013 Certified)
Subject Name: DIGITAL TECHNIQUES Subject Code: 22320
___________________________________________________________________________________________

6M
b) i) Minimize the following expression using K-map.

ii) Realize the minimized expression using basic gates.

3M for
minimize
d
expressio
n using
basic
gates

c) Reduce following boolean expressions using boolean laws. 6M

i) Y= A B + A B + A B + A B

ii) Y=A B C + A B C + ABC

iii) Y=ABC + A B C + ABC

ii)

iii)
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
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Subject Name: DIGITAL TECHNIQUES Subject Code: 22320
___________________________________________________________________________________________
22320
23124
3 Hours / 70 Marks Seat No.

Instructions – (1) All Questions are Compulsory.

(2) Answer each next main Question on a new page.
(3) Illustrate your answers with neat sketches wherever
necessary.
(4) Figures to the right indicate full marks.
(5) Assume suitable data, if necessary.
(6) Mobile Phone, Pager and any other Electronic
Communication devices are not permissible in
Examination Hall.
Marks

1. Attempt any FIVE of the following: 10

a) List the octal and hexadecimal numbers for decimal number
0 to 15.
b) Convert (159)10 = ( ? )8
Convert (380)10 = ( ? )16
c) Draw symbol, truth table of NAND gate.
d) Define min-term and max-term with respect to K-map.
e) List the types of DAC.
f) State two features of ADC IC0809.
g) List the types of semiconductor memories.

P.T.O.
22320 [2]
Marks
2. Attempt any THREE of the following: 12
a) Perform the subtraction using 2’s complement methods.
(10110)2 – (11010)2
b) Explain the following characteristics with respect to logic
families -
i) Power dissipation
ii) Fan-in and fan-out
iii) Noise margin
iv) Speed of operation
c) Draw logic diagram of half adder using K-map simplification
and write truth table.
d) Describe the working of J-K flip-flop and state the race
around condition.
e) Give classification of memory and compare RAM and ROM.
(Any four points)

3. Attempt any FOUR of the following: 16

a) Convert (53)10 = (BCD)
(34)10 = (Excess-3)
(100111)2 = (Gray)
(11010)2 = (2’s complement)
b) State and explain De-Morgan’s theorems.
c) Draw 16 : 1 mux tree using 4 : 1 mux.
d) Describe the operation of R-S flip-flop using NAND gate.
e) Describe the operation of 4 bit serial in serial out shift
register.
f) Draw and explain the block diagram of Programmable Logic
Array (PLA).
22320 [3]
Marks
4. Attempt any TWO of the following: 16
a) Design 1 : 8 demultiplexer using 1 : 4 demultiplexer. Also write
truth table.
b) Explain the role of counters in digital circuits and design
Mod - > counter using IC 7490.
c) Draw and explain the block diagram of dual slope ADC. Also
write it’s specifications.

5. Attempt any TWO of the following: 16

a) Design basic logic gates using NAND and NOR gate.
b) Minimize the following expression using K-map.
f (A, B, C, D) = ∑ m (0, 1, 2, 4, 5, 7, 8, 9, 10)
Also explain SOP and POS form.
c) Draw and explain 4-bit universal shift register. Also explain
the necessity of register in digital circuits.
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
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(ISO/IEC - 27001 - 2013 Certified)
__________________________________________________________________________________________________
WINTER – 2023 EXAMINATION
Model Answer – Only for the Use of RAC Assessors

Subject Name: Digital Techniques Subject Code: 22320

Important Instructions to examiners: XXXXX
1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme.
2) The model answer and the answer written by candidate may vary but the examiner may try to assess the
understanding level of the candidate.
3) The language errors such as grammatical, spelling errors should not be given more Importance (Not applicable for
subject English and Communication Skills.
4) While assessing figures, examiner may give credit for principal components indicated in the figure. The figures drawn
by candidate and model answer may vary. The examiner may give credit for any equivalent figure drawn.
5) Credits may be given step wise for numerical problems. In some cases, the assumed constant values may vary and
there may be some difference in the candidate’s answers and model answer.
6) In case of some questions credit may be given by judgement on part of examiner of relevant answer based on
candidate’s understanding.
7) For programming language papers, credit may be given to any other program based on equivalent concept.
8) As per the policy decision of Maharashtra State Government, teaching in English/Marathi and Bilingual (English +
Marathi) medium is introduced at first year of AICTE diploma Programme from academic year 2021-2022. Hence if
the students write answers in Marathi or bilingual language (English +Marathi), the Examiner shall consider the same
and assess the answer based on matching of concepts with model answer.

Sub
Q. Marking
Q. Answer
No. Scheme
N.
1 Attempt any FIVE of the following: 10 M
a List the octal and hexadecimal numbers for decimal number 0 to 15. 2M
Ans Decimal Octal Hexadecimal 1M for each

0 0 0

1 1 1

2 2 2

3 3 3

4 4 4

5 5 5

6 6 6

7 7 7

8 10 8

9 11 9

10 12 A

Page No: 1/20

12 14 C

13 15 D

14 16 E

15 17 F

i) Convert (159)10 = ( ? )8 2M
b
ii) Convert (380)10 = ( ? )16
Ans
1M

c Draw symbol, truth table of NAND gate. 2M

Ans 1M for
symbol and
1M for truth
table

Page No: 2/20

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d Define min-term and max-term with respect to K-map. 2M
Ans Minterm: - Each individual term in the canonical SOP form is called as 1M each
minterm. OR
Minterm is a product of all the literals within the logic system. Each
literal may be with or without the bar i.e. complemented or
uncomplemented. SOP uses minterms.
Maxterm:- Each individual in the canonical POS form is called as
Maxterm. OR
Maxterm is a product of all the literals within the logic system. Each literal may be with
or without the bar i.e. complemented or uncomplemented. POS uses maxterms.
e List the types of DAC. 2M
Ans 1) Binary weighted resistor DAC 1M each
2) R –2R ladder DAC
f State two features of ADC IC0809. 2M
Ans Features of ADC IC0809 Any two
features 1M
i. It operates on 0 to 5V input range with single 5V supply. each
ii. It does not require external zero or full scale adjustment.
iii. It has low power consumption. It is 15mW.
iv. Conversion time is 100μs.
v. It offers high speed of conversion.
vi. High accuracy over wide range minimum temperature dependence.
vii. The output is TTL compatible.
viii. It is easy to interface with microprocessor.
g List the types of semiconductor memories. 2M
Ans 1)Read & write memories or Random Access Memories (RWM or RAM) 1M each-
2)Read only memory(ROM) Any 2 types
3)Programmable read only memory(PROM)
4)Erasable Programmable read only memory(EPROM)
5)Static Random Access Memories(SRAM)
6)Dynamic Random Access Memories(DRAM)

2 Attempt any THREE of the following: 12 M

a Perform the subtraction using 2's complement methods. (10110)2 - (11010)2 4M
Ans Given A=(10110)2 , B=(11010)2 1M For 2’s
Find the 2's complement of the subtracting number. Invert all the bits and complement
add 1 to the result:

B = 11010 (original number)

00101 (1's complement of B)
+ 1 (add 1) 1M for
-------- correct
00110 (2's complement) addition

Page No: 3/20

10110 (A)2
1M
+00110 (2's complement of B)
------
11100

Here final carry is 0 so result is negative and in its 1’s complement form. 1M for final
correct
So, the true form of answer is
answer
Therefore, 1's complement of 11100 -1=11011
Inverting all bits of answer, we get 00100.
Therefore, (10110)2-(11010)2=(00100)2
Explain the following characteristics with respect to logic families
i) Power dissipation
b ii) Fan-in and fan-out 4M
iii) Noise margin
iv) Speed of operation
Ans i] Power Dissipation: It is the amount of power dissipated in an IC in the form of heat. 1M each
OR
The power drawn by an IC from the power supply is given by P=Vcc*Icc

ii] Fan in: It is defined as the number of inputs a gate has.

Fan out: It is defined as the maximum number of inputs of same IC family that a gate
can drive without falling outside the specified output voltage limits.
iii] Noise margin: A quantitative measure of noise immunity of a logic family is called
as Noise margin.
iv] Speed of Operation: Speed of operation of a logic circuit is defined as the time
delay between the instant of application of an input and the instant of occurrence of
corresponding output.

Page No: 4/20

Page No: 5/20

1M- Truth
table

Truth Table:

Inputs Outputs Comments

1M -
CLK J K Q Q explanation

0 0 Qn No change
0 1 0 1 Reset
1M - State
1 0 1 0 Set
1 1 Qn Toggle

The clock signal is applied to CLK input. IF CLK =0 than F/F is disabled and O/P Q and
Q do not change.

Page No: 6/20

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e Give classification of memory and compare RAM and ROM. (Any four points) 4M
Ans 2M-
classification

2M-
comparison

Page No: 7/20

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__________________________________________________________________________________________________

Note: Any relevant classification can be considered.

Parameter RAM ROM
Volatility Volatile memory, data is Non-volatile memory,
lost when powered off. retains data when powered
off.
Read/Write Read and write operations Generally, read-only, write
possible. operations are limited or
non-existent.
Purpose Temporary storage for Permanent storage for
running programs essential system
instructions and data.
Usage Stores data actively used Stores firmware, BIOS,
by the CPU and other critical system
information.
Modifiability Easily and frequently Typically not easily
modified modifiable, often set
during manufacturing.
Speed Faster access times Slower access times
compared to RAM.
Examples DRAM, SRAM PROM, EPROM,
EEPROM, Flash ROM

3 Attempt any FOUR of the following: 16 M

Convert (53)10 = (BCD)
(34)10 = (Excess-3)
a 4M
(100111)2 = (Gray)
(11010)2=(2 's complement)
Ans • (53)10 = (0101 0011) BCD 1M

1M
• (34)10= (0110 0111) Excess-3

0011 0100
+ 0011 0011
0110 0111

Page No: 8/20

Ꚛ Ꚛ Ꚛ Ꚛ Ꚛ
Binary: 1 0 0 1 1 1

Gray: 1 1 0 1 0 0

• (11010)2 = 1’s complement+1= 00101+1= (00110) 2 's complement 1M

b State and explain De-Morgan's theorems. 4M

Ans De Morgan´s 1st Theorem: Statements-
It states that the complement of sum is equal to the product of the complement of 1M
individual variables. each
Anyone
proof - 2M
Proof :

De Morgan´s 2nd Theorem:

It states that the compliment of product is equal to the sum of the compliments of
individual variables.

Proof:

Page No: 9/20

16:1 Multiplexer using 4:1 Multiplexer

d Describe the operation of R-S flip-flop using NAND gate. 4M

Ans Logic dig.
1M

Truth Table
1M

Description
2M

Explanation:

When clock = 0, the outputs of NAND gates 3 and 4 will be forced to be 1 irrespective
of the values of S and R. That means R’= S’ = 1.Hence the outputs of basic SR/F/F i.e.
Q n+1 and will not change. Thus if clock = 0, then there is no change in the output of the
clocked SR flip-flop.

Page No: 10/20

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Case I : S = R = 0, clock = 1: No change If S=R=0 then outputs of NAND gate 3 and 4
are forced to become 1. Hence R' and S' both will be equal to 1. Since R' and S' are the
inputs of the basic S – R flipflop using NAND gates. There will be no change in the state
of outputs.
Case II : S =1, R = 0, clock = 1: Set Now S=0, R=1 and a positive going edge is applied
to the clock Output of NAND 3 i.e. R’ = 0 and output of NAND 4 i.e. S’ = 1. Hence
output of SR flip-flop is Q n+1 = 1 and = 0. This is the set condition.

Case III : S =0, R = 1, clock = 1: Reset Now S=0, R=1 and a positive edge is applied to
the clock input. Since S=0, output of NAND – 3 i.e. R´= 1. And as R’ = 1 and clock = 1
the output of NAND-4 i.e. S´ = 0. Hence output of SR flip-flop is Q n+1 = 0 and = 1.
This is the reset condition.

Case IV : S =1, R = 1, clock = 1: Undefined/ forbidden As S=1, R=1 and clock = 1, the
outputs of NAND gates 3 and 4 both are 0 i.e. S' = R'=0. So both the outputs Q n+1 = 1
and Hence output is Undefined/ forbidden.

Truth Table:

e Describe the operation of 4 bit serial in serial out shift register. 4M

Ans Diagram : (Use SR or JK or D type flip flop.) 1M-diagram
Note : Any other data input can be considered. Shift right or left operation can be
considered.

1M-
waveform

Page No: 11/20

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Working:
The DATA leaves the shift register one bit at a time in a serial pattern, hence the
name Serial-in to Serial-Out Shift Register or SISO.
The SISO shift register is one of the simplest of the four configurations as it has only
three connections, the serial input (SI) which determines what enters the left hand flip-
flop, the serial output (SO) which is taken from the output of the right hand flip-flop and
the sequencing clock signal (Clk). The logic circuit diagram below shows a generalized
serial- in serial-out shift register, Output of FFA is Q4,FFB Q3,FFC Q2 and FFD is Q1 2M-
explanation
Waveform:(Input is 01101):

f Draw and explain the block diagram of Programmable Logic Array (PLA). 4M
Ans Diagram- 2M
The block diagram of PLA is shown in the following figure.
Description-
2M

Programmable Logic Array PLA:

PLA is a programmable logic device that has both Programmable AND array &
Programmable OR array. Hence, it is the most flexible PLD.

Page No: 12/20

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Here, the inputs of OR gates are also programmable. So, we can program any number of
required product terms, since all the outputs of AND gates are applied as inputs to each
OR gate. Therefore, the outputs of PLA will be in the form of sum of products form

4 Attempt any TWO of the following: 16 M

a Design 1 : 8 demultiplexer using 1 :4 demultiplexer. Also write truth table. 8M
Ans 1:8 Demultiplexer using 1:4 demultiplexer 4 M-
Diagram

Truth Table of 1:8 Demultiplexer .

4M-Truth
table

Explain the role of counters in digital circuits and design Mod-> counter using
b IC 7490. 8M

Ans Role of counters: 2M-Role

A counter is probably one of the most useful and versatile subsystems in a digital
system. A counter driven by a clock can be used to count the number of clock cycles.
Since the clock pulses occur at known intervals, the counter can be used as an instrument
for measuring time and therefore period or frequency. There are basically two different
types of counters-synchronous and asynchronous.

Page No: 13/20

Design of mod-7 counter using IC 7490:

2M-Design
Block schematic of decade counter IC7490

2M-
Explanation

Mod-7 means states are from o,1,2,3,4,5,6,0 Therefore we have to reset counter IC
7490 when QD,QC,QB,QA=0111 Design reset logic: Output of reset circuit should be
HIGH because R0(1) and R0(2) are active high inputs. Therefore, reset logic output
should be low for states 0 to 6.

Output should be HIGH for states 7 onwards.

2M-Truth
table
Truth table & K-map:

Page No: 14/20

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For output Y:
Expression for Y: Y= QC QB QA + QD

Page No: 15/20

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__________________________________________________________________________________________________
Draw and explain the block diagram of dual slope ADC. Also write it's
c 8M
specifications
Ans Block dig. of dual slope ADC:

2M-diagram

2M-
waveform

Operation:

Initially assume that the integrator output voltage V = 0 and the counter is in RESET
condition Le counter output is 00.

At switch S, is connected to ground and switch Sy is closed. The capacitor Caz gets
connected across the comparator output.

Any offset voltage present in the OP-AMPs will appear across the capacitor Caz This 2M-
will provide an automatic compensation for the input offset voltage of all the amplifiers explanation
Therefore integrator output voltage is zero for the interval t0 to 1,

At instant t,, the SOC command is given to the control logic. Switch S, is connected to
V, and S, is open circuited. CAZ then acts as a memory to hold the
voltage required to keep the offset zero. Hence CA is known as the autozero capacitor.
Page No: 16/20
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ADC

From t, to to this ADC will integrate the analog input V. for a fixed duration of 2 number
of clock cycles. This time interval is required for the counter to advance through all its
possible output states, because for an n-bit counter there will be 2 possible output states,

The counter output then reduces to zero. The time duration t to 1 is represented by T

This expression represents a straight line with a slope of - V/RC. Thus we get a
decreasing ramp The time period T, is thus represented by 2" clock cycles.

T1=2^n*T ….. were T = One clock cycle period

At the end of interval T₁, the integrator input is connected to a fixed negative reference
voltage - VRER Via switch S₁.

The integrator output now starts increasing towards zero with a positive slope The slope
is VRE/RC for the duration to to ty.

The counter starts counting from 0. The integration will continue till the integrator
output is non-zero. At instant t the integrator output reduces to zero, the comparator
output goes from HIGH to LOW and the clock pulses given to the counter are stopped.

Specifications of ADC:
1.Power supply voltage:5V 2M-any 2
2.Resolution : 28 specifications
3.Conversion Time: 100 µs
4.Power consumption : <15mW
5.Input voltage : 0V-5V

1.Resolution: It is the maximum number of digital output codes. Resolution= 2^n (OR)
It is defined as the ratio of change in the value of input analog voltage required to change
the digital output by 1 LSB.

2. Conversion time: The time difference between two instants i.e. 'to' where SOC signal
is given as input to the ADC and 't1' where EOC signal we get as output from ADC. It
should be small as possible.
3.Quantization error :The error produced due to approximation or quantization process is
called as quantization error.

Page No: 17/20

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__________________________________________________________________________________________________

5 Attempt any TWO of the following: 16 M

a Design basic logic gates using NAND and NOR gate. 8M
Ans 4 Marks by
using NAND
Gate ( 1M
NOT Gate, 1
½ M each for
AND, OR
Gate)

4 Marks by
using NOR
Gate( 1M
NOT Gate, 1
½ M each for
AND, OR
Gate)

Minimize the following expression using K-map.

b f(A, B, C, D) = ∑ m (0, 1, 2, 4, 5, 7, 8, 9, 10) 8M
Also explain SOP and POS form.

Page No: 18/20

1M -correct
grouping

1M-
minimized
equation

2M each
explanation
of SOP and
Explanation: POS
Logic functions can be expressed in two standard forms
1. Sum-of-product form (SOP) and
2. Product-of-sum form (POS)
1. SOP stands for Sum of Products. It is a technique of defining the Boolean terms as
the sum of product terms. SOP can be realized using AND-OR configuration.

For example, Y=A⋅B + A⋅B’

Y=XZ’ + X’Z + XZ
Y=P’QR + PQR’ + Q’R
2. POS stands for Product of Sums. It is a technique of defining Boolean terms as a
product of sum terms. POS can be realized using OR-AND configuration.

For example, Y=(A+B) ⋅ (A+B’)

Y=(X’+Z) ⋅ (X+Z) ⋅ (X+Z’)

Y=(P+Q’) ⋅ (P’+Q+R) ⋅ (P+Q+R)

Page No: 19/20

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
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__________________________________________________________________________________________________
Draw and Explain 4 bit universal shift register. Also explain the necessity of
c register in digital circuits. 8M

Ans 4M Diagram

3M
explanation

Fig:4 bit universal shift register

Working: A "Universal" shift register is a special type of register that can load the data
in a parallel way and shift that data in both directions, i.e., right and left.
1. PARALLEL LOAD (M=1): When mode control (M) is connected to logic 1, AND
gates 2, 4, 6, 8 will be enabled and AND gates 1, 3, 5, 7, will be disabled. The 4-bit
binary data will be loaded parallel. The clock-2 input will be applied to the flip-flops,
since M= 1, AND gate -10 is enabled and gate-9 is disabled. Input will transfer parallel
data to QA to QD outputs.
2. SHIFT RIGHT (M=0): When mode control (M) is connected to logic 0, AND gates
1,3,5,7 will be enabled and AND gates 2, 4, 6, 8, will be disabled. The data will be
shifted serially. The clock -1, input will be applied to the flip-flops, Since M = 0, AND
gates - 9 is enabled, and gates -10 is disabled. The data is shifted serially to right from
QA to QD.
3. SHIFT LEFT (M=1): When mode control (M) is connected to logic 1, AND gates
2,4,6,8 will be enabled. This mode permits parallel loading of the resister and shift -left
operation. . The shift -left operation can be accomplished by connecting the output of
each flip flop to the parallel input of the previous flip- flop and serial input is applied at
the input.
Necessity: The shift registers are used for temporary data storage. The shift registers are
also used for data transfer and data manipulation. The serial-in serial-out and parallel-in
1M
parallel-out shift registers are used to produce time delays in digital circuits.
Necessity

Page No: 20/20

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
(Autonomous)
(ISO/IEC - 27001 - 2013 Certified)

SUMMER-2024 EXAMINATION
Model Answer Only for the Use of RAC Assessors
Subject Name: Digital Techniques Subject Code: 22320

Important Instructions to examiners:

1) The answers should be examined by key words and not as word-to-word as given in the model answer
scheme.
2) The model answer and the answer written by candidate may vary but the examiner may try to assess the
understanding level of the candidate.
3) The language errors such as grammatical, spelling errors should not be given more Importance (Not
applicable for subject English and Communication Skills.
4) While assessing figures, examiner may give credit for principal components indicated in the figure. The
figures drawn by candidate and model answer may vary. The examiner may give credit for any
equivalent figure drawn.
5) Credits may be given step wise for numerical problems. In some cases, the assumed constant values may

6) In case of some questions credit may be given by judgement on part of examiner of relevant answer
based on candi
7) For programming language papers, credit may be given to any other program based on equivalent
concept.
8) As per the policy decision of Maharashtra State Government, teaching in English/Marathi and Bilingual
(English + Marathi) medium is introduced at first year of AICTE diploma Programme from academic
year 2021-2022. Hence if the students write answers in Marathi or bilingual language (English
+Marathi), the Examiner shall consider the same and assess the answer based on matching of concepts
with model answer.

Sub
Q. Marking
Q. Answer
No. Scheme
N.
1. Attempt any FIVE of the following: 10 M
a) List the uses of following codes: 2M
i) BCD Code
ii) ASCII

Ans. The uses of following codes are: 1 M for any

i) BCD Code: two uses of
1) In digital communication each code
2) In Digital computers
3) In many personal computers to store date and time
4) In other digital systems where, precise decimal arithmetic operations
are required e.g. calculators.
5) In real time clock systems

ii) ASCII:
1) In computers to represent characters, symbols and alphabets.
2) Most computer keyboards are standardized using ASCII.
3) ASCII is standard for character encoding used in appliances,
telecommunications, computers and other related devices.
4) It is used to display text in various devices.

Page 1 of 23
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SUMMER-2024 EXAMINATION
Model Answer Only for the Use of RAC Assessors
Subject Name: Digital Techniques Subject Code: 22320

b) Write the one application of SR-FF and mention its one drawback. 2M
Ans. Application of SR-FF: 1 M for
1) It is used in memory storage devices to store data temporarily such as Application
registers and registers are used in counters, microprocessors and digital signal &
processors. 1 M for
Drawback of SR-FF: Drawback
1) When the inputs of SR-FF are S=0, R=0 or S=1, R=1, the outputs are either
invalid or do not change due to race condition.

c) State the advantages of using tri state logic in combinational logic. 2M

Ans. Advantages of using tri state logic in combinational logic are: 1 M each for
1) It reduces crosstalk in a bus. any two
2) It prevents a bus conflict over a state of signal. Advantages
3) It allows multiple devices to share the same bus without interference.

Note: Any relevant advantages should be considered.

d) Draw excitation table of T FF. 2M
Ans. Excitation table of T FF: 1/2 M for each
I/O
Table: Excitation table of T FF combination
Output Q Input
Present state (Qn) Next state (Qn+1) Tn
0 0 0
0 1 1
1 0 1
1 1 0

e) List any two specifications of IC 0809. 2M

Ans. Specifications of IC 0809: 1 M for each
1) Input voltage range: 0 to 5 V Specification
2) Power consumption: Less than 15 mW (Any two
3) Conversion time:100 µsec Specifications)
4) Power Supply voltage: 5V
5) Resolution: 28
OR

1) Resolution: It is defined as the maximum number of digital output codes.

Resolution = 2n or VFS / 2n-1
2) Conversion time: It is the total time required to convert the analog input
signal into a corresponding digital output.
3) Quantization error: The error due to quantization process is called as
quantization error.
f) Define: Encoder 2M
Ans. Encoder is a combinational circuit which accepts N bit digital input and converts it 2 M for correct
into an M bit another digital word. Definition
g) Name four types of shift register. 2M
Ans. Types of shift register: 1/2 M each
1) Serial Input Serial Output (SISO) type
2) Serial Input Parallel Output (SIPO)
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3) Parallel Input Serial Output (PISO)

4) Parallel Input Parallel Output (PIPO)
5) Bidirectional Shift Register
6) Universal Shift Register

2. Attempt any THREE of the following: 12 M

a) S compliment method. 4M
i) (1100) (0011)
ii) (10101) (11100)

Ans.
complement
&
1 M for correct
answer (of each
sub question)

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b) Draw the MUX tree for 32:1 MUX using 4:1 MUX only. 4M
Ans.

4 M for correct
diagram

Fig.: 32:1 MUX tree using 4:1 MUX

Note : For MUX 11 at the output, though input values are not written and only
input lines are drawn, marks should be given.

c) Name the basic building block used in CPLD and state their functions. 4M
Ans. The basic building blocks used in CPLD are: 1M for writing
1) PAL like blocks names of
2) Input /Output (I/O) blocks blocks
3) Interconnecting wires &
Their functions are as below:
1) PAL like blocks:
Each PAL like block is made of 16 macrocells. 2 M for
Inside each microcell there is an AND-OR combination the output function of
of which is applied to an EX-OR gate, flip-flop, multiplexers and PAL-like block
tristate buffers. &
Every AND-OR combination contains up to about 20 AND gates 1/2 M for
and 1 OR gate. function of I/O
The OR gate output is connected to the input of a EX-OR gate. block
&

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The EX-OR gate can invert its input if one end of it is connected to 1/2 M for
1. function of
It will not invert the OR gate output if one end of it is connected to interconnecting
0. wires
The EX-OR gate output is stored into a D FF.
The output of this flip flop along with the output of the EX-OR gate
is applied to the inputs of a 2: 1 multiplexer. A multiplexer will
connect either the FF's output or the EX-OR gate output to the
tristate buffer depending on the state of its select input either 0 or 1.
The tri-state buffer acts as a switch. Its output is connected to I/O
pin of the IC. This pin of the chip acts as output if the buffer is
enabled and the same pin acts as input pin if the buffer is disabled.
But if the pin is used as input pin, then the macrocell is disabled.
2) Input/output ( I/O) block: The PAL like blocks are connected to the I/O
blocks and to the interconnecting wires.
3) Interconnecting wires: Various blocks of CPLD are interconnected with
each other via interconnecting wires
d) Minimize the following expression using K-map: 4M
f (A, B, C, D) = m(2, 3, 6, 10, 11, 12, 14, 15)
Ans. Simplification using K-map: 1 M for
drawing k
map,
1M for
representing
function in k
map,
1 M for
grouping &
1M for final
expression

Fig: K-map representation of given function

Note: Any relevant grouping and expression should be considered to minimize
the given expression.

3. Attempt any THREE of the following: 12M

a) Compare TTL and CMOS logic on the basis of:
i) Noise margin
ii) Figure of merit 4M
iii) Speed of operation
iv) Fan in

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Ans. 1M for each

Parameters TTL CMOS Parameter
i) Noise margin 0.4Volt 1.45Volt
ii) Figure of merit 100 PJ 0.7 PJ
iii) Speed of
Fast Slow
operation
iv) Fan in low, often high fan-in,
around 2 to 4 allowing them to
inputs. accommodate a
relatively large
number of input
signals.

b) Realize the following logic operations using only NOR gates 4M

i) OR
ii) EX-NOR
Ans. 2M for each
i) OR gate using NOR gate: -
Boolean expression for an OR gate using NOR gate

Q = A+B

ii) EX-NOR gate using NOR gate: -

Boolean expression for an EX-NOR gate using NOR gate

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Output of EX-NOR.

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c) Design the IC7490 as mod-B counter and describe its operation. 4M

Ans. Design IC7490 as mod-8 2M for Design
&
A mod-8 counter will count the first step from 0 to 7 and reset at ninth step. 2M for
Operation
For remaining all step, output Y = 0

K-Map

Expression of Y

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Operation

A mod-8 counter is a circuit that counts from 0 to 7 and then resets to 0. It can be
built using a variety of different integrated circuits (ICs), but one common choice is
the IC 7490.

The IC 7490 is a decade counter, which means that it can count from 0 to 9. However,
it can be configured to work as a mod-8 counter by connecting two of its reset pins
together. When this is done, the counter will count from 0 to 7 and then reset to 0.

Here is an example of how to build a mod-8 counter using the IC 7490:

Connect pins 2 and 3 of the IC 7490 together.
Connect pin 4 of the IC 7490 to VCC.
Connect pin 5 of the IC 7490 to ground.
Connect pin 6 of the IC 7490 to a clock signal.
Connect pins 11, 10, 9, and 8 of the IC 7490 to four LEDs.

Note 1: Consider mod B as mod 8 counter

Note 2: Consider any relevant diagram and description

d) Calculate the analog output of 8 -Bit DAC for digital input 10011100. Assume 4M
Vfullscale =5V.

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Ans.
2M for VR

2M for VO

Analog output of 8 -Bit DAC Vo = 3.061 volts

4. Attempt any THREE of the following: 12M

a) Draw the symbol, truth table and logical expression of following gates: 4M
i)EX-OR gate
ii) NAND gate

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Ans. i)EX-OR gate:

Symbol 1/2M
each,
Truth table 1M
each & Logical
expression 1/2
M each

ii) NAND gate:

b) Draw the full adder circuit's logic diagram, truth table and K-map 4M
simplification.
Ans A full adder is a computational logic circuit that performs addition between three 1M for circuit
bits, the two input bits A and B, and carry Cin. logic diagram,
Full adder circuit's logic diagram: - 1M for Truth
table,
1M for K-map
&
1M for
simplified
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Boolean
expression

Full adder Truth table :

K- map simplification :-

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Simplified Boolean Expression:

c) Draw the binary to gray code converter with the help of truth table and its K- 4M
map simplification.
Ans. Binary to Gray Code converter Truth Table: -
1M for Truth
Binary inputs Gray Output table &
Decimal 2M for K-map
B3 B2 B1 B0 G3 G2 G1 G0 simplification
&
0 0 0 0 0 0 0 0 0 1M for logic
1 0 0 0 1 0 0 0 1 diagram

2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
Table: Binary to Gray Code converter Truth Table

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K - MAP for G3: -

Table.: K map for G3

G3=B3

K - MAP for G2: -

G 2 B3B 2 B3B 2
G2 = B3 XOR B2

Table.: K MAP FOR G2

K MAP FOR G1: -

Table.: K MAP FOR G1

G B 2B1 B 2 B1
B1 XOR B2
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K MAP FOR G0: -

Table.: K MAP FOR G0

G0 B1B 0 B1B 0
B1 XOR B0

Diagram for Binary to Gray code converter:

d) Describe the working of clocked SR flip-flop with preset and clear. 4M

Ans.
2M for
diagram
&
2M for
working

Fig. : Clocked SR Flip Flop

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Working of clocked SR flip-flop with preset and clear:

In the flip-flop when the power is switched ON, the state of the circuit is uncertain.
It may come to set (Q=1) or reset (Q=0) state.
In many applications it is desired to Initially set or reset the flip-flop l.e. the initial
state of the flip-flop is to be assigned. This is accomplished by using preset (Pr) and
clear (Cr) Inputs.
These inputs may be applied at any time between clock pulses and are not in
synchronism with the clock. An S-R flip-flop with preset and clear is shown in Fig.
If Pr = Cr = 1, then both the circuit operates in accordance with the truth table of S-
R flip-flop given in table.
If Pr = 0 and Cr = 1, the output of G1 (Q) will certainly be 1.
Consequently, all the three inputs to G2 will be 1 which will make Q = 0. Hence
making Pr = 0 sets the flip-flop.
Similarly, if Pr = 1 and Cr = 0 then the flip-flop is reset.
The condition Pr = Cr = 0 must not be used, since this leads to an uncertain state.
Truth Table:

Table: Clocked SR flip-flop with preset and clear

Inputs operation
output
clk Pr Cr performed

1 1 1 Qn-1 Normal SR FF
x 0 1 1 FF is set
x 1 0 0 FF is reset

Note: Consider any relevant diagram and description.

e) Describe the working principle of dual slope type of ADC with neat diagram. 4M
Ans. 2M for
diagram
&
2M for
Working

Fig. : Dual slope type of ADC

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Working :
Above Fig. shows the functional block diagram of a Dual-Slope ADC. It consists of
four major blocks: 1. an integrator, 2. a comparator, 3. a binary counter and 4. a
switch driver, 5.T flip-flop.
This circuit is provided with a single-pole double throw electronic switch. The
initial state of the circuit is such that:
1. The output of the integrator is small and positive, so that the output of the
comparator is low. Thus, the AND gate is disabled.
2. The counter is kept reset, so that Y output of all flip-flops in the counter are
reading
3. The toggle mode flip-flop is kept reset.
The conversion process begins at t=0 with the switch S1 position 0 thereby
connecting the analog voltage Vx to the input of the integrator.
The integrator output is:

This results in high Vcr thus enabling the AND gate and the clock pulses reach the
clock (clk) Input terminal of the counter which was initially clear. The counter counts
N-1 clock pulses are applied.
N,
At the next clock pulse 2 the counter is cleared and Q becomes 1. This controls the
state of S1 which now moves to position 1 at T1 thereby connecting -VR to the input
of the Integrator. The output of the Integrator now starts to move in the positive
direction. The counter continues to count until V0 < 0 As soon as V0 goes positive at
T2, Vc goes low enabling the AND gate. The counter will counting in the absence of
the clock pulses. The waveforms of voltages V0 and Vc are shown in below Fig.

Note: Consider any relevant diagram and description.

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5. Attempt any TWO of the following: 12M

a) Design 4-bit ripple counter and draw output waveforms. 6M
Ans.
2M for
diagram,
2M for Truth
Table
&
2M for
waveforms

Since it is 4 bit Ripple up counter , we need to use four Flip Flops .

Initially all the Flip Flops have Zero output QDQCQBQA = 0000
All the Flip Flops are negative edge triggered CLK is applied to the clock input of
FF-A .
Where as Q output of every Flip Flop is applied to the clock input of next Flip Flop.

Truth Table of 4 bit ripple counter:

0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
0 0 0 0

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Waveforms:

b) Compare weighted resister DAC with R-2R ladder type DAC (any six points). 6M
Ans. 1 M for each
Weighted Resistor (any six points)
Aspect R-2R Ladder DAC
DAC
Higher precision due to Generally precise, binary-
1) Precision
varied resistor values. weighted structure.
2) Component Higher due to many Lower due to binary-
Complexity unique resistor values. weighted structure.
May exhibit non- Typically, better linearity
3) Non-Linearity linearity due to resistor due to binary-weighted
tolerance. design.
Slower due to complex
Faster due to simpler
4) Conversion Speed voltage division
structure.
process.
Requires precise digital- Suited for direct binary-
5) Digital Inputs
to-analog conversion. weighted digital inputs.
More sensitive to
6) Accuracy vs. More forgiving due to
resistor tolerance
Tolerance binary-weighted structure.
variations.
7) Simplicity Simple. Slightly complicated.
8) Range of register Registers of only two
Wide range is required.
values value are required.
9) Number of registers
One Two.
per bit
Not easy to expand for
10) Ease of expansion Easy to expand.
more no of bits.

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c) Convert the following 6M

i) (ABCD)16 = ( ? ) 10
ii) (101011001111)2 = ( ? )10
iii) (101011001111)2 = ( ? )8

Ans. i) (ABCD)16 = ( ? ) 10 2M for each

conversion and
correct answer.

ii) (101011001111)2 = ( ? )10

iii) (101011001111)2 = ( ? )8

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6. Attempt any TWO of the following: 12M

a) Draw universal shift register and describe its operation. 6M
Ans.
3M for
diagram
&
3M for
Operation

Fig.: Universal Shift Register

Operation:
A shift register which can shift the data in both the directions (shift right or left) as
well as load it parallelly, is called as a Universal Shift Register.
This shift register is capable of performing the following operations:
1)Parallel loading (parallel input parallel output)
2)Left Shifting
3) Right Shifting
The mode control input is connected to Logic 1 for parallel loading operation
whereas it is connected to 0 for serial shifting.
With mode control pin connected to ground, the Universal Shift Register acts as a
Bi- directional register.
For serial left operation, the input is applied to the serial input which goes to AND
gate-1. Whereas for shift right operation , the serial input is applied to D input AND
gate 8
b) Draw the 4-Bit adder circuit using IC 7483 and describe its working with 6M
suitable examples.

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Ans.

3M for
Diagram
&
3M for
working

Working:

1. Inputs (A0 to A3 and B0 to B3):

Connect the four input pins (A0 to A3 and B0 to B3) of the IC 7483
to the corresponding bits of the two 4-bit binary numbers you want to
add.
2. Outputs (S0 to S3 and C4):
The four sum outputs (S0 to S3) represent the result of the addition of
the two input numbers.
The carry out output (C4) indicates if there's a carry generated beyond
the 4-bit result.
3. Carry Propagation:
The IC 7483 internally generates carries as needed while adding the
input bits.
It performs full binary addition, taking into account the input bits and
any carry from the previous stage.
4. Example:
Let's say we want to add two 4-bit binary numbers: A = 1010 and B
= 0111.
Connect A0 to A3 with 1010 and B0 to B3 with 0111.
The resulting sum (S0 to S3) would be 10001 (binary representation
of 17 in decimal).
The carry out (C4) would be 1, indicating that there's a carry beyond
the 4-bit result

Note: Consider any relevant correct diagram.

c) Draw the circuit diagram of 3-input TTL NAND gate and explain its working. 6M
Ans.

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Circuit Diagram: 3M for

diagram
&
3M Working

Fig.: Circuit diagram of 3 input TTL NAND Gate

Circuit Description:
The 3-input TTL NAND gate circuit consists of three input terminals and one output
terminal. Each input terminal is connected through an input resistor, and the output
is taken from the connection point between these resistors. The circuit operates with
a positive power supply voltage (Vcc) and a ground reference (GND).
Working:
1. Input Signals:
The gate has three input terminals (A, B, and C), each connected
through a resistor.
Inputs can be at logic level HIGH (typically Vcc, representing a
binary '1') or logic level LOW (typically GND, representing a binary
'0').
2. Voltage Divider Network:
When any input terminal is at logic level LOW (GND), it pulls the
corresponding node of the voltage divider network to LOW.
When all input terminals are at logic level HIGH (Vcc), the voltage at
the common node between the resistors is pulled up to HIGH.
3. Transistor Configuration:
The output transistor configuration of a NAND gate ensures that when
any input is LOW, the base voltage of the transistor(s) is pulled down
to LOW.
As a result, the transistor(s) conduct and pull the output voltage to
LOW.
When the transistor Q3 is ON, the output at terminal Y is HIGH. The output
is LOW when the transistor Q4 is turned ON. The first and second states are
the normal operation of TTL. In the third state, both the transistors Q3 and
Q4 are turned OFF, which results in neither LOW nor HIGH output.

Page 23 of 23

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