Accelerating State-Of-Charge Estimation in FPGA-based Battery

Management Systems
X. Tian*, B. Jeppesen*, T. Ikushima*, F. Baronti†, R. Morello†
*Altera (now part of Intel), United Kingdom, [email protected], [email protected]

†University of Pisa, Italy, [email protected]

Keywords: FPGA, Battery Management System, State-Of- more battery modules in a single device than off-the-shelf
Charge, Dual Extended Kalman Filter processor-based solutions. Moreover, FPGA has capability of
massive parallelism. For instance, you can use FPGA to
Abstract estimate more number of cells in the same time. A most direct
benefit from the above features is that one can have improved
This paper presents the implementation of a state of charge usable vehicle range, as more accurate battery status can be
(SOC) estimator for Lithium-ion battery in a Field achieved by using more advanced SOC algorithms.
Programmable Gate Array (FPGA) based System-in-the-Loop
platform. The paper explains and provides results from The Altera® Battery Management System (BMS) reference
alternative methods for accelerating the SOC calculations in design [2] demonstrates battery State Of Charge (SOC)
the FPGA. The System-In-the-Loop (SIL) simulation estimation in an FPGA-based real-time control platform that
provides a platform to develop a full FPGA-based BMS, could be extended to include other BMS functionality such as
using high-level tools to generate Hardware Description battery State-of-Health monitoring and charge equalization
Language (HDL) code for the FPGA. The work has been (cell balancing). It uses a Dual Extended Kalman Filter
developed into a reference design that is freely available and (DEKF) algorithm to estimate SOC values for 96 cells, using
can be run on low-cost hardware. Results have been obtained a MAX® 10 development kit. The reference design’s System-
for SOC calculation times for several alternative hardware in-the-Loop simulation runs under MATLAB®/Simulink®.
implementations in the FPGA. The execution time to update
one battery cell ranges from 44.9μs down to 16.5μs. The The reference design offers the following features:
alternative methods allow a designer to choose a balance
between calculation time and resource usage. x Uses the Altera MAX® 10 development kit, which
includes a 10M50D, F484 package FPGA.
1 Introduction x SOC estimation and parameter identification using dual
extended Kalman filter algorithm (DEKF).
A Battery Management System (BMS) is a critical component
x Estimating SOC value for 96 cells.
in high-value battery powered applications such as electric
x Alternative hardware implementations of SOC
vehicles or energy storage. The main objective of a BMS is to
calculations:
maintain the health of all the cells in the battery pack to
x Nios®II processor with floating point acceleration
deliver the power needed by the application, while protecting
the cells from damage and maintaining all the cells within the x Nios®II with floating point acceleration and floating
manufacturer-recommended operating conditions in order to point matrix processor
prolong the life of the battery pack. Key features of a BMS x Nios®II processor and DEKF algorithm
usually includes: SOC estimation, State-Of-Health (SOH) implemented in dedicated floating point IP
estimation, cell balancing, thermal management, charge x SIL simulation runs a MATLAB®/Simulink® model that
control, battery safety and protection, cell monitoring, and so communicates with FPGA hardware using Altera’s
on. In this paper, we will focus the one of the most important System Console API.
parts of BMS, which is SOC estimation. x The results from the FPGA can be compared in real-time
with the results from the Simulink® calculations.
Usually, microprocessors are used for the general control unit x Nios®II processor used to do scheduling and
for a BMS. However, we consider that Field Programmable communicating with MATLAB® through System
Gate Array (FPGA) can be a good replacement for Console.
microprocessor, or co-processor sitting beside microprocessor x Nios®II software runs on μC/OS-II® real-time operation
[1]. An FPGA combines a high I/O count for parallel system.
connections to many battery modules with the ability to
accelerate processor-intensive calculations in the FPGA The remainder of the paper is organised as follows. Section 2
fabric. This enables a BMS to be developed that can monitor gives the mathematical background of battery model and
SOC estimation in general, and DEKF algorithm in particular.

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 The architecture of our BMS reference design, benchmarking
R0 Ri iL
results, as well as comparison with other implementations are
described in section 3. Finally, conclusions are drawn. Ci +
VRCi
N RC branches

2 Background +
iL Qn SOC + Voc VM
- -
The SOC of a battery is a measurement of how much energy
is remaining in percentage. There is no direct indication of
SOC. Over the years, many different methods are developed
-
to measure SOC. Two of the simple ways are: measure cell Figure 1: Battery cell equivalent circuit model
voltage to calculate SOC, and current integrations, which is
also called coulomb counting. The first way can work well for 2.2 Dual Extended Kalman Filter
battery chemistries such as Lead-Acid, for which voltage and In the DEKF technique, two cooperating Kalman Filters for
capacity are fairly linearly related, but ineffective for other nonlinear systems are executed simultaneously: one for the
battery chemistries, such as Lithium-ion, for which voltage is state and the other for the parameters estimation. The use of
mostly flat over the battery capacity, except at extremes, the dual estimation, instead of a joint estimation, in which
where it is very non-linear. The latter is an open-loop only one Kalman Filter is used, reduces the state matrix
technique based on integration. Hence noise and quantisation dimensions and may improve the estimation robustness. The
errors can cause large SOC estimation errors. Although errors parameter evolution is described by the process equation (1),
can be eliminate by recalibration after full discharging or which is used in combination with the measurement equation
charging. However, this can rarely be achieved in Electric (3), in order to build the first EKF. The state evolution is
Vehicle (EV) or Hybrid Electric Vehicle (HEV). Other more instead represented by (2), which is again combined to the
advanced techniques include Kalman Filter [3], Fuzzy Logic, measurement equation (3) to form the second EKF.
Neural Networks, etc. Among different solutions, Kalman
Filter is considered to be one of the most popular methods. It ‫݌‬ሺ݇ ൅ ͳሻ ൌ ‫݌‬ሺ݇ሻ ൅ ߯ሺ݇ሻ (1)
is designed to strip unwanted noise out of a stream of data. It
operates by predicting the new state and its uncertainty. ‫ݔ‬ሺ݇ ൅ ͳሻ ൌ ‫ܨ‬ሺ‫ݔ‬ሺ݇ሻǡ ݅௅ ሺ݇ሻǡ ‫݌‬ሺ݇ሻሻ ൅ ߦሺ݇ሻ (2)
DEKF [4] is one of the Kalman Filter extensions which will
‫ ்ݒ‬ሺ݇ሻ ൌ ‫ܩ‬ሺ‫ݔ‬ሺ݇ሻǡ ݅௅ ሺ݇ሻǡ ‫݌‬ሺ݇ሻሻ ൅ ߰ሺ݇ሻ (3)
be described later on. Next, we will introduce the battery
model used in DEKF. The measurement equation (3) is the same for both filters. In
the above equations, k is the discrete time, p is parameters
2.1 Battery model vector, x = [SOC; ܸோ஼ଵ ] is the battery state vector. χ, ξ and ψ
are the parameters, the state and measurement noise, with
The battery model is able to simulate a number of series- zero mean and covariance matrix Σχ, Σξ and Σψ, respectively.
connected cells. The only input is the battery current, which is
the same for all the series-connected cells. As output, at each Given the above methods, we use the following equations to
time step, the model generates the arrays of the cell voltage describe the actual circuit:
ܸ௜ , SOC, as well as the current values of the model parameters
[5]. The model adopted is the equivalent circuit model shown ܱܵ‫ܥ‬௞
in Figure 1. The left hand side models the cell capacity ܳ௡ ‫ݔ‬௞ ൌ ݂൫ܱܵ‫ܥ‬௞ ǡ ܸோ஼ೖ ǡ ݅௅ೖ ൯ ൌ ൤ ܸ ൨ ൌ
ோ஼ೖ
and evaluates the SOC as the voltage across a linear capacitor ்
with a capacity equal to ܳ௡ (expressed in Coulomb) divided ܱܵ‫ܥ‬௞ିଵ െ ݅௜ಽ
ொೝ
൥ ೖ
൩ (4)
by 1V. The cell voltage vM is obtained by the sum of the ‫ݒ‬ோ஼ೖషభ ݁ ି்Ȁఛ ൅ ܴሺͳ െ ݁ ି்Ȁఛ ሻ݅௅ೖ
open-circuit voltage VOC and a dynamic term, which accounts
for the internal resistance R0 and the double layer effect ‫்ݒ‬ೖ ൌ ݃൫ܱܵ‫ܥ‬௞ ǡ ܸோ஼ೖ ǡ ݅௅ೖ ൯ ൌ ܱ‫ܸܥ‬ሺܱܵ‫ܥ‬௞ ሻ െ ܴ଴ ݅௅ೖ െ ‫ݒ‬ோ஼ೖ (5)
(ܸோ஼ଵ ) and diffusion (ܸோ஼ଶ ) of the Li-ion during charging and
discharging (2 RC branches). The model parameters change ܱ‫ܸܥ‬ሺܱܵ‫ܥ‬ሻ ൌ ܲଵ ܱܵ‫ ଻ ܥ‬൅ ܲଶ ܱܵ‫ ଺ ܥ‬൅ ܲଷ ܱܵ‫ ܥ‬ହ ൅ ܲସ ܱܵ‫ ܥ‬ସ ൅
with manufacturing variations, ageing and operating ܲହ ܱܵ‫ ܥ‬ଷ ൅ ܲ଺ ܱܵ‫ ܥ‬ଶ ൅ ܲ଻ ܱܵ‫ ܥ‬ଵ ൅ ଼ܲ (6)
conditions, such as temperature and state of charge. In order With these equations, we can derive the matrix equations used
to model the temperature and SOC dependences, the in the DEKF:
parameter values are stored in 2D LUTs. The variability of
the cell behaviour is modelled by setting the model ܱܵ‫ܥ‬௞
parameters, temperature and capacity of each cell ‫ݔ‬௞ ൌ ൤ ܸ ൨
ோ஼ೖ
individually. Note that the battery model developed for this
design is a Kokam SLPB723870H4 battery [5]. ܱܵ‫ܥ‬௞
‫ݍ‬௞ ൌ ൥ ͳȀ߬ ൩
ܴ௞
ͳ Ͳ
‫ܣ‬௞ ൌ ቂ ቃ (7-13)
Ͳ ݁ ି்Ȁఛ

horized licensed use limited to: NUST School of Electrical Engineering and Computer Science (SEECS). Downloaded on September 24,2024 at 23:45:25 UTC from IEEE Xplore. Restrictions ap
 ܱ݀‫ܸܥ‬ሺܱܵ‫ܥ‬ሻ MATLAB, receiving results coming back from FPGA, and
‫ܥ‬௫ೖ ൌ ൤ െ ͳ൨ plot the results. On the FPGA side, major components include
ܱ݀ܵ‫ܥ‬
the JTAG-Avalon bridge which is used to communicate with
݀‫ݔ‬௞ି
‫ܥ‬௤ೖ ൌ ሾ݅௅ೖ Ͳ Ͳሿ ൅ ‫ܥ‬௫ೖ MATLAB/Simulink API, a Nios®II processor, Nios®II
݀‫ݍ‬ processor custom instruction floating point core which is used
݀‫ݔ‬௞ି to accelerate the floating point calculations in Nios®II
݀‫ݍ‬ processor, matrix processor, on-chip RAM, DEKF DSP
ା Builder IP, DDR3 controller, etc.
ͳ Ͳ ݀‫ݔ‬௞ିଵ
ൌቂ ି்Ȁఛ ቃ
Ͳ ݁ ݀‫ݍ‬
Ͳ Ͳ Ͳ Driving cycle Matrix Processor

൅ቈ ି
் ቉
Ͳ ܶ݁ ఛ ሺܴ݅௅ೖ െ ܸோ஼ೖషభ ሻ ሺͳ െ ݁ ି்Ȁఛ ݅௅ೖ ሻ

JTAG-Avalon Master Bridge

On-chip memory

System Console Matlab API

Avalon Memory-map interface

Car model (control registers,
measured values, etc.)
ା
݀‫ݔ‬௞ିଵ ݀‫ݔ‬௞ି
ൌ െ ‫ܮ‬௫ೖషభ ‫ܥ‬௤ೖషభ Battery model DEKF DSPbuilder IP
݀‫ݍ‬ ݀‫ݍ‬ Nios2
processor
Nios2 custom instruction
Equivalent Floating point core
The full DEKF process is as below: algortihm running
in Matlab Performance
counter
Scope
1) Initialization DDR3 controller
Matlab/Simulink FPGA

‫ݔ‬଴ ǡ ܲ଴ ǡ ‫ݍ‬଴ ǡ ܲ௤బ (14) DDR3 memory

2) Prediction Figure 2: System diagram of the reference design

‫ݍ‬௞ି ൌ ‫ݍ‬௞ିଵ
ା

ܲ௤ିೖ ൌ ܲ௤ାೖషభ ൅ ܳ௤ (15-18)

‫ݔ‬௞ି ൌ ݂ሺ‫ݔ‬௞ିଵ
ା ା
ǡ ‫ݑ‬௞ିଵ ǡ ‫ݍ‬௞ିଵ ሻ
ܲ௞ି ൌ ‫ܣ‬௞ ܲ௞ିଵ
ା
‫்ܣ‬௞ ൅ ܳ
3) Correction

‫ܮ‬௫ೖ ൌ ܲ௞ି ‫ܥ‬௫்ೖ ሺ‫ܥ‬௫ೖ ܲ௞ି ‫ܥ‬௫்ೖ ൅ ܴሻିଵ

‫ݔ‬௞ା ൌ ‫ݔ‬௞ି ൅ ‫ܮ‬௫ೖ ሺ‫ݕ‬௞ െ ݃ሺ‫ݔ‬௞ି ǡ ‫ݑ‬௞ ǡ ‫ݍ‬௞ିଵ
ା
ሻሻ
ܲ௞ି ൌ ሺ‫ ܫ‬െ ‫ܮ‬௫ೖ ‫ܥ‬௫ೖ ሻܲ௞ି (19-24)
‫ܮ‬௤ೖ ൌ ܲ௤ିೖ ‫ܥ‬௤்ೖ ሺ‫ܥ‬௤ೖ ܲ௤ିೖ ‫ܥ‬௤்ೖ ൅ ܴሻିଵ
Figure 3: Reference design top level in MATLAB/Simulink
‫ݍ‬௞ା ൌ ‫ݍ‬௞ା ൅ ‫ܮ‬௤ೖ ሺ‫ݕ‬௞ െ ݃ሺ‫ݔ‬௞ି ǡ ‫ݑ‬௞ ǡ ‫ݍ‬௞ିଵ
ା
ሻሻ
ܲ௤ିೖ ൌ ሺ‫ ܫ‬െ ‫ܮ‬௤ೖ ‫ܥ‬௤ೖ ሻܲ௤ିೖ The functionality of each component will be described in
section 3.2. Firstly, details of car model and driving cycles
will be introduced.
3 Implementation
Given the above algorithm and battery model, we x Car model and driving cycles
implemented it on Altera MAX® 10 development kit. In this
section, we will start with introduction of the system level The car model computes the electric power at the battery’s
architecture. terminals, so that the vehicle speed follows a driving cycle.
There are 11 standard driving cycles to choose from [5]. The
3.1 System architecture Urban Dynamometer Driving Schedule (UDDS), the
Highway Fuel Economy Test (HWFET) and the Federal Test
Figure 2 shows the overall system architecture of the Procedure (FTP) are defined by the U.S. Environmental
reference design, and Figure 3 gives the look of Protection Agency. The New European Driving Cycle
Maltab/Simulink top level API. The whole system is divided (NEDC), the Extra-Urban Driving Cycle (EUDC) and the
into two parts: MATLAB/Simulink API, and FPGA. Major Economic Commission for Europe urban driving cycle (ECE
functions on MATLAB/Simulink API include: generating R15) are maintained by the United Nations Economic
speed from a number of driving cycles, generating voltage Commission for Europe (UNECE). The Common Artemis
and current values based on the speed of the vehicle, feeding Driving Cycles consists of the Urban cycle (ArtUrban), the
data to both FPGA and the golden reference model running in Rural road cycle (ArtRoad) and the Motorway cycles

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 (ArtMw130 and ArtMw150, with a maximum speed of 130 x Nios®II processor and DEKF algorithm implemented in
and 150 km/h, respectively). The Worldwide harmonized dedicated floating point IP (Design C)
Light vehicles Test Procedures (WLTP) Class 3 is developed
the following the guidelines of UNECE World Forum for In addition, we used an experimental tool called ASIP
Harmonization of Vehicle Regulations. The duration, distance (Application-Specific Instruction Processor) to implement the
and average speed of each cycle are reported in Table 1. The algorithm.
various cycles differ in the average speed and electric power
required from the traction battery. In each implementation, every functional component takes
charge of different tasks, including System-in-the-loop
Duration Distance Average communication with MATLAB®/Simulink® (SIL), Cell data
Driving Cycle management, DEKF calculation. In three methods, Nios®II
(min) (km) speed (km/h)
takes charge of SIL and data management tasks. In Nios®II
UDDS 23 12.0 31.5
with matrix processor methods, Nios®II and matrix processor
HWFET 13 16.5 77.5 both do part of the DEKF calculation, and matrix processor
FTP 31 17.8 34.1 processes most of the matrix calculations. In the Nios®II with
EUDC 7 6.5 58.6 DSPbuilder IP method, DSPbuilder IP processes all DEKF
calculation. Finally, the ASIP core does all DEKF calculation
NEDC 20 8.3 25.4 as well.
ECE R15 3 0.9 16.5
WLTP class 3 30 23.2 46.5 x Matrix processor
ArtUrban 17 4.9 17.6
The Matrix Processor is a generic matrix processor IP that
ArtRoad 18 17.3 57.4 was developed using the DSP Builder Advanced Blockset. It
ArtMw130 18 28.7 96.8 can perform sequences of different matrix operations. The
ArtMw150 18 29.5 99.5 user can select the maximum size of matrices to use in order
to scale the usage of internal memory to fit the desired
Table 1: Driving Cycle Details application.

A dynamic model has been implemented to simulate the Matrix Processor includes two data processing cores as in
behaviour of a car model. The mechanical power ܲ௠ is Figure 4. Those are Faddeev and Matrix Multiply cores.
calculated as the sum of three contributions: one linked to the Faddeev core can calculate the operation: ሺ‫ ܦ‬൅ ‫ିܣ כ ܥ‬ଵ ‫ܤ כ‬ሻ.
acceleration, one due to the air resistance and another due to While Matrix Multiply core can calculate ሺ‫ܤ כ ܣ‬ሻ and
the rolling resistance. ሺ‫ ܤ כ ܣ‬൅ ‫ܥ‬ሻ matrix expressions.
ଵ
ܲ௠ ൌ ‫ ݒܨ‬ൌ ሺ‫ݒܯ‬ሶ ൅ ߩ௔௜௥ ܵ‫ܥ‬௫ ‫ ݒ‬ଶ ൅ ߙோ ‫݃ܯ‬ሻ‫ݒ‬ (25)
ଶ

In equation (1),  is the kerb weight,  is the frontal area, ‫ܥ‬௫ Faddeev
Core
is the drag coefficient, R is the rolling resistance, ߩ௔௜௥ is the
air density, g is the gravity acceleration and ‫ ݒ‬is the speed. User
Processor Interface
Memory
The electric power ܲ௘ is obtained from ܲ௠ by using the Matrix
equation below, in which ߟ௪௛௘௘௟ is the efficiency from the Multiply
Core
battery to the wheels and ߟ௥௘௚ is the efficiency in the opposite
direction, i.e., during the regenerative breaking. In order to uCode
Controller
obtain the battery current, the electric power is divided by the
sum of the cell voltages calculated by the battery model.

ଵ ଵା௦௚௡ሺ௉೘ ሻ ଵି௦௚௡ሺ௉೘ሻ Figure 4: Matrix Processor Block Diagram

ܲ௘ ൌ ሺ ൅ ߟ௥௘௚ ሻܲ௠ (26)
ఎೢ೓೐೐೗ ଶ ଶ
The Matrix Processor interface is the main interface between
3.2 Different implementation methods the Matrix Processor and the external environment. It is used
to program the matrix processor for certain μCode, provide
This reference design includes three different methods to input matrix arguments and read-back results.
implement the DEKF algorithm:
In the matrix processor solution, part of the matrix operations
x Nios®II processor with floating point acceleration is accelerated using matrix processor. In the meantime,
(Design A) Nios®II processor can also be busy doing calculations. Figure
x Nios®II with floating point acceleration and floating 5 can described the scheduling of the tasks. Nios®II processor
point matrix processor (Design B) firstly calculates the steps in the blue box. Then matrix
processor can start calculating equations in red box. In the

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 meantime, Nios®II processor can process the steps in the Component LE M9K DSP
green box. Finally, Nios®II finishes the calculation in the
yellow box. DEKF IP 20610 30 29
Matrix processor 6304 35 24
Nios®II processor 2916 32 6
x0 , P0 , q0 , Pq 0
®
qk qk1
Nios II floating
point custom 2204 3 9
Pqk Pqk 1  Qq
instruction core
xk f xk1 , u k 1 , qk1
DDR controller 4785 12 0

P Ak Pk1 AkT  Q
k
Avalon MM
Lx k PkC xTk C xk PkC xTk  R
1
5897 0 0
interconnect
Jtag-AvalonMM
799 1 0
bridge
ASIP 7300 41 26
Pk ( I  Lxk Cxk ) Pk Miscellaneous 1292 23 0
   
x  Lxk yk  g x , uk , q
1
Lqk 
P C Cqk P C  R
qk
T
qk

qk
T
qk xk k k k 1 Design A Total ~14000 57 15
Pq ( I  Lqk Cqk ) Pqk
k Design B Total ~24000 92 39
Design C Total ~33000 84 35
Design ASIP total ~19690 95 32
Reference design
q k qk  Lqk yk  g xk , uk , qk1 Total(not including ~45,000/50,000 136/182 68/288
ASIP)

Figure 5: Tasks scheduling Table 2: Resources breakdown

x DEKF DSPBuilder IP The MAX10 series FPGA has a wide range of selections
available, which ranges from 2k to 50k logic elements.
The DEKF DSP builder IP includes all calculations in the Therefore, depending on different performance requirement,
DEKF. The Nios®II processor only communicates with the one can chose different FPGA chips.
host, sends inputs, and receives results.
3.4 Performance
The DEKF algorithm is relatively complex. If we use DSP
Table 3 contains the execution time to update one cell,
Builder Advanced to generate a direct implementation of the
including the communication time between the Nios software
algorithm in the FPGA fabric, it executes quickly but uses too
and the accelerating IP. We can see that the largest design,
many FPGA resources for a low-cost FPGA device. Instead,
which is the DSP builder IP, has the best performance. And
we use the DSP Builder Advanced feature ‘ALU folding’,
the smallest design, which is the pure software
which automatically generates a design which reuses FPGA
implementation, has the longest execution time.
logic. In this design, using the ALU folder saves around 90%
of the FPGA resources in this design compared to the same
design without folding while still meeting the latency Implementation method Time (μs)
constraint.
Design A (Nios®II + Floating Point IP) 44.9
®
x ASIP core Design B (Nios II + Floating Point IP +
33.8
matrix processor)
Altera's ASIP tool converts a C description (with restrictions) Design C (Nios®II + Floating Point
into a program which runs on a custom processor. 16.5
DEKF DSPbuilder IP)
Design ASIP (Nios®II + Floating Point
3.3 Resources consumption 21.45
ASIP core)
The MAX10 FPGA we use in the design has 50k logic Table 3: Execution time for updating one cell
elements. The resource breakdown of the whole design is
listed in Table 2. Since we implement the algorithm using To have a more direct understanding of the performance
three different methods, the total resource consumptions of together with resources consumption, we combine resource
three implementations are listed respectively as well. consumption and performance to get the number of cells

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 updated per second per logic element, which can be 4 Conclusion
calculated as
In this paper, we present an FPGA implementation of the
ଵ most critical part of a BMS, which is the SOC estimation. We
(27) use DEKF algorithm in the design to estimate the remaining
்௜௠௘்௢௎௣ௗ௔௧௘ை௡௘஼௘௟௟‫כ‬௅௢௚௜௖ா௟௘௠௘௡௧௎௦௔௚௘
capacity of 96 lithium-ion battery cells. Four different
Therefore, we get the numbers in implementation methods are used to calculate the SOC value.
The different implementations allow the user to choose their
preferred balance between execution speed and resource
Number of cells
usage on the FPGA.
Implementation method updated per second per
logic element
Design A (Nios®II + Floating
Acknowledgement
1.59
Point IP) Altera would like to acknowledge the help of Federico
Design B (Nios®II + Floating Baronti and Rocco Morello of the University of Pisa with the
1.23 models and algorithms used in this reference design.
Point IP + matrix processor)
Design C (Nios®II + Floating
1.84 References
Point DEKF DSPbuilder IP)
Design ASIP (Nios®II +
2.37 [1] M. Bingeman and B. Jeppesen, “Improving Battery
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www/global/en_US/pdfs/literature/wp/wp-01247-
Figure 6 shows the detailed information for cell 1, including improving-battery-management-system-performance-and-
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battery-management-system-reference-design-an762/.
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[4] G. L. Plett, “Extended Kalman filtering for battery
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Figure 7: SOC values for 12 cells

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