NXP Semiconductors Document Number: MMPF0100

Data sheet: Technical Data Rev. 20, 5/2022

14 channel configurable power

management integrated circuit PF0100
The PF0100 SMARTMOS power management integrated circuit (PMIC)
provides a highly programmable/ configurable architecture, with fully integrated
power devices and minimal external components. With up to six buck POWER MANAGEMENT
converters, six linear regulators, RTC supply, and coin-cell charger, the
PF0100 can provide power for a complete system, including applications
processors, memory, and system peripherals, in a wide range of applications.
With on-chip one time programmable (OTP) memory, the PF0100 is available
in pre-programmed standard versions, or non-programmed to support custom
programming. The PF0100 is defined to power an entire embedded MCU
platform solution such as i.MX 6 based eReader, IPTV, medical monitoring, and
home/factory automation. EP SUFFIX (E-TYPE) ES SUFFIX (WF-TYPE)
98ASA00405D 98ASA00589D
56 QFN 8X8 56 QFN 8X8
Features:
• Four to six buck converters, depending on configuration Applications:
• Single/Dual phase/ parallel options • Tablets
• DDR termination tracking mode option • IPTV
• Boost regulator to 5.0 V output • eReaders
• Six general purpose linear regulators • Set top boxes
• Programmable output voltage, sequence, and timing • Industrial control
• OTP (one time programmable) memory for device configuration • Medical monitoring
• Coin cell charger and RTC supply • Home automation/ alarm/ energy management
• DDR termination reference voltage
• Power control logic with processor interface and event detection
• I2C control
• Individually programmable ON, OFF, and standby modes

PF0100 i.MX 6X
VREFDDR

SW4 DDR Memory DDR MEMORY

1000 mA INTERFACE

SW3A/B
2500 mA
SW1A/B
2500 mA Processor Core
Voltages
SW1C
2000 mA External AMP
SW2 Microphones
2000 mA SATA - FLASH Speakers
SD-MMC/ SATA NAND - NOR
SWBST NAND Mem. HDD
Interfaces
600 mA Audio
Codec
Control Signals Parallel control/GPIOS

I2 C Communication I2C Communication Sensors

VGEN1
Camera
100 mA Camera
VGEN2 GPS
250 mA WAM
MIPI
GPS uPCIe
VGEN3 MIPI
100 mA
VGEN4 HDMI
350 mA LDVS Display
VGEN5
100 mA
USB
LICELL VGEN6 Ethernet
Charger 200 mA CAN

Main Supply
COINCELL
2.8 – 4.5 V Front USB Rear Seat Rear USB
Cluster/HUD
POD Infotaiment POD

Figure 1. Simplified application diagram

© NXP B.V. 2022.

 Table of Contents
1 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3.1 General specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3.2 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.1 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.2 Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Functional block requirements and behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1.1 Device start-up configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1.2 One time programmability (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.3 OTP prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1.4 Reading OTP fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1.5 Programming OTP fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 16 MHz and 32 kHz clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2.1 Clock adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 Bias and references block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3.1 Internal core voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3.2 VREFDDR voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.1 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.2 State machine flow summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4.3 Power tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4.4 Buck regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4.5 Boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.4.6 LDO regulators description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.4.7 VSNVS LDO/switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.5 Control interface I2C block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.5.1 I2C device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.5.2 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.5.3 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.5.4 Interrupt bit summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.5.5 Specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.5.6 Register bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

PF0100

2 NXP Semiconductors
7 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7.1.1 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7.1.2 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7.2 PF0100 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.2.1 General board recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.2.2 Component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.2.3 General routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.2.4 Parallel routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.2.5 Switching regulator layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
7.3 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.3.1 Rating data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.3.2 Estimation of junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
8.1 Packaging dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9 Reference section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
9.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

PF0100

NXP Semiconductors 3
ORDERABLE PARTS

1 Orderable parts
The PF0100 is available with both pre-programmed and non-programmed OTP memory configurations. The non-programmed device uses
“NP” as the programming code. The pre-programmed devices are identified using the program codes from Table 1, which also list the
associated NXP reference designs where applicable. Details of the OTP programming for each device can be found in Table 10.

Table 1. Orderable Part Variations

Part Number Temperature (TA) Package Programming Reference Designs Notes

MMPF0100NPAEP NP N/A

MCIMX6Q-SDP (1), (2)

MMPF0100F0AEP F0 MCIMX6Q-SDB
MCIMX6DL-SDP

MMPF0100F1AEP F1 MCIMX6SLEVK
(1), (2), (3)
-40 °C to 85 °C
MMPF0100F2AEP 56 QFN 8x8 mm - 0.5 mm pitch F2 N/A
(for use in consumer E-Type QFN (full lead)
MMPF0100F3AEP applications) F3 N/A

MMPF0100F4AEP F4 N/A (1), (2)

MMPF0100F6AEP F6 MCIMX6SX-SDB
MMPF0100FCAEP FC N/A
(1), (2)
MMPF0100FDAEP FD MCIMX6SLLEVK

MMPF0100NPANES NP N/A (1), (2), (4)

MCIMX6Q-SDP
MMPF0100F0ANES F0 MCIMX6Q-SDB
MCIMX6DL-SDP

MMPF0100F3ANES F3 N/A (1), (2)

MMPF0100F4ANES -40 °C to 105 °C F4 N/A

56 QFN 8x8 mm - 0.5 mm pitch
(for use in extended WF-Type QFN (wettable flank)
MMPF0100F6ANES industrial applications) F6 MCIMX6SX-SDB

MMPF0100F9ANES F9 N/A

MMPF0100FAANES FA N/A (1), (2), (4)

MMPF0100FBANES FB N/A

MMPF0100FCANES FC N/A (1), (2)

Notes
1. For tape and reel, add an R2 suffix to the part number.
2. For programming details see Table 10. The available OTP options are not restricted to the listed reference designs. They can be used in any
application where the listed voltage and sequence details are acceptable.
3. For designs using the i.MX 6SoloLite, it is recommended to use the F3 OTP option instead of the F1 OTP option and F4 OTP option instead of
the F2 OTP option.
4. SW2 can support an output current rating of 2.5 A in NP, F9, and FA Industrial versions only (ANES suffix) when SW2ILIM=0

PF0100

4 NXP Semiconductors
 ORDERABLE PARTS

1.1 PF0100 version differences

PF0100A is an improved version of the PF0100 power management IC. Table 2 summarizes the difference between the two versions and
should be referred to when migrating from the PF0100 to the PF0100A. Note that programming options are the same for both versions of
the device.

Table 2. Differences between PF0100 and PF0100A

Description PF0100 PF0100A

Reading SILICON REV register at address 0x03 Reading SILICON REV register at address 0x03
Version identification returns 0x11. DEVICEID register at address 0x00 returns 0x21. DEVICEID register at address 0x00
reads 0x10 in PF0100 and PF0100A reads 0x10 in PF0100 and PF0100A

VSNVS current limit VSNVS current limit increased in the PF0100A

In the PF0100, FUSE_POR1, FUSE_POR2, and In the PF0100A, the XOR function is removed. It is
FUSE_POR3 bits are XOR’ed into the required to set FUSE_POR1, FUSE_POR2, and
OTP_FUSE_PORx register setting during OTP FUSE_POR_XOR bit. The FUSE_POR_XOR bit FUSE_POR3 bits during OTP programming.
programming has to be 1 for fuses to be loaded during startup.
This can be achieved by setting any one or all of the
FUSE_PORx bits during OTP programming.

Erratum ER19 applicable to PF0100. Applications Errata ER19 fixed in PF0100A. External
expecting to operate in the conditions mentioned in workaround not required
Erratum ER19 ER19 need to implement an external workaround to
overcome the problem. Refer to the product errata
for details

Erratum ER20 Erratum ER20 applicable to PF0100 Errata ER20 fixed in PF0100A

Errata ER22 fixed in PF0100A. Workaround not

Erratum ER22 Erratum ER22 applicable to PF0100
required

In addition to the version differences, Table 3 shows the differences on the test temperature rating for each version of PF0100 covered
on this datasheet.

Table 3. Ambient temperature range

Ambient temperature range

Device Qualification tier
(TMIN to TMAX)

MMPF0100 Consumer and Industrial TA = -40 °C to 85 °C

MMPF0100A Consumer TA = -40 °C to 85 °C

MMPF0100AN Extended Industrial TA = -40 °C to 105 °C

PF0100

NXP Semiconductors 5
INTERNAL BLOCK DIAGRAM

2 Internal block diagram

PF0100
SW1FB
VIN1 VGEN1
100 mA SW1AIN
VGEN1 O/P
SW1A/B
Drive
Single/Dual SW1ALX
VGEN2 2500 mA
VGEN2 Buck
250 mA SW1BLX
O/P
Drive
SW1BIN
VIN2 VGEN3
VGEN3 100 mA

O/P SW1CLX
SW1C Drive SW1CIN
VGEN4
VGEN4 350 mA 2000 mA
Buck
SW1CFB
Core Control logic SW1VSSSNS
VIN3 VGEN5
100 mA
VGEN5

Initialization State Machine SW2 O/P

SW2LX
VGEN6 2000 mA Drive SW2IN
VGEN6 200 mA Buck SW2IN
SW2FB

OTP Supplies
SW3AFB
Control
O/P SW3AIN
VDDOTP
SW3A/B Drive SW3ALX
CONTROL Single/Dual
DDR

VDDIO
I2C 2500 mA O/P SW3BLX
Buck
SCL
Interface Drive SW3BIN

SDA
DVS CONTROL SW3BFB
DVS Control SW3VSSSNS

SW4FB

SW4
1000 mA O/P SW4IN
2 Buck Drive
I C Register Trim-In-Package SW4LX
VCOREDIG GNDREF1
map
VCOREREF
Reference
Generation
Clocks and SWBST O/P
SWBSTLX
VCORE resets 600 mA Drive
Boost SWBSTIN
GNDREF
SWBSTFB

VREFDDR

VINREFDDR
Clocks
32 kHz and 16 MHz
VHALF

VIN
Best
Li Cell
of
Charger
Supply
LICELL

VSNVS
ICTEST

PWRON

RESETBMCU
VSNVS

STANDBY

SDWNB

INTB

Figure 2. Simplified internal block diagram

PF0100

6 NXP Semiconductors
 PIN CONNECTIONS

3 Pin connections

3.1 Pinout diagram

VCOREREF

VCOREDIG

SWBSTFB
SWBSTLX

SWBSTIN
GNDREF

VDDOTP
PWRON

VCORE

VSNVS
VDDIO

SDA
SCL

VIN
56 55 54 53 52 51 50 49 48 47 46 45 44 43

INTB 1 42 LICELL

SDWNB 2 41 VGEN6

RESETBMCU 3 40 VIN3

STANDBY 4 39 VGEN5

ICTEST 5 38 SW3AFB

SW1FB 6 37 SW3AIN

SW1AIN 7 EP 36 SW3ALX

SW1ALX 8 35 SW3BLX

SW1BLX 9 34 SW3BIN

SW1BIN 10 33 SW3BFB

SW1CLX 11 32 SW3VSSSNS

SW1CIN 12 31 VREFDDR

SW1CFB 13 30 VINREFDDR

SW1VSSSNS 14 29 VHALF

15 16 17 18 19 20 21 22 23 24 25 26 27 28
GNDREF1

VIN1

SW4FB

SW4IN

SW4LX

SW2LX

SW2IN

SW2IN

SW2FB
VGEN1

VGEN2

VGEN3

VIN2

VGEN4

Figure 3. Pinout diagram

PF0100

NXP Semiconductors 7
PIN CONNECTIONS

3.2 Pin definitions

Table 4. PF0100 pin definitions

Pin
Pin number Pin name Max rating Type Definition
function

1 INTB O 3.6 V Digital Open drain interrupt signal to processor

2 SDWNB O 3.6 V Digital Open drain signal to indicate an imminent system shutdown

Open drain reset output to processor. Alternatively can be used as a power

3 RESETBMCU O 3.6 V Digital
good output.

4 STANDBY I 3.6 V Digital Standby input signal from processor

Digital/
5 ICTEST I 7.5 V Reserved pin. Connect to GND in application.
Analog

Output voltage feedback for SW1A/B. Route this trace separately from the
6 SW1FB (6) I 3.6 V Analog
high current path and terminate at the output capacitance.

Input to SW1A regulator. Bypass with at least a 4.7 μF ceramic capacitor

7 SW1AIN (6) I 4.8 V Analog
and a 0.1 μF decoupling capacitor as close to the pin as possible.

8 SW1ALX (6) O 4.8 V Analog Regulator 1A switch node connection

(6)
9 SW1BLX O 4.8 V Analog Regulator 1B switch node connection

Input to SW1B regulator. Bypass with at least a 4.7 μF ceramic capacitor

10 SW1BIN (6) I 4.8 V Analog
and a 0.1 μF decoupling capacitor as close to the pin as possible.

11 SW1CLX (6) O 4.8 V Analog Regulator 1C switch node connection

Input to SW1C regulator. Bypass with at least a 4.7 μF ceramic capacitor

12 SW1CIN (6) I 4.8 V Analog
and a 0.1 μF decoupling capacitor as close to the pin as possible.

Output voltage feedback for SW1C. Route this trace separately from the
13 SW1CFB (6) I 3.6V Analog
high current path and terminate at the output capacitance.
Ground reference for regulators SW1ABC. It is connected externally to
14 SW1VSSSNS GND - GND
GNDREF through a board ground plane.

Ground reference for regulators SW2 and SW4. It is connected externally to

15 GNDREF1 GND - GND
GNDREF, via board ground plane.

16 VGEN1 O 2.5 V Analog VGEN1 regulator output, Bypass with a 2.2 μF ceramic output capacitor.

VGEN1, 2 input supply. Bypass with a 1.0 μF decoupling capacitor as close

17 VIN1 I 3.6 V Analog
to the pin as possible.

18 VGEN2 O 2.5 V Analog VGEN2 regulator output, Bypass with a 4.7 μF ceramic output capacitor.

Output voltage feedback for SW4. Route this trace separately from the high
19 SW4FB (6) I 3.6 V Analog
current path and terminate at the output capacitance.

Input to SW4 regulator. Bypass with at least a 4.7μF ceramic capacitor and
20 SW4IN (6) I 4.8 V Analog
a 0.1 μF decoupling capacitor as close to the pin as possible.

21 SW4LX (6) O 4.8 V Analog Regulator 4 switch node connection

(6)
22 SW2LX O 4.8 V Analog Regulator 2 switch node connection
(6)
23 SW2IN I 4.8 V Analog Input to SW2 regulator. Connect pin 23 together with pin 24 and bypass with
at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as
24 SW2IN (6) I 4.8 V Analog close to these pins as possible.

Output voltage feedback for SW2. Route this trace separately from the high
25 SW2FB (6) I 3.6 V Analog
current path and terminate at the output capacitance.

26 VGEN3 O 3.6 V Analog VGEN3 regulator output. Bypass with a 2.2 μF ceramic output capacitor.
VGEN3,4 input. Bypass with a 1.0 μF decoupling capacitor as close to the
27 VIN2 I 3.6 V Analog
pin as possible.

28 VGEN4 O 3.6 V Analog VGEN4 regulator output, Bypass with a 4.7 μF ceramic output capacitor.

PF0100

8 NXP Semiconductors
 PIN CONNECTIONS

Table 4. PF0100 pin definitions (continued)

Pin
Pin number Pin name Max rating Type Definition
function

29 VHALF I 3.6 V Analog Half supply reference for VREFDDR

VREFDDR regulator input. Bypass with at least 1.0 μF decoupling capacitor

30 VINREFDDR I 3.6 V Analog
as close to the pin as possible.

31 VREFDDR O 3.6 V Analog VREFDDR regulator output

Ground reference for the SW3 regulator. Connect to GNDREF externally via
32 SW3VSSSNS GND - GND
the board ground plane.

Output voltage feedback for SW3B. Route this trace separately from the high
33 SW3BFB (6) I 3.6 V Analog
current path and terminate at the output capacitance.

Input to SW3B regulator. Bypass with at least a 4.7 μF ceramic capacitor

34 SW3BIN (6) I 4.8 V Analog
and a 0.1 μF decoupling capacitor as close to the pin as possible.

35 SW3BLX (6) O 4.8 V Analog Regulator 3B switch node connection

(6)
36 SW3ALX O 4.8 V Analog Regulator 3A switch node connection

Input to SW3A regulator. Bypass with at least a 4.7 μF ceramic capacitor

37 SW3AIN (6) I 4.8 V Analog
and a 0.1 μF decoupling capacitor as close to the pin as possible.

Output voltage feedback for SW3A. Route this trace separately from the high
38 SW3AFB (6) I 3.6 V Analog
current path and terminate at the output capacitance.

39 VGEN5 O 3.6 V Analog VGEN5 regulator output. Bypass with a 2.2 μF ceramic output capacitor.

VGEN5, 6 input. Bypass with a 1.0 μF decoupling capacitor as close to the

40 VIN3 I 4.8 V Analog
pin as possible.

41 VGEN6 O 3.6 V Analog VGEN6 regulator output. By pass with a 2.2 μF ceramic output capacitor.

42 LICELL I/O 3.6 V Analog Coin cell supply input/output

43 VSNVS O 3.6 V Analog LDO or coin cell output to processor

Boost regulator feedback. Connect this pin to the output rail close to the
44 SWBSTFB (6) I 5.5 V Analog
load. Keep this trace away from other noisy traces and planes.

Input to SWBST regulator. Bypass with at least a 2.2 μF ceramic capacitor

45 SWBSTIN (6) I 4.8 V Analog
and a 0.1 μF decoupling capacitor as close to the pin as possible.
46 SWBSTLX (6) O 7.5 V Analog SWBST switch node connection

Digital and
47 VDDOTP I 10 V(5) Supply to program OTP fuses
Analog

48 GNDREF GND - GND Ground reference for the main band gap regulator.

49 VCORE O 3.6 V Analog Analog Core supply

50 VIN I 4.8 V Analog Main chip supply

51 VCOREDIG O 1.5 V Analog Digital Core supply

52 VCOREREF O 1.5 V Analog Main band gap reference

53 SDA I/O 3.6 V Digital I2C data line (Open drain)

54 SCL I 3.6 V Digital I2C clock

55 VDDIO I 3.6 V Analog Supply for I2C bus. Bypass with 0.1 μF ceramic capacitor

56 PWRON I 3.6 V Digital Power On/off from processor

Expose pad. Functions as ground return for buck regulators. Tie this pad to
- EP GND - GND the inner and external ground planes through vias to allow effective thermal
dissipation.

Notes
5. 10 V Maximum voltage rating during OTP fuse programming. 7.5 V Maximum DC voltage rated otherwise.
6. Unused switching regulators should be connected as follow: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should be
connected to VIN with a 0.1 μF bypass capacitor.

PF0100

NXP Semiconductors 9
GENERAL PRODUCT CHARACTERISTICS

4 General product characteristics

4.1 Absolute maximum ratings

Table 5. Absolute maximum ratings

All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause malfunction or permanent damage
to the device. The detailed maximum voltage rating per pin can be found in the pin list section.

Symbol Description Value Unit Notes

Electrical ratings

VIN Main input supply voltage -0.3 to 4.8 V

VDDOTP OTP programming input supply voltage -0.3 to 10 V

VLICELL Coin cell voltage -0.3 to 3.6 V

ESD ratings
(7)
VESD Human body model ±2000 V
Charge device model ±500
Notes
7. ESD testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM),
robotic (CZAP = 4.0 pF).

PF0100

10 NXP Semiconductors
 GENERAL PRODUCT CHARACTERISTICS

4.2 Thermal characteristics

Table 6. Thermal ratings

Symbol Description (rating) Min. Max. Unit Notes

Thermal ratings

Ambient operating temperature range

• PF0100 -40 85
TA °C
• PF0100A -40 85
• PF0100AN -40 105

°C (8)
TJ Operating junction temperature range -40 125

TST Storage temperature range -65 150 °C

TPPRT Peak package reflow temperature – Note 10 °C (9)(10)

QFN56 thermal resistance and package dissipation ratings

Junction to ambient
• Natural convection (11)(12)(13)
RθJA °C/W
• Four layer board (2s2p) – 28
• Eight layer board (2s6p) – 15

Junction to ambient (@200 ft/min) (11)(13)

RθJMA °C/W
• Four layer board (2s2p) – 22
(14)
RθJB Junction to board – 10 °C/W
(15)
RΘJCBOTTOM Junction to case bottom – 1.2 °C/W

Junction to package top (16)

ΨJT – 2.0 °C/W
• Natural convection
Notes
8. Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See Table 7 for
thermal protection features.
9. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a
malfunction or permanent damage to the device.
10. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and
Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable
parts, and review parametrics.
11. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
12. The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5.
13. Per JEDEC JESD51-6 with the board horizontal.
14. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the
board near the package.
15. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
16. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-
2. When Greek letter (Ψ) are not available, the thermal characterization parameter is written as Psi-JT.

4.2.1 Power dissipation

During operation, the temperature of the die should not exceed the operating junction temperature noted in Table 6. To optimize the
thermal management and to avoid overheating, the PF0100 provides thermal protection. An internal comparator monitors the die
temperature. Interrupts THERM110I, THERM120I, THERM125I, and THERM130I are generated when the respective thresholds specified
in Table 7 are crossed in either direction. The temperature range can be determined by reading the THERMxxxS bits in register
INTSENSE0.
In the event of excessive power dissipation, thermal protection circuitry shuts down the PF0100. This thermal protection acts above the
thermal protection threshold listed in Table 7. To avoid any unwanted power downs resulting from internal noise, the protection is
debounced for 8.0 ms. This protection should be considered as a fail-safe mechanism and therefore the system should be configured so
protection is not tripped under normal conditions.

PF0100

NXP Semiconductors 11
GENERAL PRODUCT CHARACTERISTICS

Table 7. Thermal protection thresholds

Parameter Min. Typ. Max. Units

Thermal 110 °C Threshold (THERM110) 100 110 120 °C

Thermal 120 °C Threshold (THERM120) 110 120 130 °C

Thermal 125 °C Threshold (THERM125) 115 125 135 °C

Thermal 130 °C Threshold (THERM130) 120 130 140 °C

Thermal Warning Hysteresis 2.0 – 4.0 °C

Thermal Protection Threshold 130 140 150 °C

4.3 Electrical characteristics

4.3.1 General specifications

Table 8. General PMIC static characteristics.
TMIN to TMAX (See Table 3), VIN = 2.8 to 4.5 V, VDDIO = 1.7 to 3.6 V, typical external component values and full load current range, unless
otherwise noted.

Pin name Parameter Load condition Min. Max. Unit

VIL – 0.0 0.2 * VSNVS V

PWRON
VIH – 0.8 * VSNVS 3.6 V
VOL -2.0 mA 0.0 0.4 V
RESETBMCU
VOH Open Drain 0.7* VIN VIN V

VIL – 0.0 0.2 * VDDIO V

SCL
VIH – 0.8 * VDDIO 3.6 V

VIL – 0.0 0.2 * VDDIO V

VIH – 0.8 * VDDIO 3.6 V

SDA
VOL -2.0 mA 0.0 0.4 V

VOH Open Drain 0.7*VDDIO VDDIO V

VOL -2.0 mA 0.0 0.4 V

INTB
VOH Open Drain 0.7* VIN VIN V

VOL -2.0 mA 0.0 0.4 V

SDWNB
VOH Open Drain 0.7* VIN VIN V

VIL – 0.0 0.2 * VSNVS V

STANDBY
VIH – 0.8 * VSNVS 3.6 V

VIL – 0.0 0.3 V

VDDOTP
VIH – 1.1 1.7 V

PF0100

12 NXP Semiconductors
 GENERAL PRODUCT CHARACTERISTICS

4.3.2 Current consumption

Table 9. Current consumption summary
TMIN to TMAX (See Table 3), VIN = 3.6 V, VDDIO = 1.7 V to 3.6 V, LICELL = 1.8 V to 3.3 V, VSNVS = 3.0 V, typical external component
values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VDDIO = 3.3 V, LICELL = 3.0 V, VSNVS = 3.0 V and
25 °C, unless otherwise noted.

Mode PF0100 conditions System conditions Typical MAX Unit Notes

VSNVS from LICELL

All other blocks off (17),(19),
Coin Cell No load on VSNVS 4.0 7.0 μA (23)
VIN = 0.0 V
VSNVSVOLT[2:0] = 110

VSNVS from VIN or LICELL

Wake-up from PWRON active
Off (18),(19)
MMPF0100
32 k RC on No load on VSNVS, PMIC able to wake-up 16 21 μA
All other blocks off
VIN ≥ UVDET

VSNVS from VIN or LICELL

Wake-up from PWRON active
Off (18),(19)
MMPF0100A
32 k RC on No load on VSNVS, PMIC able to wake-up 17 25 μA
All other blocks off
VIN ≥ UVDET

VSNVS from VIN

Wake-up from PWRON active
Trimmed reference active 122 220(22)
No load on VSNVS. DDR memories in self (19)
Sleep SW3A/B PFM
refresh
μA
Trimmed 16 MHz RC off 122 250(21)
32 k RC on
VREFDDR disabled

VSNVS from either VIN or LICELL

SW1A/B combined in PFM
SW1C in PFM
SW2 in PFM
SW3A/B combined in PFM No load on VSNVS. Processor enabled in 297 450 (20)
Standby (19)
MMPF0100
SW4 in PFM low power mode. All rails powered on μA
SWBST off except boost (load = 0 mA) 297 1000 (22)
Trimmed 16 MHz RC enabled
Trimmed reference active
VGEN1-6 enabled
VREFDDR enabled

VSNVS from either VIN or LICELL

SW1A/B combined in PFM
SW1C in PFM
SW2 in PFM
SW3A/B combined in PFM No load on VSNVS. Processor enabled in 297 450 (22)
Standby (19)
MMPF0100A
SW4 in PFM low power mode. All rails powered on μA
SWBST off except boost (load = 0 mA) 297 550(21)
Trimmed 16 MHz RC enabled
Trimmed reference active
VGEN1-6 enabled
VREFDDR enabled

Notes
17. Refer to Figure 4 for coin cell mode characteristics over temperature.
18. When VIN is below the UVDET threshold, in the range of 1.8 V ≤ VIN < 2.65 V, the quiescent current increases by 50 μA, typically.
19. For PFM operation, headroom should be 300 mV or greater.
20. From 0 °C to 85 °C
21. From -40 °C to 105 °C, applicable only to extended industrial parts.
22. From -40 °C to 85 °C, applicable to consumer, industrial and extended industrial part numbers.
23. Additional current may be drawn in the coin cell mode when RESETBMCU is pulled up to VSNVS due an internal path from RESETBMCU to VIN.
The additional current is < 30 μA with a pull up resistor of 100 kΩ. The i.MX 6x processors have an internal pull up from the POR_B pin to the
VDD_SNVS_IN pin. For i.MX 6x applications, if additional current in the coin cell mode is not desired, use an external switch to disconnect the
RESETBMCU path when VIN is removed. For non-i.MX 6 applications, pull-up RESETBMCU to a rail off in the coin cell mode.

PF0100

NXP Semiconductors 13
GENERAL PRODUCT CHARACTERISTICS

Coin cell mode

Coin Cell mode current (uA)

100

MMPF0100
10
MMPF0100A

1
-40 -20 0 20 40 60 80
Temperature (°C)
Temperature (oC)
Figure 4. Coin cell mode current vs temperature

PF0100

14 NXP Semiconductors
 GENERAL DESCRIPTION

5 General description
The PF0100 is the power management integrated circuit (PMIC) designed primarily for use with NXP’s i.MX 6 series of application
processors.

5.1 Features
This section summarizes the PF0100 features.
• Input voltage range to PMIC: 2.8 V - 4.5 V
• Buck regulators
• Four to six channel configurable
• SW1A/B/C, 4.5 A (single); 0.3 V to 1.875 V
• SW1A/B, 2.5 A (single/dual); SW1C 2.0 A (independent); 0.3 V to 1.875 V
• SW2, 2.0 A; 0.4 V to 3.3 V (2.5 A; 1.2 V to 3.3 V (24))
• SW3A/B, 2.5 A (single/dual); 0.4 V to 3.3 V
• SW3A, 1.25 A (independent); SW3B, 1.25 A (independent); 0.4 V to 3.3 V
• SW4, 1.0 A; 0.4 V to 3.3 V
• SW4, VTT mode provide DDR termination at 50% of SW3A
• Dynamic voltage scaling
• Modes: PWM, PFM, APS
• Programmable output voltage
• Programmable current limit
• Programmable soft start
• Programmable PWM switching frequency
• Programmable OCP with fault interrupt
• Boost regulator
• SWBST, 5.0 V to 5.15 V, 0.6 A, OTG support
• Modes: PFM and auto
• OCP fault interrupt
• LDOs
• Six user programable LDO
• VGEN1, 0.80 V to 1.55 V, 100 mA
• VGEN2, 0.80 V to 1.55 V, 250 mA
• VGEN3, 1.8 V to 3.3 V, 100 mA
• VGEN4, 1.8 V to 3.3 V, 350 mA
• VGEN5, 1.8 V to 3.3 V, 100 mA
• VGEN6, 1.8 V to 3.3 V, 200 mA
• Soft start
• LDO/switch supply
• VSNVS (1.0/1.1/1.2/1.3/1.5/1.8/3.0 V), 400 μA
• DDR memory reference voltage
• VREFDDR, 0.6 V to 0.9 V, 10 mA
• 16 MHz internal master clock
• OTP(one time programmable) memory for device configuration
• User programmable start-up sequence and timing
• Battery backed memory including coin cell charger
• I2C interface
• User programmable standby, sleep, and off modes

Notes
24. SW2 capable of 2.5 A in NP, F9, and FA Industrial versions only (ANES suffix)

PF0100

NXP Semiconductors 15
GENERAL DESCRIPTION

5.2 Functional block diagram

MMPF0100 functional internal block diagram

OTP startup configuration Power generation

OTP prototyping Switching regulators Linear regulators
Voltage
(Try before buy)
SW1A/B/C VGEN1
Sequence and Phasing and (0.3 V to 1.875 V) (0.8 V to 1.55 V, 100 mA)
timing frequency selection Configurable 4.5 A or
2.5 A+2.0 A VGEN2
Bias & references (0.8 V to 1.55 V, 250 mA)

Internal core voltage reference SW2

(0.4 V to 3.3 V, 2.0 A) VGEN3
(1.8 V to 3.3 V, 100 mA)
DDR voltage reference

SW3A/B VGEN4
(0.4 V to 3.3 V) (1.8 V to 3.3 V, 350 mA)
Logic and control
Configurable 2.5 A
Parallel MCU interface Regulator control or 1.25 A+1.25 A VGEN5
(1.8 V to 3.3 V, 100 mA)
2
I C communication and registers
SW4 VGEN6
(0.4 V to 3.3 V, 1.0 A) (1.8 V to 3.3 V, 200 mA)
Fault detection and protection
VSNVS
Boost Regulator
Thermal Current limit (1.0 V to 3.0 V, 400 μA)
(5.0 V to 5.15 V, 600 mA)
RTC supply with coin cell
USB OTG Supply
Short-circuit charger

Figure 5. Functional block diagram

5.3 Functional description

5.3.1 Power generation

The PF0100 PMIC features four buck regulators (up to six independent outputs), one boost regulator, six general purpose LDOs, one
switch/LDO combination and a DDR voltage reference to supply voltages for the application processor and peripheral devices.
The number of independent buck regulator outputs can be configured from four to six, thereby providing flexibility to operate with higher
current capability, or to operate as independent outputs for applications requiring more voltage rails with lower current demands. Further,
SW1 and SW3 regulators can be configured as single/dual phase and/or independent converters. One of the buck regulators, SW4, can
also operate as a tracking regulator when used for memory termination. The buck regulators provide the supply to processor cores and
to other low voltage circuits such as IO and memory. Dynamic voltage scaling is provided to allow controlled supply rail adjustments for
the processor cores and/or other circuitry.
Depending on the system power path configuration, the six general purpose LDO regulators can be directly supplied from the main input
supply or from the switching regulators to power peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. A specific VREFDDR
voltage reference is included to provide accurate reference voltage for DDR memories operating with or without VTT termination. The
VSNVS block behaves as an LDO, or as a bypass switch to supply the SNVS/SRTC circuitry on the i.MX processors; VSNVS may be
powered from VIN, or from a coin cell.

5.3.2 Control logic

The PF0100 PMIC is fully programmable via the I2C interface. Additional communication is provided by direct logic interfacing including
interrupt and reset. Start-up sequence of the device is selected upon the initial OTP configuration explained in the Start-up section, or by
configuring the “Try Before Buy” feature to test different power up sequences before choosing the final OTP configuration.
The PF0100 PMIC has the interfaces for the power buttons and dedicated signaling interfacing with the processor. It also ensures supply
of critical internal logic and other circuits from the coin cell in case of brief interruptions from the main battery. A charger for the coin cell
is included as well.

PF0100

16 NXP Semiconductors
 GENERAL DESCRIPTION

5.3.2.1 Interface signals

5.3.2.1.1 PWRON
PWRON is an input signal to the IC generating a turn-on event. It can be configured to detect a level, or an edge using the PWRON_CFG
bit. Refer to section 6.4.2.1 Turn on events, page 31 for more details.

5.3.2.1.2 STANDBY
STANDBY is an input signal to the IC. When it is asserted the part enters standby mode and when de-asserted, the part exits standby
mode. STANDBY can be configured as active high or active low using the STANDBYINV bit. Refer to the section 6.4.1.3 Standby mode,
page 29 for more details.
Note: When operating the PMIC at VIN ≤ 2.85 V and VSNVS is programmed for a 3.0 V output, a coin cell must be present to provide
VSNVS, or the PMIC does not reliably enter and exit the STANDBY mode.

5.3.2.1.3 RESETBMCU
RESETBMCU is an open drain, active low output configurable for two modes of operation. In its default mode, it is de-asserted 2.0 ms to
4.0 ms after the last regulator in the start-up sequence is enabled; refer to Figure 6 as an example. In this mode, the signal can be used
to bring the processor out of reset, or as an indicator that all supplies have been enabled; it is only asserted for a turn-off event.
When configured for its fault mode, RESETBMCU is de-asserted after the start-up sequence is completed only if no faults occurred during
start-up. At anytime, if a fault occurs and persists for 1.8 ms typically, RESETBMCU is asserted, LOW. The PF0100 is turned off if the
fault persists for more than 100 ms typically. The PWRON signal restarts the part, though if the fault persists, the sequence described
above is repeated. To enter the fault mode, set bit OTP_PG_EN of register OTP PWRGD EN to “1”. This register, 0xE8, is located on
Table 137 of the register map. To test the fault mode, the bit may be set during TBB prototyping, or the mode may be permanently chosen
by programming OTP fuses.

5.3.2.1.4 SDWNB
SDWNB is an open drain, active low output notifying the processor of an imminent PMIC shut down. It is asserted low for one 32 kHz clock
cycle before powering down and is then de-asserted in the OFF state.

5.3.2.1.5 INTB
INTB is an open drain, active low output. It is asserted when any fault occurs, provided the fault interrupt is unmasked. INTB is de-asserted
after the fault interrupt is cleared by software, which requires writing a “1” to the fault interrupt bit.

PF0100

NXP Semiconductors 17
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6 Functional block requirements and behaviors

6.1 Start-up
The PF0100 can be configured to start-up from either the internal OTP configuration, or with a hard-coded configuration built in to the
device. The internal hard-coded configuration is enabled by connecting the VDDOTP pin to VCOREDIG through a 100 kΩ resistor. The
OTP configuration is enabled by connecting VDDOTP to GND.
For NP devices, selecting the OTP configuration causes the PF0100 to not start-up. However, the PF0100 can be controlled through the
I2C port for prototyping and programming. Once programmed, the NP device starts up with the customer programmed configuration.

6.1.1 Device start-up configuration

Table 10 shows the default configuration, which can be accessed on all devices as described previously, as well as the pre-programmed
OTP configurations.

Table 10. Start-up configuration

Default
Pre-programmed OTP configuration
Registers configuration

All devices F0 F1(25) F2(25) F3 F4 F6 F9 FA FB FC FD

2
Default I C Address 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08

VSNVS_VOLT 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V

SW1AB_VOLT 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.2 V

SW1AB_SEQ 1 1 1 1 2 2 2 5 5 2 2 2

SW1C_VOLT 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.375 V 1.2 V

SW1C_SEQ 1 2 1 1 2 2 2 5 5 2 2 2

SW2_VOLT 3.0 V 3.3 V 3.15 V 3.15 V 3.15 V 3.15 V 3.3 V 1.375 V 1.375 V 3.3 V 3.3 V 3.15 V

SW2_SEQ 2 5 2 2 1 1 4 5 5 6 5 1

SW3A_VOLT 1.5 V 1.5 V 1.2 V 1.5 V 1.2 V 1.5 V 1.35 V 1.350 V 1.5 V 1.2 V 1.35 V 1.2 V

SW3A_SEQ 3 3 4 4 4 4 3 6 6 4 3 4

SW3B_VOLT 1.5 V 1.5 V 1.2 V 1.5 V 1.2 V 1.5 V 1.35 V 1.350 V 1.5 V 1.2 V 1.35 V 1.2 V

SW3B_SEQ 3 3 4 4 4 4 3 6 6 4 3 4

SW4_VOLT 1.8 V 3.15 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.825 V 1.825 V 1.8 V 3.15 V 1.8 V

SW4_SEQ 3 6 3 3 3 3 4 7 7 3 6 3

SWBST_VOLT - 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V

SWBST_SEQ - 13 6 6 6 6 Off 10 10 Off 13 6

VREFDDR_SEQ 3 3 4 4 4 4 3 6 6 4 3 4

VGEN1_VOLT - 1.5 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.5 V 1.5 V 1.2 V

VGEN1_SEQ - 9 4 4 4 4 5 - - 3 9 -

VGEN2_VOLT 1.5 V 1.5 V - - - - 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V

VGEN2_SEQ 2 10 - - - - Off 8 8 Off 10 7

VGEN3_VOLT - 2.5 V - - - - 2.8 V 1.8 V 1.8 V 2.5 V 2.5 V 1.8 V

VGEN3_SEQ - 11 - - - - 5 8 8 Off 11 7

VGEN4_VOLT 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 3.0 V 3.0 V 1.8 V 1.8V 1.8 V

VGEN4_SEQ 3 7 3 3 3 3 4 4 4 7 7 3

VGEN5_VOLT 2.5 V 2.8 V 2.5 V 2.5 V 2.5 V 2.5 V 3.3 V 2.5 V 2.5 V 2.8 V 2.8 V 2.5 V

PF0100

18 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 10. Start-up configuration (continued)

Default
Pre-programmed OTP configuration
Registers configuration

All devices F0 F1(25) F2(25) F3 F4 F6 F9 FA FB FC FD

VGEN5_SEQ 3 12 5 5 5 5 5 8 8 1 1 5

VGEN6_VOLT 2.8 V 3.3 V - - - - 3.0 V 2.8 V 2.8 V 3.3 V 3.3 V 2.8 V

VGEN6_SEQ 3 8 - - - - 1 7 7 8 8 7

PU CONFIG,
1.0 ms 2.0 ms 1.0 ms 1.0 ms 1.0 ms 1.0 ms 0.5 ms 0.5 ms 0.5 ms 2.0 ms 2.0 ms 1.0 ms
SEQ_CLK_SPEED

PU CONFIG, 1.5625 mV 12.5 mV/ 12.5 mV/ 12.5 mV/ 12.5 mV/ 6.25 mV/ 1.5625 mV/ 1.5625 mV/
6.25 mV/μs 6.25 mV/μs 6.25 mV/μs 12.5 mV/μs
SWDVS_CLK /μs μs μs μs μs μs μs μs

PU CONFIG,
Level sensitive
PWRON
SW1ABC Single SW1AB Single Phase, SW1C
SW1AB CONFIG SW1AB Single Phase, SW1C Independent Mode, 2.0 MHz Phase, 2.0 MHz Independent mode, 2.0 MHz

SW1C CONFIG 2.0 MHz

SW2 CONFIG 2.0 MHz

SW3A CONFIG SW3AB Single Phase, 2.0 MHz

SW3B CONFIG 2.0 MHz

SW4 CONFIG No VTT, 2.0 MHz

PG EN RESETBMCU in default mode

Notes
25. For designs using the i.MX 6SoloLite, it is recommended to use the F3 OTP option instead of the F1 OTP option
and F4 OTP option instead of the F2 OTP option.

PF0100

NXP Semiconductors 19
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

LICELL
UVDET
VIN td1 tr1

1V
VSNVS td2 tr2

PWRON td3 tr3

SW1A/B

SW1C td4 tr3

SW2

VGEN2 td4 tr3

SW3A/B

SW4

VREFDDR

VGEN4

VGEN5

td5 tr4
VGEN6

RESETBMCU

*VSNVS starts from 1.0 V if LICELL is valid before VIN.

Figure 6. Default start-up sequence

Table 11. Default start-up sequence timing

Parameter Description Min. Typ. Max. Unit Notes

(26)
tD1 Turn-on delay of VSNVS – 5.0 – ms

tR1 Rise time of VSNVS – 3.0 – ms

tD2 User determined delay – 1.0 – ms

(27)
tR2 Rise time of PWRON – – ms

Turn-on delay of first regulator

• SEQ_CLK_SPEED[1:0] = 00 – 2.0 –

tD3 • SEQ_CLK_SPEED[1:0] = 01 – 2.5 – (28)

ms
• SEQ_CLK_SPEED[1:0] = 10 – 4.0 –

• SEQ_CLK_SPEED[1:0] = 11 – 7.0 –

tR3 (29)
Rise time of regulators – 0.2 – ms

PF0100

20 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 11. Default start-up sequence timing (continued)

Parameter Description Min. Typ. Max. Unit Notes

Delay between regulators

• SEQ_CLK_SPEED[1:0] = 00 – 0.5 –

tD4 • SEQ_CLK_SPEED[1:0] = 01 – 1.0 –

ms
• SEQ_CLK_SPEED[1:0] = 10 – 2.0 –

• SEQ_CLK_SPEED[1:0] = 11 – 4.0 –

tR4 Rise time of RESETBMCU – 0.2 – ms

tD5 Turn-on delay of RESETBMCU – 2.0 – ms

Notes
26. Assumes LICELL voltage is valid before VIN is applied. If LICELL is not valid before VIN is applied then VSNVS turn-on delay may extend to a
maximum of 24 ms.
27. Depends on the external signal driving PWRON.
28. Default configuration.
29. Rise time is a function of slew rate of regulators and nominal voltage selected.

6.1.2 One time programmability (OTP)

OTP allows the programming of start-up configurations for a variety of applications. Before permanently programming the IC by
programming fuses, a configuration may be prototyped by using the “Try Before Buy” (TBB) feature. Further, an error correction
code(ECC) algorithm is available to correct a single bit error and to detect multiple bit errors when fuses are programmed.
The parameters which can be configured by OTP are listed below.
• General: I2C slave address, PWRON pin configuration, start-up sequence and timing
• Buck regulators: Output voltage, dual/single phase or independent mode configuration, switching frequency, and soft start ramp
rate
• Boost regulator and LDOs: Output voltage
NOTE: When prototyping or programming fuses, the user must ensure register settings are consistent with the hardware configuration.
This is most important for the buck regulators, where the quantity, size, and value of the inductors depend on the configuration (single/
dual phase or independent mode) and the switching frequency. Additionally, if an LDO is powered by a buck regulator, it is gated by the
buck regulator in the start-up sequence.

6.1.2.1 Start-up sequence and timing

Each regulator has 5-bit allocated to program its start-up time slot from a turn on event; therefore, each can be placed from position one
to thirty-one in the start-up sequence. The all zeros code indicates a regulator is not part of the start-up sequence and remains off. See
Table 12. The delay between each position is equal; however, four delay options are available. See Table 13. The start-up sequence
terminates at the last programmed regulator.

PF0100

NXP Semiconductors 21
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 12. Start-up sequence

SWxx_SEQ[4:0]/
VGENx_SEQ[4:0]/ Sequence
VREFDDR_SEQ[4:0]

00000 Off

00001 SEQ_CLK_SPEED[1:0] * 1

00010 SEQ_CLK_SPEED[1:0] * 2

* *

* *

* *

* *
11111 SEQ_CLK_SPEED[1:0] * 31

Table 13. Start-up sequence clock speed

SEQ_CLK_SPEED[1:0] Time (μs)

00 500

01 1000

10 2000

11 4000

6.1.2.2 PWRON pin configuration

The PWRON pin can be configured as either a level sensitive input (PWRON_CFG = 0), or as an edge sensitive input
(PWRON_CFG = 1). As a level sensitive input, an active high signal turns on the part and an active low signal turns off the part, or puts it
into sleep mode. As an edge sensitive input, such as when connected to a mechanical switch, a falling edge turns on the part and if the
switch is held low for greater than or equal to 4.0 seconds, the part turns off or enters sleep mode.

Table 14. PWRON configuration

PWRON_CFG Mode

PWRON pin HIGH = ON

0
PWRON pin LOW = OFF or Sleep mode

PWRON pin pulled LOW momentarily = ON

1
PWRON pin LOW for 4.0 seconds = OFF or Sleep mode

6.1.2.3 I2C address configuration

The I2C device address can be programmed from 0x08 to 0x0F. This allows flexibility to change the I2C address to avoid bus conflicts.
Address bit, I2C_SLV_ADDR[3] in OTP_I2C_ADDR register is hard coded to “1” while the lower three LSBs of the I2C address
(I2C_SLV_ADDR[2:0]) are programmable as shown in Table 15.

Table 15. I2C address configuration

I2C_SLV_ADDR[3] I2C device address

I2C_SLV_ADDR[2:0]
hard coded (Hex)

1 000 0x08

1 001 0x09

1 010 0x0A

1 011 0x0B

PF0100

22 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 15. I2C address configuration (continued)

I2C_SLV_ADDR[3] I2C device address

I2C_SLV_ADDR[2:0]
hard coded (Hex)

1 100 0x0C

1 101 0x0D

1 110 0x0E

1 111 0x0F

6.1.2.4 Soft start ramp rate

The start-up ramp rate or soft start ramp rate can be chosen from the same options as shown in 6.4.4.2.1 Dynamic voltage scaling, page
35.

6.1.3 OTP prototyping

Before permanently programming fuses, it is possible to test the desired configuration by using the “Try Before Buy” feature. With this
feature, the configuration is loaded from the OTP registers. These registers merely serve as temporary storage for the values to be written
to the fuses, for the values read from the fuses, or for the values read from the default configuration. To avoid confusion, these registers
are referred to as the TBBOTP registers. The portion of the register map concerned with OTP is shown in Table 137 and Table 138.
The contents of the TBBOTP registers are initialized to zero when a valid VIN is first applied. The values loaded into the TBBOTP registers
depend on the setting of the VDDOTP pin and on the value of the TBB_POR and FUSE_POR_XOR bits. Refer to Table 16.
• If VDDOTP = VCOREDIG (1.5 V), the values are loaded from the default configuration.
• If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR_XOR = 1, the values are loaded from the fuses. In the MMPF0100,
FUSE_POR1, FUSE_POR2, and FUSE_POR3 are XOR’ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR has to be 1 for
fuses to be loaded. This can be achieved by setting any one or all of the FUSE_PORx bits. In the MMPF0100A, the XOR function
is removed. It is required to set all of the FUSE_PORx bits to be able to load the fuses.
• If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR_XOR = 0, the TBBOTP registers remain initialized at zero.
The initial value of TBB_POR is always “0”; only when VDDOTP = 0.0 V and TBB_POR is set to “1” are the values from the TBBOTP
registers maintained and not loaded from a different source.
The contents of the TBBOTP registers are modified by I2C. To communicate with I2C, VIN must be valid and VDDIO, to which SDA and
SCL are pulled up, must be powered by a 1.7 V to 3.6 V supply. VIN, or the coin cell voltage must be valid to maintain the contents of the
registers. To power on with the contents of the TBBOTP registers, the following conditions must exist; VIN is valid, VDDOTP = 0.0 V,
TBB_POR = 1 and there is a valid turn-on event. Refer to the application note AN4536 for an example of prototyping.

6.1.4 Reading OTP fuses

As described in the previous section, the contents of the fuses are loaded to the TBBOTP registers when the following conditions are met;
VIN is valid, VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR_XOR = 1. If ECC were enabled at the time the fuses were programmed,
the error corrected values can be loaded into the TBBOTP registers if desired. Once the fuses are loaded and a turn-on event occurs, the
PMIC powers on with the configuration programmed in the fuses. For more details on reading the OTP fuses, see application note
AN4536.

6.1.5 Programming OTP fuses

The parameters which can be programmed are shown in the TBBOTP registers in Table 137. Extended page 1, page 111 of the register
map. The PF0100 offers ECC, the control registers for which functions are located in Extended Page 2 of the register map. There are ten
banks of twenty-six fuses each which can be programmed. Programming the fuses requires an 8.25 V, 100 mA supply powering the
VDDOTP pin, bypassed with 10 to 20 μF of capacitance. For more details on programming the OTP fuses, see application note AN4536.

PF0100

NXP Semiconductors 23
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 16. Source of start-up sequence

VDDOTP(V) TBB_POR FUSE_POR_XOR Start-up sequence

0 0 0 None

0 0 1 OTP fuses
0 1 x TBBOTP registers

1.5 x x Factory defined

6.2 16 MHz and 32 kHz clocks

There are two clocks: a trimmed 16 MHz, RC oscillator and an untrimmed 32 kHz, RC oscillator. The 16 MHz oscillator is specified within
-8.0/+8.0%. The 32 kHz untrimmed clock is only used in the following conditions:
• VIN < UVDET
• All regulators are in sleep mode
• All regulators are in PFM switching mode
A 32 kHz clock, derived from the 16 MHz trimmed clock, is used when accurate timing is needed under the following conditions:
• During start-up, VIN > UVDET
• PWRON_CFG = 1, for power button debounce timing
In addition, when the 16 MHz is active in the ON mode, the debounce times in Table 27 are referenced to the 32 kHz derived from the
16 MHz clock. The exceptions are the LOWVINI and PWRONI interrupts, which are referenced to the 32 kHz untrimmed clock.

Table 17. 16 MHz clock specifications

TMIN to TMAX (See Table 3), VIN = 2.8 V to 4.5 V, LICELL = 1.8 V to 3.3 V and typical external component values. Typical values are
characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.

Symbol Parameters Min. Typ. Max. Units Notes

VIN16MHz Operating voltage from VIN 2.8 – 4.5 V

f16MHZ 16 MHz clock frequency 14.7 16 17.2 MHz

(30)
f2MHZ 2.0 MHz clock frequency 1.84 – 2.15 MHz

Notes
30. 2.0 MHz clock is derived from the 16 MHz clock.

6.2.1 Clock adjustment

The 16 MHz clock and hence the switching frequency of the regulators, can be adjusted to improve the noise integrity of the system. By
changing the factory trim values of the 16 MHz clock, the user may add an offset as small as ±3.0% of the nominal frequency. Contact
your NXP representative for detailed information on this feature.

6.3 Bias and references block description

6.3.1 Internal core voltage references

All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at VCOREREF. The bandgap and
the rest of the core circuitry are supplied from VCORE. The performance of the regulators is directly dependent on the performance of the
bandgap. No external DC loading is allowed on VCORE, VCOREDIG, or VCOREREF. VCOREDIG is kept powered as long as there is a
valid supply and/or valid coin cell. Table 18 shows the main characteristics of the core circuitry.

PF0100

24 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 18. Core voltages electrical specifications(32)

TMIN to TMAX (See Table 3), VIN = 2.8 V to 4.5 V, LICELL = 1.8 V to 3.3 V, and typical external component values. Typical values are
characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.

Symbol Parameters Min. Typ. Max. Units Notes

VCOREDIG (digital core supply)

Output voltage
(31)
VCOREDIG • ON mode – 1.5 – V
• Coin cell mode and OFF – 1.3 – —
VCORE (analog core supply)

Output voltage
VCORE (31)
• ON mode and charging – 2.775 – V
• OFF and coin cell mode – 0.0 – —
VCOREREF (bandgap / regulator reference)
(31)
VCOREREF Output voltage – 1.2 – V

VCOREREFACC Absolute accuracy – 0.5 – %

VCOREREFTACC Temperature drift – 0.25 – %

Notes
31. 3.0 V < VIN < 4.5 V, no external loading on VCOREDIG, VCORE, or VCOREREF. Extended operation down to UVDET, but no system malfunction.
32. For information only.

6.3.1.1 External components

Table 19. External components for core voltages

Regulator Capacitor value (μF)

VCOREDIG 1.0

VCORE 1.0
VCOREREF 0.22

6.3.2 VREFDDR voltage reference

VREFDDR is an internal PMOS half supply voltage follower capable of supplying up to 10 mA. The output voltage is at one half the input
voltage. Its typically used as the reference voltage for DDR memories. A filtered resistor divider is utilized to create a low frequency pole.
This divider then utilizes a voltage follower to drive the load.

VINREFDDR
VINREFDDR

CHALF1
100 nf
VHALF _

CHALF2 +
100 nf
Discharge

VREFDDR
VREFDDR
CREFDDR
1.0 uf

Figure 7. VREFDDR block diagram

PF0100

NXP Semiconductors 25
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.3.2.1 VREFDDR control register

The VREFDDR voltage reference is controlled by a single bit in VREFDDCRTL register in Table 20.

Table 20. Register VREFDDCRTL - ADDR 0x6A

Name Bit # R/W Default Description

UNUSED 3:0 – 0x00 UNUSED

Enable or disables VREFDDR output voltage

VREFDDREN 4 R/W 0x00 • 0 = VREFDDR Disabled
• 1 = VREFDDR Enabled

UNUSED 7:5 – 0x00 UNUSED

6.3.2.1.1 External components

Table 21. VREFDDR external components(33)

Capacitor Capacitance (μF)

VINREFDDR(34) to VHALF 0.1

VHALF to GND 0.1

VREFDDR 1.0

Notes
33. Use X5R or X7R capacitors.
34. VINREFDDR to GND, 1.0 μF minimum capacitance is provided by buck regulator output.

6.3.2.1.2 VREFDDR specifications

Table 22. VREFDDR electrical characteristics

TMIN to TMAX (See Table 3), VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V and typical external component values, unless otherwise
noted. Typical values are characterized at VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V, and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

VREFDDR

VINREFDDR Operating input voltage range 1.2 – 1.8 V

IREFDDR Operating load current range 0.0 – 10 mA

Current limit
IREFDDRLIM 10.5 15 25 mA
• IREFDDR when VREFDDR is forced to VINREFDDR/4
(35)
IREFDDRQ Quiescent Current – 8.0 – μA
Active mode – DC

Output voltage
VREFDDR • 1.2 V < VINREFDDR < 1.8 V – VINREFDDR/2 – V
• 0.0 mA < IREFDDR < 10 mA

Output voltage tolerance (TA = -40 °C to 85 °C)

VREFDDRTOL • 1.2 V < VINREFDDR < 1.8 V –1.0 – 1.0 %
• 0.6 mA ≤ IREFDDR ≤ 10 mA
Output voltage tolerance (TA = -40 °C to 105 °C), applicable only
to the extended industrial version
VREFDDRTOL –1.2 – 1.2 %
• 1.2 V < VINREFDDR < 1.8 V
• 0.6 mA ≤ IREFDDR ≤ 10 mA

Load regulation
VREFDDRLOR • 1.0 mA < IREFDDR < 10 mA – 0.40 – mV/mA
• 1.2 V < VINREFDDR < 1.8 V

PF0100

26 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 22. VREFDDR electrical characteristics (continued)

TMIN to TMAX (See Table 3), VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V and typical external component values, unless otherwise
noted. Typical values are characterized at VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V, and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

Active mode – AC

Turn-on time
• Enable to 90% of end value
tONREFDDR – – 100 μs
• VINREFDDR = 1.2 V, 1.8 V
• IREFDDR = 0.0 mA
Turn-off time
• Disable to 10% of initial value
tOFFREFDDR – – 10 ms
• VINREFDDR = 1.2 V, 1.8 V
• IREFDDR = 0.0 mA

Start-up overshoot
VREFDDROSH • VINREFDDR = 1.2 V, 1.8 V – 1.0 6.0 %
• IREFDDR = 0.0 mA

Transient load response

VREFDDRTLR – 5.0 – mV
• VINREFDDR = 1.2 V, 1.8 V
Notes
35. When VREFDDR is off there is a quiescent current of 1.5 μA typical.

PF0100

NXP Semiconductors 27
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.4 Power generation

6.4.1 Modes of operation

The operation of the PF0100 can be reduced to five states, or modes: on, off, sleep, standby, and coin cell. Figure 8 shows the state
diagram of the PF0100, along with the conditions to enter and exit from each state.

Coin Cell
VIN < UVDET VIN < UVDET

VIN > UVDET

PWRON = 0 held >= 4.0 sec
Any SWxOMODE bits=1
Thermal shutdown
& PWRONRSTEN = 1
(PWRON_CFG=1)

PWRON=1 OFF
& VIN > UVDET
VIN < UVDET
Sleep (PWRON_CFG = 0)
Or
PWRON = 0 PWRON= 0 < 4.0 sec
Any SWxOMODE bits=1 & VIN > UVDET
(PWRON_CFG=0) (PWRON_CFG=1)
Or
PWRON=0 held >= 4.0 sec PWRON = 0
Any SWxOMODE bits=1 All SWxOMODE bits= 0
VIN < UVDET (PWRON_CFG = 0)
& PWRONRSTEN = 1
PWRON = 0 (PWRON_CFG=1) Or
Any SWxOMODE bits=1 PWRON = 0 held >= 4.0 sec
(PWRON_CFG=0) PWRON=1 All SWxOMODE bits= 0
Or & VIN > UVDET & PWRONRSTEN = 1
PWRON=0 held >= 4.0 sec (PWRON_CFG =0) (PWRON_CFG = 1)
Any SWxOMODE bits=1 Or
ON
& PWRONRSTEN = 1 PWRON= 0 < 4.0 sec
(PWRON_CFG=1) & VIN > UVDET Thermal shudown
(PWRON_CFG=1)

PWRON = 0
All SWxOMODE bits= 0
(PWRON_CFG = 0)
STANDBY asserted STANDBY de-asserted
Or
PWRON = 0 held >= 4.0 sec
All SWxOMODE bits= 0
& PWRONRSTEN = 1
(PWRON_CFG = 1)

Thermal shutdown
Standby

Figure 8. State diagram

To complement the state diagram in Figure 8, a description of the states is provided in following sections. Note that VIN must exceed the
rising UVDET threshold to allow a power up. Refer to Table 29 for the UVDET thresholds. Additionally, I2C control is not possible in the
coin cell mode and the interrupt signal, INTB, is only active in sleep, standby, and on states.

6.4.1.1 ON mode
The PF0100 enters the On mode after a turn-on event. RESETBMCU is de-asserted, high, in this mode of operation.

6.4.1.2 OFF mode

The PF0100 enters the off mode after a turn-off event. A thermal shutdown event also forces the PF0100 into the off mode. Only
VCOREDIG and VSNVS are powered in the mode of operation. To exit the off mode, a valid turn-on event is required. RESETBMCU is
asserted, low, in this mode.

PF0100

28 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.4.1.3 Standby mode

• Depending on STANDBY pin configuration, standby is entered when the STANDBY pin is asserted. This is typically used for low-
power mode of operation.
• When STANDBY is de-asserted, standby mode is exited.
A product may be designed to go into a low-power mode after periods of inactivity. The STANDBY pin is provided for board level control
of going in and out of such deep sleep modes (DSM).
When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing the
operating mode of the regulators or disabling some regulators. The configuration of the regulators in standby is pre-programmed through
the I2C interface.
Note that the STANDBY pin is programmable for active high or active low polarity, and decoding of a standby event takes into account
the programmed input polarity as shown in Table 23. When the PF0100 is powered up first, regulator settings for the standby mode are
mirrored from the regulator settings for the on mode. To change the STANDBY pin polarity to Active Low, set the STANDBYINV bit via
software first, and then change the regulator settings for Standby mode as required. For simplicity, STANDBY generally is referred to as
active high throughout this document.

Table 23. Standby pin and polarity control

STANDBY (pin)(37) STANDBYINV (I2C bit)(38) STANDBY control (36)

0 0 0

0 1 1
1 0 1

1 1 0

Notes
36. STANDBY = 0: System is not in standby, STANDBY = 1: System is in standby
37. The state of the STANDBY pin only has influence in on mode.
38. Bit 6 in power control register (ADDR - 0x1B)

Since STANDBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond
to the pin level changes. A programmable delay is provided to hold off the system response to a standby event. This allows the processor
and peripherals some time after a standby instruction has been received to terminate processes to facilitate seamless entering into
standby mode.
When enabled (STBYDLY = 01, 10, or 11) per Table 24, STBYDLY delays the standby initiated response for the entire IC, until the
STBYDLY counter expires.
An allowance should be made for three additional 32 k cycles required to synchronize the standby event.

Table 24. STANDBY delay - initiated response

STBYDLY[1:0](39) Function

00 No delay

01 One 32 k period (default)

10 Two 32 k periods

11 Three 32 k periods

Notes
39. Bits [5:4] in power control register (ADDR - 0x1B)

6.4.1.4 Sleep mode

• Depending on PWRON pin configuration, sleep mode is entered when PWRON is de-asserted and SWxOMODE bit is set.
• To exit sleep mode, assert the PWRON pin.
In the sleep mode, the regulator uses the set point as programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/
B, and SW4. The activated regulators maintains settings for this mode and voltage until the next turn-on event. Table 25 shows the control
bits in sleep mode. During sleep mode, interrupts are active and the INTB pin reports any unmasked fault event.

PF0100

NXP Semiconductors 29
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 25. Regulator mode control

SWxOMODE Off operational mode (Sleep) (40)

0 Off

1 PFM

Notes
40. For sleep mode, an activated switching regulator, should use the off
mode set point as programmed by SW1xOFF[5:0] for SW1A/B/C and
SWxOFF[6:0] for SW2, SW3A/B, and SW4.

6.4.1.5 Coin cell mode

In the coin cell state, the coin cell is the only valid power source (VIN = 0.0 V) to the PMIC. No turn-on event is accepted in the coin cell
state. Transition to the off state requires VIN surpasses UVDET threshold. RESETBMCU is held low in this mode.
If the coin cell is depleted, a complete system reset occurs. At the next application of power and the detection of a turn-on event, the system
is re-initialized with all I2C bits including those reset on COINPORB, which are restored to their default states.

6.4.2 State machine flow summary

Table 26 provides a summary matrix of the PF0100 flow diagram to show the conditions needed to transition from one state to another.

Table 26. State machine flow summary

Next state
STATE
OFF Coin cell Sleep Standby ON

PWRON_CFG = 0
PWRON = 1 & VIN > UVDET
OFF or
X VIN < UVDET X X
PWRON_CFG = 1
PWRON = 0 < 4.0 s
& VIN > UNDET
Coin cell VIN > UVDET X X X X

Thermal shutdown PWRON_CFG = 0

PWRON = 1 & VIN > UVDET
PWRON_CFG = 1 or
Sleep VIN < UVDET X X
PWRON = 0 ≥ 4.0 s PWRON_CFG = 1
Any SWxOMODE = 1 & PWRON = 0 < 4.0 s &
PWRONRSTEN = 1 VIN > UNDET

Thermal shutdown
Initial state

PWRON_CFG = 0
PWRON_CFG = 0 PWRON = 0
PWRON = 0 Any SWxOMODE = 1
All SWxOMODE = 0 or
Standby VIN < UVDET X Standby de-asserted
or PWRON_CFG = 1
PWRON_CFG = 1 PWRON = 0 ≥ 4.0 s
PWRON = 0 ≥ 4.0 s Any SWxOMODE = 1 &
All SWxOMODE = 0 & PWRONRSTEN = 1
PWRONRSTEN = 1

Thermal shutdown
PWRON_CFG = 0
PWRON_CFG = 0 PWRON = 0
PWRON = 0 Any SWxOMODE = 1
All SWxOMODE = 0 or
ON VIN < UVDET Standby asserted X
or PWRON_CFG = 1
PWRON_CFG = 1 PWRON = 0 ≥ 4.0 s
PWRON = 0 ≥ 4.0 s Any SWxOMODE = 1 &
All SWxOMODE = 0 & PWRONRSTEN = 1
PWRONRSTEN = 1

PF0100

30 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.4.2.1 Turn on events

From off and sleep modes, the PMIC is powered on by a turn-on event. The type of turn-on event depends on the configuration of PWRON.
PWRON may be configured as an active high when PWRON_CFG = 0, or as the input of a mechanical switch when PWRON_CFG = 1.
VIN must be greater than UVDET for the PMIC to turn-on. When PWRON is configured as an active high and PWRON is high (pulled up
to VSNVS) before VIN is valid, a VIN transition from 0.0 V to a voltage greater than UVDET is also a Turn-on event. See the state diagram,
Figure 8, and the Table 26 for more details. Any regulator enabled in the sleep mode remains enabled when transitioning from sleep to
on, i.e., the regulator does not turn off and then on again to match the start-up sequence. The following is a more detailed description of
the PWRON configurations:
• If PWRON_CFG = 0, the PWRON signal is high and VIN > UVDET, the PMIC turns on; the interrupt and sense bits, PWRONI and
PWRONS respectively, is set.
• If PWRON_CFG = 1, VIN > UVDET and PWRON transitions from high to low, the PMIC turns on; the interrupt and sense bits,
PWRONI and PWRONS respectively, sets.
The sense bit shows the real time status of the PWRON pin. In this configuration, the PWRON input can be a mechanical switch
debounced through a programmable debouncer, PWRONDBNC[1:0], to avoid a response to a very short (i.e., unintentional) key press.
The interrupt is generated for both the falling and the rising edge of the PWRON pin. By default, a 30 ms interrupt debounce is applied to
both falling and rising edges. The falling edge debounce timing can be extended with PWRONDBNC[1:0] as defined in Table 27. The
interrupt is cleared by software, or when cycling through the OFF mode.

Table 27. PWRON hardware debounce bit settings

Turn on Falling edge INT Rising edge INT

Bits State
debounce (ms) debounce (ms) debounce (ms)

00 0.0 31.25 31.25

01 31.25 31.25 31.25
PWRONDBNC[1:0]
10 125 125 31.25
11 750 750 31.25
Notes
41. The sense bit, PWRONS, is not debounced and follows the state of the PWRON pin.

6.4.2.2 Turn off events

6.4.2.2.1 PWRON pin

The PWRON pin is used to power off the PF0100. The PWRON pin can be configured with OTP to power off the PMIC under the following
two conditions:
1. PWRON_CFG bit = 0, SWxOMODE bit = 0 and PWRON pin is low.

2. PWRON_CFG bit = 1, SWxOMODE bit = 0, PWRONRSTEN = 1 and PWRON is held low for longer than 4.0 seconds.
Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.

6.4.2.2.2 Thermal protection

If the die temperature surpasses a given threshold, the thermal protection circuit powers off the PMIC to avoid damage. A turn-on event
does not power on the PMIC while it is in thermal protection. The part remains in off mode until the die temperature decreases below a
given threshold. There are no specific interrupts related to this other than the warning interrupt. See 4.2.1 Power dissipation, page 11
section for more detailed information.

6.4.2.2.3 Undervoltage detection

When the voltage at VIN drops below the undervoltage falling threshold, UVDET, the state machine transitions to the coin cell mode.

PF0100

NXP Semiconductors 31
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.4.3 Power tree

The PF0100 PMIC features six buck regulators, one boost regulator, six general purpose LDOs, one switch/LDO combination, and a DDR
voltage reference to supply voltages for the application processor and peripheral devices. The buck regulators as well as the boost
regulator are supplied directly from the main input supply (VIN). The inputs to all of the buck regulators must be tied to VIN, whether they
are powered on or off. The six general use LDO regulators are directly supplied from the main input supply or from the switching regulators
depending on the application requirements. Since VREFDDR is intended to provide DDR memory reference voltage, it should be supplied
by any rail supplying voltage to DDR memories; the typical application recommends the use of SW3 as the input supply for VREFDDR.
VSNVS is supplied by either the main input supply or the coin cell. Refer to Table 28 for a summary of all power supplies provided by the
PF0100.

Table 28. Power tree summary

Supply Output voltage (V) Step size (mV) Maximum load current (mA)

SW1A/B 0.3 - 1.875 25 2500

SW1C 0.3 - 1.875 25 2000

SW2 0.4 - 3.3 25/50 2000 (43)

SW3A/B 0.4 - 3.3 25/50 1250 (42)

SW4 0.5*SW3A_OUT, 0.4 - 3.3 25/50 1000

SWBST 5.00/5.05/5.10/5.15 50 600

VGEN1 0.80 – 1.55 50 100

VGEN2 0.80 – 1.55 50 250

VGEN3 1.8 – 3.3 100 100

VGEN4 1.8 – 3.3 100 350

VGEN5 1.8 – 3.3 100 100

VGEN6 1.8 – 3.3 100 200

VSNVS 1.0 - 3.0 NA 0.4

VREFDDR 0.5*SW3A_OUT NA 10

Notes
42. Current rating per independent phase, when SW3A/B is set in single or dual phase, current capability is up
to 2500 mA.
43. SW2 capable of 2500 mA in NP, F9, and FA Industrial versions only (ANES suffix)

Figure 9 shows a simplified power map with various recommended options to supply the different block within the PF0100, as well as the
typical application voltage domain on the i.MX 6X processor. Note that each application power tree is dependent upon the system’s voltage
and current requirements, therefore a proper input voltage should be selected for the regulators.
The minimum operating voltage for the main VIN supply is 2.8 V, for lower voltages proper operation is not guaranteed. However at initial
power up, the input voltage must surpass the rising UVDET threshold before proper operation is guaranteed. Refer to the representative
tables and text specifying each supply for information on performance metrics and operating ranges. Table 29 summarizes the UVDET
thresholds.

Table 29. UVDET threshold

UVDET threshold VIN

Rising 3.1 V
Falling 2.65 V

PF0100

32 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

i.MX6X
MCU
SW1A
VDDARM_IN
CORE
(0.3 to 1.875 V), 1.25 A

SW1B
CORE
(0.3 to 1.875 V), 1.25 A

SW1C VDDSOC_IN
SOC
(0.3 to 1.875 V), 2.0 A

SW2 VDDHIGH_IN
VIN VDDHIGH
2.8 - 4.5 V (0.4 to 3.3 V), 2.0 A

SW3A
DDR CORE
(0.4 to 3.3 V), 1.25 A

SW3B VDD_DDR_IO
DDR IO
(0.4 to 3.3 V), 1.25 A

SW4
System/VTT
(0.4 to 3.3 V)
(0.5*VDDR)
1.0 A

SWBST
5.0 V, 0.6 A LDO_3p0

VREFDDR
SW3A/B 0.5*VDDR, 10 mA

VIN VSNVS
MUX /
COIN 1.0 to 3.0 V, VSNVS_IN
Coincell CHRG 400 uA

VGEN1 USB_OTG
(0.80 to 1.55 V),
VIN 100 mA
SW2 VINMAX = 3.4 V
VGEN2
SW4 DDR3
(0.80 to 1.55 V),
250 mA

VGEN3
(1.8 to 3.3 V),
Peripherals
VIN 100 mA
SW2 VINMAX = 3.6 V
VGEN4
SW4 (1.8 to 3.3 V),
350 mA

VGEN5
(1.8 to 3.3 V),
VIN 100 mA
SW2 VINMAX = 4.5 V
VGEN6
SW4 (1.8 to 3.3 V),
200 mA

Figure 9. PF0100 typical power map

PF0100

NXP Semiconductors 33
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.4.4 Buck regulators

Each buck regulator is capable of operating in PFM, APS, and PWM switching modes.

6.4.4.1 Current limit

Each buck regulator has a programmable current limit. In an overcurrent condition, the current is limited cycle-by-cycle. If the current limit
condition persists for more than 8.0 ms, a fault interrupt is generated.

6.4.4.2 General control

To improve system efficiency the buck regulators can operate in different switching modes. Changing between switching modes can occur
by any of the following means: I2C programming, exiting/entering the Standby mode, exiting/entering Sleep mode, and load current
variation. Available switching modes for buck regulators are presented in Table 30.

Table 30. Switching mode description

Mode Description

OFF The regulator is switched off and the output voltage is discharged.

PFM In this mode, the regulator is always in PFM mode, which is useful at light loads for optimized efficiency.
PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions.

In this mode, the regulator moves automatically between pulse skipping mode and PWM mode
APS
depending on load conditions.

During soft-start of the buck regulators, the controller transitions through the PFM, APS, and PWM switching modes. 3.0 ms (typical) after
the output voltage reaches regulation, the controller transitions to the selected switching mode. Depending on the particular switching
mode selected, additional ripple may be observed on the output voltage rail as the controller transitions between switching modes.
Table 31 summarizes the buck regulator programmability for normal and standby modes.

Table 31. Regulator mode control

SWxMODE[3:0] Normal mode Standby mode

0000 Off Off

0001 PWM Off

0010 Reserved Reserved

0011 PFM Off

0100 APS Off

0101 PWM PWM

0110 PWM APS

0111 Reserved Reserved

1000 APS APS

1001 Reserved Reserved

1010 Reserved Reserved

1011 Reserved Reserved

1100 APS PFM

1101 PWM PFM

1110 Reserved Reserved

1111 Reserved Reserved

PF0100

34 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Transitioning between normal and standby modes can affect a change in switching modes as well as output voltage. The rate of the output
voltage change is controlled by the dynamic voltage scaling (DVS), explained in 6.4.4.2.1 Dynamic voltage scaling, page 35. For each
regulator, the output voltage options are the same for normal and standby modes.
When in standby mode, the regulator outputs the voltage programmed in its standby voltage register and operates in the mode selected
by the SWxMODE[3:0] bits. Upon exiting Standby mode, the regulator returns to its normal switching mode and its output voltage
programmed in its voltage register.
Any regulators whose SWxOMODE bit is set to “1” enters Sleep mode if a PWRON turn-off event occurs, and any regulator whose
SWxOMODE bit is set to “0” turns off. In sleep mode, the regulator outputs the voltage programmed in its off (sleep) voltage register and
operates in the PFM mode. The regulator exits the sleep mode when a turn-on event occurs. Any regulator whose SWxOMODE bit is set
to “1” remains on and change to its normal configuration settings when exiting the sleep state to the on state. Any regulator whose
SWxOMODE bit is set to “0” is powered up with the same delay in the start-up sequence as when powering on from off. At this point, the
regulator returns to its default on state output voltage and switch mode settings.
Table 25 shows the control bits in sleep mode. When sleep mode is activated by the SWxOMODE bit, the regulator uses the set point as
programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/B, and SW4.

6.4.4.2.1 Dynamic voltage scaling

To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor.
1. Normal operation: The output voltage is selected by I2C bits SW1x[5:0] for SW1A/B/C and SWx[6:0] for SW2, SW3A/B, and SW4.
A voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 34 and Table 35.
2. Standby mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the lowest state
retention voltage of a given processor; it is selected by I2C bits SW1xSTBY[5:0] for SW1A/B/C and by bits SWxSTBY[6:0] for SW2,
SW3A/B, and SW4. Voltage transitions initiated by a Standby event are governed by the SW1xDVSSPEED[1:0] and
SWxDVSSPEED[1:0] I2C bits shown in Table 34 and Table 35, respectively.
3. Sleep mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest state
retention voltage of a given processor; it is selected by I2C bits SW1xOFF[5:0] for SW1A/B/C and by bits SWxOFF[6:0] for SW2,
SW3A/B, and SW4. Voltage transitions initiated by a turn-off event are governed by the SW1xDVSSPEED[1:0] and
SWxDVSSPEED[1:0] I2C bits shown in Table 34 and Table 35, respectively.
Table 32, Table 33, Table 34, and Table 35 summarize the set point control and DVS time stepping applied to all regulators.

Table 32. DVS control logic for SW1A/B/C

STANDBY Set point selected by

0 SW1x[5:0]

1 SW1xSTBY[5:0]

Table 33. DVS control logic for SW2, SW3A/B, and SW4

STANDBY Set Point Selected by

0 SWx[6:0]

1 SWxSTBY[6:0]

Table 34. DVS speed selection for SW1A/B/C

SW1xDVSSPEED[1:0] Function

00 25 mV step each 2.0 μs

01 (default) 25 mV step each 4.0 μs

10 25 mV step each 8.0 μs

11 25 mV step each 16 μs

PF0100

NXP Semiconductors 35
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 35. DVS speed selection for SW2, SW3A/B, and SW4

Function Function
SWxDVSSPEED[1:0]
SWx[6] = 0 or SWxSTBY[6] = 0 SWx[6] = 1 or SWxSTBY[6] = 1

00 25 mV step each 2.0 μs 50 mV step each 4.0 μs

01 (default) 25 mV step each 4.0 μs 50 mV step each 8.0 μs
10 25 mV step each 8.0 μs 50 mV step each 16 μs
11 25 mV step each 16 μs 50 mV step each 32 μs
The regulators have a strong sourcing capability and sinking capability in PWM mode, therefore the fastest rising and falling slopes are
determined by the regulator in PWM mode. However, if the regulators are programmed in PFM or APS mode during a DVS transition, the
falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS transitions in
PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation.
The following diagram shows the general behavior for the regulators when initiated with I2C programming, or standby control. During the
DVS period the overcurrent condition on the regulator should be masked.

Requested
Set Point
Output Voltage
with light Load
Internally
Controlled Steps
Output Example
Actual Output
Voltage Voltage
Initial
Set Point Actual
Output Voltage Internally
Controlled Steps Possible
Output Voltage
Window
Request for Request for
Voltage Higher Voltage Lower Voltage
Change
Request
Initiated by I2C Programming, Standby Control

Figure 10. Voltage stepping with DVS

6.4.4.2.2 Regulator phase clock

The SWxPHASE[1:0] bits select the phase of the regulator clock as shown in Table 36. By default, each regulator is initialized at 90 ° out
of phase with respect to each other. For example, SW1x is set to 0 °, SW2 is set to 90 °, SW3A/B is set to 180 °, and SW4 is set to 270 °
by default at power up.

Table 36. Regulator phase clock selection

SWxPHASE[1:0] Phase of clock sent to regulator (degrees)

00 0

01 90

10 180

11 270

The SWxFREQ[1:0] register is used to set the desired switching frequency for each one of the buck regulators. Table 38 shows the
selectable options for SWxFREQ[1:0]. For each frequency, all phases are available, allowing regulators operating at different frequencies
to have different relative switching phases. However, not all combinations are practical. For example, 2.0 MHz, 90 ° and 4.0 MHz, 180 °
are the same in terms of phasing. Table 37 shows the optimum phasing when using more than one switching frequency.

PF0100

36 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 37. Optimum phasing

Frequencies Optimum Phasing

1.0 MHz 0°
2.0 MHz 180 °

1.0 MHz 0°
4.0 MHz 180 °

2.0 MHz 0°
4.0 MHz 180 °

1.0 MHz 0°
2.0 MHz 90 °
4.0 MHz 90 °

Table 38. Regulator frequency configuration

SWxFREQ[1:0] Frequency

00 1.0 MHz

01 2.0 MHz

10 4.0 MHz

11 Reserved

6.4.4.2.3 Programmable maximum current

The maximum current, ISWxMAX, of each buck regulator is programmable. This allows the use of smaller inductors where lower currents
are required. Programmability is accomplished by choosing the number of paralleled power stages in each regulator. The
SWx_PWRSTG[2:0] bits in Table 138. Extended Page 2, page 115 of the register map control the number of power stages. See Table 39
for the programmable options. Bit[0] must always be enabled to ensure the stage with the current sensor is chosen. The default setting,
SWx_PWRSTG[2:0] = 111, represents the highest maximum current. The current limit for each option is also scaled by the percentage
of power stages enabled.

Table 39. Programmable current configuration

Regulators Control bits % of power stages enabled Rated current (A)

SW1AB_PWRSTG[2:0] ISW1ABMAX
0 0 1 40% 1.0

SW1AB 0 1 1 80% 2.0

1 0 1 60% 1.5

1 1 1 100% 2.5

SW1C_PWRSTG[2:0] ISW1CMAX

0 0 1 43% 0.9
SW1C 0 1 1 58% 1.2

1 0 1 86% 1.7

1 1 1 100% 2.0
SW2_PWRSTG[2:0] ISW2MAX

0 0 1 38% 0.75

SW2 0 1 1 75% 1.5

1 0 1 63% 1.25

1 1 1 100% 2.0

PF0100

NXP Semiconductors 37
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 39. Programmable current configuration (continued)

Regulators Control bits % of power stages enabled Rated current (A)

SW3A_PWRSTG[2:0] ISW3AMAX
0 0 1 40% 0.5

SW3A 0 1 1 80% 1.0

1 0 1 60% 0.75
1 1 1 100% 1.25

SW3B_PWRSTG[2:0] ISW3BMAX

0 0 1 40% 0.5
SW3B 0 1 1 80% 1.0

1 0 1 60% 0.75

1 1 1 100% 1.25

SW4_PWRSTG[2:0] ISW4MAX

0 0 1 50% 0.5

SW4 0 1 1 75% 0.75

1 0 1 75% 0.75

1 1 1 100% 1.0

6.4.4.3 SW1A/B/C
SW1/A/B/C are 2.5 A to 4.5 A buck regulators which can be configured in various phasing schemes, depending on the desired cost/
performance trade-offs. The following configurations are available:
• SW1A/B/C single phase with one inductor
• SW1A/B as a single phase with one inductor and SW1C in independent mode with one inductor
• SW1A/B as a dual phase with two inductors and SW1C in independent mode with one inductor
The desired configuration is programmed by OTP by using SW1_CONFIG[1:0] bits in the register map Table 137. Extended page 1, page
111, as shown in Table 40.
.
Table 40. SW1 configuration

SW1_CONFIG[1:0] Description

00 A/B/C single phase

01 A/B single phase, C independent mode

10 A/B dual phase, C independent mode

11 Reserved

6.4.4.3.1 SW1A/B/C single phase

In this configuration, all phases A, B, and C, are connected together to a single inductor, thus, providing up to 4.50 A current capability for
high current applications. The feedback and all other controls are accomplished by use of pin SW1CFB and SW1C control registers,
respectively. Figure 11 shows the connection for SW1A/B/C in single phase mode.
During single phase mode operation, all three phases use the same configuration for frequency, phase, and DVS speed set in
SW1CCONF register. However, the same configuration settings for frequency, phase, and DVS speed setting on SW1AB registers should
be used. The SW1FB pin should be left floating in this configuration.

PF0100

38 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

VIN
SW1AIN SW1AMODE
ISENSE
CINSW1A

SW1A/B/C Controller
SW1ALX
Driver
LSW1
COSW1A SW1AFAULT

Internal I2C
Compensation Z2
SW1FB Z1
EA VREF
DAC

VIN
SW1BIN SW1BMODE
ISENSE
CINSW1B
Controller I2C
SW1BLX
Driver Interface

SW1BFAULT

VIN
SW1CIN SW1CMODE
ISENSE
CINSW1C

Controller
SW1CLX
Driver

EP SW1CFAULT

Internal I2C
Compensation Z2
SW1CFB
Z1
VREF
EA
DAC

Figure 11. SW1A/B/C single phase block diagram

6.4.4.3.2 SW1A/B single phase - SW1C independent mode

In this configuration, SW1A/B is connected as a single phase with a single inductor, while SW1C is used as an independent output, using
its own inductor and configurations parameters. This configuration allows reduced component count by using only one inductor for SW1A/
B. As mentioned before, SW1A/B and SW1C operate independently from one another, thus, they can be operated with a different voltage
set point for normal, standby, and sleep modes, as well as switching mode selection and on/off control. Figure 12 shows the physical
connection for SW1A/B in single phase and SW1C as an independent output.

PF0100

NXP Semiconductors 39
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

VIN
SW1AIN SW1AMODE
ISENSE
CINSW1A

SW1A/B Controller
SW1ALX
Driver
LSW1A
COSW1A SW1AFAULT

Internal I2C
Compensation Z2
SW1FB Z1
EA VREF
DAC

VIN
SW1BIN SW1BMODE
ISENSE
CINSW1B
Controller I2C
SW1BLX
Driver Interface

SW1BFAULT

VIN
SW1CIN SW1CMODE
ISENSE
CINSW1C

SW1C Controller
SW1CLX
Driver
LSW1C
COSW1C SW1CFAULT
EP

Internal I2C
Compensation Z2
SW1CFB
Z1
VREF
EA
DAC

Figure 12. SW1A/B single phase, SW1C independent mode block diagram

Both SW1ALX and SW1BLX nodes operate at the same DVS, frequency, and phase configured by the SW1ABCONF register, while
SW1CLX node operates independently, using the configuration in the SW1CCONF register.

6.4.4.3.3 SW1A/B dual phase - SW1C independent mode

In this mode, SW1A/B is connected in dual phase mode using one inductor per switching node, while SW1C is used as an independent
output using its own inductor and configuration parameters. This mode provides a smaller output voltage ripple on the SW1A/B output. As
mentioned before, SW1A/B and SW1C operate independently from one another, thus, they can be operated with a different voltage set
point for normal, standby, and sleep modes, as well as switching mode selection and on/off control. Figure 13 shows the physical
connection for SW1A/B in dual phase and SW1C as an independent output.

PF0100

40 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

VIN
SW1AIN SW1AMODE
ISENSE
CINSW1A

SW1AB Controller
SW1ALX
Driver
LSW1A
COSW1A SW1AFAULT

Internal I2C
Compensation Z2
SW1FB
Z1
EA VREF
DAC

VIN
SW1BIN SW1BMODE
ISENSE
CINSW1B

Controller I2C
SW1BLX Interface
Driver
LSW1B
COSW1B SW1BFAULT

VIN
SW1CIN SW1CMODE
ISENSE
CINSW1C

SW1C Controller
SW1CLX
Driver
LSW1C
COSW1C SW1CFAULT
EP

Internal I2C
Compensation Z2
SW1CFB Z1
VREF
EA
DAC

Figure 13. SW1A/B dual phase, SW1C independent mode block diagram

In this mode of operation, SW1ALX and SW1BLX nodes operate automatically at 180 ° phase shift from each other and use the same
frequency and DVS configured by SW1ABCONF register, while SW1CLX node operate independently using the configuration in the
SW1CCONF register.

6.4.4.3.4 SW1A/B/C setup and control registers

SW1A/B and SW1C output voltages are programmable from 0.300 V to 1.875 V in steps of 25 mV. The output voltage set point is
independently programmed for normal, standby, and sleep mode by setting the SW1x[5:0], SW1xSTBY[5:0], and SW1xOFF[5:0] bits
respectively. Table 41 shows the output voltage coding for SW1A/B or SW1C.
Note: Voltage set points of 0.6 V and below are not supported.

PF0100

NXP Semiconductors 41
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 41. SW1A/B/C output voltage configuration

SW1x[5:0] SW1x[5:0]
Set point SW1xSTBY[5:0] SW1x output (V) Set point SW1xSTBY[5:0] SW1x output (V)
SW1xOFF[5:0] SW1xOFF[5:0]

0 000000 0.3000 32 100000 1.1000

1 000001 0.3250 33 100001 1.1250

2 000010 0.3500 34 100010 1.1500

3 000011 0.3750 35 100011 1.1750

4 000100 0.4000 36 100100 1.2000

5 000101 0.4250 37 100101 1.2250

6 000110 0.4500 38 100110 1.2500

7 000111 0.4750 39 100111 1.2750

8 001000 0.5000 40 101000 1.3000

9 001001 0.5250 41 101001 1.3250

10 001010 0.5500 42 101010 1.3500

11 001011 0.5750 43 101011 1.3750

12 001100 0.6000 44 101100 1.4000

13 001101 0.6250 45 101101 1.4250

14 001110 0.6500 46 101110 1.4500

15 001111 0.6750 47 101111 1.4750

16 010000 0.7000 48 110000 1.5000

17 010001 0.7250 49 110001 1.5250

18 010010 0.7500 50 110010 1.5500

19 010011 0.7750 51 110011 1.5750

20 010100 0.8000 52 110100 1.6000

21 010101 0.8250 53 110101 1.6250

22 010110 0.8500 54 110110 1.6500

23 010111 0.8750 55 110111 1.6750

24 011000 0.9000 56 111000 1.7000

25 011001 0.9250 57 111001 1.7250

26 011010 0.9500 58 111010 1.7500

27 011011 0.9750 59 111011 1.7750

28 011100 1.0000 60 111100 1.8000

29 011101 1.0250 61 111101 1.8250

30 011110 1.0500 62 111110 1.8500

31 011111 1.0750 63 111111 1.8750

PF0100

42 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 42 provides a list of registers used to configure and operate SW1A/B/C and a detailed description on each one of these register is
provided in Table 43 through Table 52.

Table 42. SW1A/B/C register summary

Register Address Output

SW1ABVOLT 0x20 SW1AB output voltage set point in normal operation

SW1ABSTBY 0x21 SW1AB output voltage set point on standby

SW1ABOFF 0x22 SW1AB output voltage set point on sleep

SW1ABMODE 0x23 SW1AB switching mode selector register

SW1ABCONF 0x24 SW1AB DVS, phase, frequency and ILIM configuration

SW1CVOLT 0x2E SW1C output voltage set point in normal operation

SW1CSTBY 0x2F SW1C output voltage set point in standby

SW1COFF 0x30 SW1C output voltage set point in sleep

SW1CMODE 0x31 SW1C switching mode selector register

SW1CCONF 0x32 SW1C DVS, phase, frequency and ILIM configuration

Table 43. Register SW1ABVOLT - ADDR 0x20

Name Bit # R/W Default Description

Sets the SW1AB output voltage during normal

SW1AB 5:0 R/W 0x00 operation mode. See Table 41 for all possible
configurations.

UNUSED 7:6 – 0x00 unused

Table 44. Register SW1ABSTBY - ADDR 0x21

Name Bit # R/W Default Description

Sets the SW1AB output voltage during standby

SW1ABSTBY 5:0 R/W 0x00 mode. See Table 41 for all possible
configurations.

UNUSED 7:6 – 0x00 unused

Table 45. Register SW1ABOFF - ADDR 0x22

Name Bit # R/W Default Description

Sets the SW1AB output voltage during sleep

SW1ABOFF 5:0 R/W 0x00 mode. See Table 41 for all possible
configurations.

UNUSED 7:6 – 0x00 unused

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NXP Semiconductors 43
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 46. Register SW1ABMODE - ADDR 0x23

Name Bit # R/W Default Description

Sets the SW1AB switching operation mode.

SW1ABMODE 3:0 R/W 0x08
See Table 31 for all possible configurations.

UNUSED 4 – 0x00 unused

Set status of SW1AB when in sleep mode

SW1ABOMODE 5 R/W 0x00 • 0 = OFF
• 1 = PFM

UNUSED 7:6 – 0x00 unused

Table 47. Register SW1ABCONF - ADDR 0x24

Name Bit # R/W Default Description

SW1AB current limit level selection

SW1ABILIM 0 R/W 0x00 • 0 = High level current limit
• 1 = Low level current limit

UNUSED 1 R/W 0x00 unused

SW1A/B switching frequency selector. See

SW1ABFREQ 3:2 R/W 0x00
Table 38.

SW1ABPHASE 5:4 R/W 0x00 SW1A/B phase clock selection. See Table 36.

SW1ABDVSSPEED 7:6 R/W 0x00 SW1A/B DVS speed selection. See Table 34.

Table 48. Register SW1CVOLT - ADDR 0x2E

Name Bit # R/W Default Description

Sets the SW1C output voltage during normal

SW1C 5:0 R/W 0x00 operation mode. See Table 41 for all possible
configurations.

UNUSED 7:6 – 0x00 unused

Table 49. Register SW1CSTBY - ADDR 0x2F

Name Bit # R/W Default Description

Sets the SW1C output voltage during standby

SW1CSTBY 5:0 R/W 0x00 mode. See Table 41 for all possible
configurations.

UNUSED 7:6 – 0x00 unused

Table 50. Register SW1COFF - ADDR 0x30

Name Bit # R/W Default Description

Sets the SW1C output voltage during sleep

SW1COFF 5:0 R/W 0x00 mode. See Table 41 for all possible
configurations.

UNUSED 7:6 – 0x00 unused

PF0100

44 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 51. Register SW1CMODE - ADDR 0x31

Name Bit # R/W Default Description

Sets the SW1C switching operation mode.

SW1CMODE 3:0 R/W 0x08
See Table 30 for all possible configurations.

UNUSED 4 – 0x00 unused

Set status of SW1C when in sleep mode

SW1COMODE 5 R/W 0x00 • 0 = OFF
• 1 = PFM

UNUSED 7:6 – 0x00 unused

Table 52. Register SW1CCONF - ADDR 0x32

Name Bit # R/W Default Description

SW1C current limit level selection

SW1CILIM 0 R/W 0x00 • 0 = High level current limit
• 1 = Low level current limit

UNUSED 1 R/W 0x00 unused

SW1C switching frequency selector. See

SW1CFREQ 3:2 R/W 0x00
Table 38.
SW1CPHASE 5:4 R/W 0x00 SW1C phase clock selection.See Table 36.

SW1CDVSSPEED 7:6 R/W 0x00 SW1C DVS speed selection. See Table 34.

6.4.4.3.5 SW1A/B/C external components

Table 53. SW1A/B/C external component recommendations

Mode
Components Description A/B/C single A/B Single - C A/B Dual - C
phase independent mode independent mode

CINSW1A(44) SW1A input capacitor 4.7 μF 4.7 μF 4.7 μF

(44)
CIN1AHF SW1A decoupling input capacitor 0.1 μF 0.1 μF 0.1 μF
(44)
CINSW1B SW1B input capacitor 4.7 μF 4.7 μF 4.7 μF
(44)
CIN1BHF SW1B decoupling input capacitor 0.1 μF 0.1 μF 0.1 μF
(44)
CINSW1C SW1C input capacitor 4.7 μF 4.7 μF 4.7 μF
(44)
CIN1CHF SW1C decoupling input capacitor 0.1 μF 0.1 μF 0.1 μF
(44)
COSW1AB SW1A/B output capacitor 6 x 22 μF 2 x 22 μF 4 x 22 μF
(44)
COSW1C SW1C output capacitor – 3 x 22 μF 3 x 22 μF

LSW1A SW1A inductor 1.0 μH 1.0 μH 1.0 μH

LSW1B SW1B inductor – – 1.0 μH

LSW1C SW1C inductor – 1.0 μH 1.0 μH

Notes
44. Use X5R or X7R capacitors.

PF0100

NXP Semiconductors 45
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.4.4.3.6 SW1A/B/C specifications

Table 54. SW1A/B/C electrical characteristics

All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA,
SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are
characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

SW1A/B/C (single phase)

VINSW1A
VINSW1B Operating input voltage 2.8 – 4.5 V
VINSW1C

VSW1ABC Nominal output voltage – Table 41 – V

Output voltage accuracy

• PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1ABC < 4.5 A
• 0.625 V ≤ VSW1ABC ≤ 1.450 V -25 – 25
• 1.475 V ≤ VSW1ABC ≤ 1.875 V -3.0% – 3.0%
mV
VSW1ABCACC
%
• PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW1ABC < 150 mA
• 0.625 V < VSW1ABC < 0.675 V -65 – 65
• 0.7 V < VSW1ABC < 0.85 V -45 – 45
• 0.875 V < VSW1ABC < 1.875 V -3.0% – 3.0%

Rated output load current,

ISW1ABC – – 4500 mA
• 2.8 V < VIN < 4.5 V, 0.625 V < VSW1ABC < 1.875 V
Current limiter peak current detection
• Current through inductor
ISW1ABCLIM A
• SW1ABILIM = 0 7.1 10.5 13.7
• SW1ABILIM = 1 5.3 7.9 10.3

Start-up overshoot
VSW1ABCOSH • ISW1ABC = 0 mA – – 66 mV
• DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1ABC = 1.875 V
Turn-on time
• Enable to 90% of end value
tONSW1ABC • ISW1x = 0 mA – – 500 µs
• DVS clk = 25 mV/4.0 μs, VIN = VINSW1x = 4.5 V,
VSW1ABC = 1.875 V

Switching frequency
• SW1xFREQ[1:0] = 00 – 1.0 –
fSW1ABC MHz
• SW1xFREQ[1:0] = 01 – 2.0 –
• SW1xFREQ[1:0] = 10 – 4.0 –

Efficiency
• VIN = 3.6 V, fSW1ABC = 2.0 MHz, LSW1ABC = 1.0 μH
• PFM, 0.9 V, 1.0 mA – 77 –
• PFM, 1.2 V, 50 mA – 82 –
ηSW1ABC %
• APS, PWM, 1.2 V, 850 mA – 86 –
• APS, PWM, 1.2 V, 1275 mA – 84 –
• APS, PWM, 1.2 V, 2125 mA – 80 –
• APS, PWM, 1.2 V, 4500 mA – 68 –

ΔVSW1ABC Output ripple – 10 – mV

VSW1ABCLIR Line regulation (APS, PWM) – – 20 mV

VSW1ABCLOR DC load regulation (APS, PWM) – – 20 mV

PF0100

46 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 54. SW1A/B/C electrical characteristics (continued)

All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA,
SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are
characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

SW1A/B/C (single phase) (continued)

Transient load regulation

• Transient load = 0 to 2.25 A, di/dt = 100 mA/μs
VSW1ABCLOTR mV
• Overshoot – – 50
• Undershoot – – 50

Quiescent current
ISW1ABCQ • PFM Mode – 18 – µA
• APS Mode – 145 –

RSW1ABCDIS Discharge resistance – 600 – Ω

SW1A/B (single/dual phase)

VINSW1A
Operating input voltage 2.8 – 4.5 V
VINSW1B

VSW1AB Nominal output voltage – Table 41 – V

Output voltage accuracy

• PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1AB < 2.5 A
• 0.625 V ≤ VSW1AB ≤ 1.450 V -25 - 25
• 1.475 V ≤ VSW1AB ≤ 1.875 V -3.0% - 3.0%
mV
VSW1ABACC
%
• PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW1AB < 150 mA
• 0.625 V < VSW1AB < 0.675 V -65 – 65
• 0.7 V < VSW1AB < 0.85 V -45 – 45
• 0.875 V < VSW1AB < 1.875 V -3.0% – 3.0%

Rated output load current, (46)

ISW1AB – – 2500 mA
• 2.8 V < VIN < 4.5 V, 0.625 V < VSW1AB < 1.875 V

Current limiter peak current detection

• SW1A/B single phase (current through inductor)
• SW1ABILIM = 0 4.5 6.5 8.5
• SW1ABILIM = 1 3.3 4.9 6.4 (46)
ISW1ABLIM A
•
• SW1A/B dual phase (current through inductor per phase)
• SW1ABILIM = 0 2.2 3.2 4.3
• SW1ABILIM = 1 1.6 2.4 3.2

Start-up overshoot
VSW1ABOSH • ISW1AB = 0.0 mA – – 66 mV
• DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V
Turn-on time
• Enable to 90% of end value
tONSW1AB – – 500 µs
• ISW1AB = 0.0 mA
• DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V

Switching frequency
• SW1ABFREQ[1:0] = 00 – 1.0 –
fSW1AB MHz
• SW1ABFREQ[1:0] = 01 – 2.0 –
• SW1ABFREQ[1:0] = 10 – 4.0 –

PF0100

NXP Semiconductors 47
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 54. SW1A/B/C electrical characteristics (continued)

All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA,
SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are
characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

SW1A/B (single/dual phase) (continued)

Efficiency (single phase)

• VIN = 3.6 V, fSW1AB = 2.0 MHz, LSW1AB = 1.0 μH
• PFM, 0.9 V, 1.0 mA – 82 –
• PFM, 1.2 V, 50 mA – 84 –
ηSW1AB %
• APS, PWM, 1.2 V, 500 mA – 86 –
• APS, PWM, 1.2 V, 750 mA – 87 –
• APS, PWM, 1.2 V, 1250 mA – 82 –
• APS, PWM, 1.2 V, 2500 mA – 71 –

ΔVSW1AB Output ripple – 10 – mV

VSW1ABLIR Line regulation (APS, PWM) – – 20 mV

VSW1ABLOR DC load regulation (APS, PWM) – – 20 mV

Transient load regulation

• Transient load = 0 to 1.25 A, di/dt = 100 mA/μs
VSW1ABLOTR mV
• Overshoot – – 50
• Undershoot – – 50

Quiescent current
ISW1ABQ • PFM mode – 18 – µA
• APS mode – 235 –
SW1A P-MOSFET RDS(on)
RONSW1AP – 215 245 mΩ
• VINSW1A = 3.3 V

SW1A N-MOSFET RDS(on)

RONSW1AN – 258 326 mΩ
• VINSW1A = 3.3 V

SW1A P-MOSFET leakage current

ISW1APQ – – 7.5 µA
• VINSW1A = 4.5 V
SW1A N-MOSFET leakage current
ISW1ANQ – – 2.5 µA
• VINSW1A = 4.5 V

SW1B P-MOSFET RDS(on)

RONSW1BP – 215 245 mΩ
• VINSW1B = 3.3 V

SW1B N-MOSFET RDS(on)

RONSW1BN – 258 326 mΩ
• VINSW1B = 3.3 V
SW1B P-MOSFET leakage current
ISW1BPQ – – 7.5 µA
• VINSW1B = 4.5 V

SW1B N-MOSFET leakage current

ISW1BNQ – – 2.5 µA
• VINSW1B = 4.5 V

RSW1ABDIS Discharge resistance – 600 – Ω

PF0100

48 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 54. SW1A/B/C electrical characteristics (continued)

All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA,
SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are
characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

SW1C (independent)

VINSW1C Operating input voltage 2.8 – 4.5 V

VSW1C Nominal output voltage – Table 41 – V

Output voltage accuracy

• PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1C < 2.0 A
• 0.625 V ≤ VSW1C ≤ 1.450 V -25 – 25
• 1.475 V ≤ VSW1C ≤ 1.875 V -3.0% – 3.0%
VSW1CACC mV
• PFM, steady state 2.8 V < VIN < 4.5 V, 0 < ISW1C < 50 mA
• 0.625 V < VSW1C < 0.675 V -65 – 65
• 0.7 V < VSW1C < 0.85 V -45 – 45
• 0.875 V < VSW1C < 1.875 V -3.0% – 3.0%

Rated output load current

ISW1C – – 2000 mA
• 2.8 V < VIN < 4.5 V, 0.625 V < VSW1C < 1.875 V

Current limiter peak current detection

• Current through inductor
ISW1CLIM A (45)
• SW1CILIM = 0 2.6 4.0 5.2
• SW1CILIM = 1 1.95 3.0 3.9 —

Start-up overshoot
VSW1COSH • ISW1C = 0 mA – – 66 mV
• DVS clk = 25 mV/4 μs, VIN = VINSW1C = 4.5 V, VSW1C = 1.875 V

Turn-on time
• Enable to 90% of end value
tONSW1C – – 500 µs
• ISW1C = 0 mA
• DVS clk = 25 mV/4 μs, VIN = VINSW1C = 4.5 V, VSW1C = 1.875 V

Switching frequency
• SW1CFREQ[1:0] = 00 – 1.0 –
fSW1C MHz
• SW1CFREQ[1:0] = 01 – 2.0 –
• SW1CFREQ[1:0] = 10 – 4.0 –
Efficiency
• VIN = 3.6 V, fSW1C = 2.0 MHz, LSW1C = 1.0 μH
• PFM, 0.9 V, 1.0 mA – 77 –
• PFM, 1.2 V, 50 mA – 78 –
ηSW1C %
• APS, PWM, 1.2 V, 400 mA – 86 –
• APS, PWM, 1.2 V, 600 mA – 84 –
• APS, PWM, 1.2 V, 1000 mA – 78 –
• APS, PWM, 1.2 V, 2000 mA – 65 –

ΔVSW1C Output ripple – 10 – mV

VSW1CLIR Line regulation (APS, PWM) – – 20 mV

VSW1CLOR DC load regulation (APS, PWM) – – 20 mV

Transient load regulation

• Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/μs
VSW1CLOTR mV
• Overshoot – – 50
• Undershoot – – 50

Quiescent current
ISW1CQ • PFM mode – 22 – µA
• APS mode – 145 –

PF0100

NXP Semiconductors 49
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 54. SW1A/B/C electrical characteristics (continued)

All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA,
SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are
characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

SW1C (independent) (continued)

SW1C P-MOSFET RDS(on)

RONSW1CP – mΩ
• at VINSW1C = 3.3 V 184 206

SW1C N-MOSFET RDS(on)

RONSW1CN – mΩ
• at VINSW1C = 3.3 V 211 260

SW1C P-MOSFET leakage current

ISW1CPQ – – 10.5 µA
• VINSW1C = 4.5 V
SW1C N-MOSFET leakage current
ISW1CNQ – – 3.5 µA
• VINSW1C = 4.5 V

RSW1CDIS Discharge resistance – 600 – Ω

Notes
45. Meets 1.89 A current rating for VDDSOC_IN domain on i.MX 6X processor.
46. Current rating of SW1AB supports the power virus mode of operation of the i.MX 6X processor.

100 100
90 90
80 80
) 70 ) 70
Efficiency (%)

Efficiency (%)

%
( %
(
y 60 y 60
c c
n 50 n 50
e
i e
i
ic
ff 40 ic
ff 40
E 30 E 30
APS
20 PFM 20
PWM
10 10
0 0
0.1 1 10 100 1000 10 100 1000 10000
Load Current (mA) Load Current (mA)

Figure 14. SW1AB efficiency waveforms: VIN = 4.2 V; VOUT = 1.375 V; consumer version

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50 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

100 100
90 90
80 80
Efficiency (%)

Efficiency (%)
) 70
(% 70 %
(
y 60 y 60
c c
n 50 n 50
e
i 40 e
i
c
if c
if 40
f 30 f
E E 30 APS
20 PFM 20
10 PWM
10
0 0
0.1 1 10 100 1000 10 100 1000 10000
Load Current (mA) Load Current (mA)

Figure 15. SW1AB efficiency waveforms: VIN = 4.2 V; VOUT = 1.375 V; extended industrial version

100 100
90 90
80 80
Efficiency (%)
) 70
Efficiency (%)

) 70
%
( %
(
y 60 y 60
c c
n 50 n 50
e
i e
i
ic
ff 40 ic
ff 40
E 30 E 30
APS
20 PFM 20
10 PWM
10
0 0
0.1 1 10 100 1000 10 100 1000 10000
Load Current (mA) Load Current (mA)

Figure 16. SW1C efficiency waveforms: VIN = 4.2 V; VOUT = 1.375 V; consumer version

100 100
90 90
80 80
Efficiency (%)

Efficiency (%)

) 70 ) 70
(% (%
y 60 y 60
c c
n 50 n 50
e
i e
i
c c
if 40
f fif 40
E 30 E 30
APS
20 PFM 20
PWM
10 10
0 0
0.1 1 10 100 1000 10 100 1000 10000
Load Current (mA) Load Current (mA)

Figure 17. SW1C efficiency waveforms: VIN = 4.2 V; VOUT = 1.375 V; extended industrial version

PF0100

NXP Semiconductors 51
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.4.4.4 SW2
SW2 is a single phase, 2.0 A rated buck regulator (2.5 A in NP, F9, and FA Industrial versions only (ANES suffix)). Table 30 describes the
modes, and Table 31 show the options for the SWxMODE[3:0] bits. Figure 18 shows the block diagram and the external component
connections for SW2 regulator.

VIN
SW2IN SW2MODE
ISENSE
CINSW2

SW2 Controller
SW2LX
Driver
LSW2
COSW2 SW2FAULT
EP
I2C
Interface

Internal I2C
Compensation Z2
SW2FB
Z1
VREF
EA
DAC

Figure 18. SW2 block diagram

6.4.4.4.1 SW2 setup and control registers

SW2 output voltage is programmable from 0.400 V to 3.300 V; however, bit SW2[6] in register SW2VOLT is read-only during normal
operation. Its value is determined by the default configuration, or may be changed by using the OTP registers. Therefore, once SW2[6] is
set to “0”, the output is limited to the lower output voltages from 0.400 V to 1.975 V with 25 mV increments, as determined by bits SW2[5:0].
Likewise, once bit SW2[6] is set to “1”, the output voltage is limited to the higher output voltage range from 0.800 V to 3.300 V with 50 mV
increments, as determined by bits SW2[5:0].
In order to optimize the performance of the regulator, it is recommended only voltages from 2.000 V to 3.300 V be used in the high range,
and the lower range be used for voltages from 0.400 V to 1.975 V.
The output voltage set point is independently programmed for normal, standby, and sleep mode by setting the SW2[5:0], SW2STBY[5:0]
and SW2OFF[5:0] bits, respectively. However, the initial state of bit SW2[6] are copied into bits SW2STBY[6], and SW2OFF[6] bits.
Therefore, the output voltage range remains the same in all three operating modes. Table 55 shows the output voltage coding valid for
SW2.
Note: Voltage set points of 0.6 V and below are not supported.

Table 55. SW2 output voltage configuration

Low output voltage range(47) High output voltage range

Set point SW2[6:0] SW2 output Set point SW2[6:0] SW2 output

0 0000000 0.4000 64 1000000 0.8000

1 0000001 0.4250 65 1000001 0.8500

2 0000010 0.4500 66 1000010 0.9000

3 0000011 0.4750 67 1000011 0.9500

4 0000100 0.5000 68 1000100 1.0000

5 0000101 0.5250 69 1000101 1.0500

6 0000110 0.5500 70 1000110 1.1000

7 0000111 0.5750 71 1000111 1.1500

8 0001000 0.6000 72 1001000 1.2000

9 0001001 0.6250 73 1001001 1.2500

10 0001010 0.6500 74 1001010 1.3000

11 0001011 0.6750 75 1001011 1.3500

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Table 55. SW2 output voltage configuration (continued)

Low output voltage range(47) High output voltage range

Set point SW2[6:0] SW2 output Set point SW2[6:0] SW2 output

12 0001100 0.7000 76 1001100 1.4000

13 0001101 0.7250 77 1001101 1.4500

14 0001110 0.7500 78 1001110 1.5000

15 0001111 0.7750 79 1001111 1.5500

16 0010000 0.8000 80 1010000 1.6000

17 0010001 0.8250 81 1010001 1.6500

18 0010010 0.8500 82 1010010 1.7000

19 0010011 0.8750 83 1010011 1.7500

20 0010100 0.9000 84 1010100 1.8000

21 0010101 0.9250 85 1010101 1.8500

22 0010110 0.9500 86 1010110 1.9000

23 0010111 0.9750 87 1010111 1.9500

24 0011000 1.0000 88 1011000 2.0000

25 0011001 1.0250 89 1011001 2.0500

26 0011010 1.0500 90 1011010 2.1000

27 0011011 1.0750 91 1011011 2.1500

28 0011100 1.1000 92 1011100 2.2000

29 0011101 1.1250 93 1011101 2.2500

30 0011110 1.1500 94 1011110 2.3000

31 0011111 1.1750 95 1011111 2.3500

32 0100000 1.2000 96 1100000 2.4000

33 0100001 1.2250 97 1100001 2.4500

34 0100010 1.2500 98 1100010 2.5000

35 0100011 1.2750 99 1100011 2.5500

36 0100100 1.3000 100 1100100 2.6000

37 0100101 1.3250 101 1100101 2.6500

38 0100110 1.3500 102 1100110 2.7000

39 0100111 1.3750 103 1100111 2.7500

40 0101000 1.4000 104 1101000 2.8000

41 0101001 1.4250 105 1101001 2.8500

42 0101010 1.4500 106 1101010 2.9000

43 0101011 1.4750 107 1101011 2.9500

44 0101100 1.5000 108 1101100 3.0000

45 0101101 1.5250 109 1101101 3.0500

46 0101110 1.5500 110 1101110 3.1000

47 0101111 1.5750 111 1101111 3.1500

48 0110000 1.6000 112 1110000 3.2000

49 0110001 1.6250 113 1110001 3.2500

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Table 55. SW2 output voltage configuration (continued)

Low output voltage range(47) High output voltage range

Set point SW2[6:0] SW2 output Set point SW2[6:0] SW2 output

50 0110010 1.6500 114 1110010 3.3000

51 0110011 1.6750 115 1110011 Reserved

52 0110100 1.7000 116 1110100 Reserved

53 0110101 1.7250 117 1110101 Reserved

54 0110110 1.7500 118 1110110 Reserved

55 0110111 1.7750 119 1110111 Reserved

56 0111000 1.8000 120 1111000 Reserved

57 0111001 1.8250 121 1111001 Reserved

58 0111010 1.8500 122 1111010 Reserved

59 0111011 1.8750 123 1111011 Reserved

60 0111100 1.9000 124 1111100 Reserved

61 0111101 1.9250 125 1111101 Reserved

62 0111110 1.9500 126 1111110 Reserved

63 0111111 1.9750 127 1111111 Reserved

Notes
47. For voltages less than 2.0 V, only use set points 0 to 63.

Setup and control of SW2 is done through I2C registers listed in Table 56, and a detailed description of each one of the registers is provided
in Tables 57 to Table 61.

Table 56. SW2 register summary

Register Address Description

SW2VOLT 0x35 Output voltage set point on normal operation

SW2STBY 0x36 Output voltage set point on standby

SW2OFF 0x37 Output voltage set point on sleep

SW2MODE 0x38 Switching mode selector register

SW2CONF 0x39 DVS, phase, frequency, and ILIM configuration

Table 57. Register SW2VOLT - ADDR 0x35

Name Bit # R/W Default Description

Sets the SW2 output voltage during normal operation

SW2 5:0 R/W 0x00
mode. See Table 55 for all possible configurations.
Sets the operating output voltage range for SW2. Set
SW2 6 R 0x00 during OTP or TBB configuration only. See Table 55
for all possible configurations.
UNUSED 7 – 0x00 unused

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Table 58. Register SW2STBY - ADDR 0x36

Name Bit # R/W Default Description

Sets the SW2 output voltage during standby mode.

SW2STBY 5:0 R/W 0x00
See Table 55 for all possible configurations.
Sets the operating output voltage range for SW2 on
standby mode. This bit inherits the value configured
SW2STBY 6 R 0x00
on bit SW2[6] during OTP or TBB configuration. See
Table 55 for all possible configurations.
UNUSED 7 – 0x00 unused

Table 59. Register SW2OFF - ADDR 0x37

Name Bit # R/W Default Description

Sets the SW2 output voltage during sleep mode. See

SW2OFF 5:0 R/W 0x00
Table 55 for all possible configurations.
Sets the operating output voltage range for SW2 on
sleep mode. This bit inherits the value configured on
SW2OFF 6 R 0x00
bit SW2[6] during OTP or TBB configuration. See
Table 55 for all possible configurations.
UNUSED 7 – 0x00 unused

Table 60. Register SW2MODE - ADDR 0x38

Name Bit # R/W Default Description

Sets the SW2 switching operation mode.

SW2MODE 3:0 R/W 0x08
See Table 30 for all possible configurations.
UNUSED 4 – 0x00 unused
Set status of SW2 when in sleep mode
SW2OMODE 5 R/W 0x00 • 0 = OFF
• 1 = PFM
UNUSED 7:6 – 0x00 unused

Table 61. Register SW2CONF - ADDR 0x39

Name Bit # R/W Default Description

SW2 current limit level selection (48)

SW2ILIM 0 R/W 0x00 • 0 = High level current limit
• 1 = Low level current limit
UNUSED 1 R/W 0x00 unused
SW2FREQ 3:2 R/W 0x00 SW2 switching frequency selector. See Table 38.
SW2PHASE 5:4 R/W 0x00 SW2 phase clock selection. See Table 36.
SW2DVSSPEED 7:6 R/W 0x00 SW2 DVS speed selection. See Table 35.
Notes
48. SW2ILIM = 0 must be used in NP/F9/FA versions (Industrial only) if 2.5 A output load current is
desired

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6.4.4.4.2 SW2 external components

Table 62. SW2 external component recommendations

Components Description Values

CINSW2(49) SW2 input capacitor 4.7 μF

(49)
CIN2HF SW2 decoupling input capacitor 0.1 μF
(49)
COSW2 SW2 output capacitor 3 x 22 μF
LSW2 SW2 inductor 1.0 μH
Notes
49. Use X5R or X7R capacitors.

6.4.4.4.3 SW2 Specifications

Table 63. SW2 electrical characteristics

All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA,
SW2_PWRSTG[2:0] = [111], typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are
characterized at VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

Symbol Parameter Min Typ Max Unit Notes

Switch mode supply SW2

(50)
VINSW2 Operating input voltage 2.8 – 4.5 V

VSW2 Nominal output voltage – Table 55 – V

Output voltage accuracy

• PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW2 < 2.0 A
• 0.625 V < VSW2 < 0.85 V -25 – 25
• 0.875 V < VSW2 < 1.975 V -3.0% – 3.0%
• 2.0 V < VSW2 < 3.3 V -6.0% – 6.0%
mV
VSW2ACC
%
• PFM, 2.8 V < VIN < 4.5 V, 0 < ISW2 ≤ 50 mA
• 0.625 V < VSW2 < 0.675 V -65 – 65
• 0.7 V < VSW2 < 0.85 V -45 – 45
• 0.875 V < VSW2 < 1.975 V -3.0% – 3.0%
• 2.0 V < VSW2 < 3.3 V -3.0% – 3.0%

Rated output load current

(51)
ISW2 • 2.8 V < VIN < 4.5 V, 0.625 V < VSW2 < 3.3 V – – 2000 mA
(52)
• 2.8 V < VIN < 4.5 V, 1.2 V < VSW2 < 3.3 V, SW2LIM = 0 – – 2500
Current limiter peak current detection
• Current through inductor
ISW2LIM A
• SW2ILIM = 0 2.8 4.0 5.2
• SW2ILIM = 1 2.1 3.0 3.9

Start-up overshoot
VSW2OSH • ISW2 = 0.0 mA – – 66 mV
• DVS clk = 25 mV/4 μs, VIN = VINSW2 = 4.5 V
Turn-on time
• Enable to 90% of end value
tONSW2 – – 550 µs
• ISW2 = 0.0 mA
• DVS clk = 50 mV/8 μs, VIN = VINSW2 = 4.5 V

Switching frequency
• SW2FREQ[1:0] = 00 – 1.0 –
fSW2 MHz
• SW2FREQ[1:0] = 01 – 2.0 –
• SW2FREQ[1:0] = 10 – 4.0 –

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Table 63. SW2 electrical characteristics (continued)

All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA,
SW2_PWRSTG[2:0] = [111], typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are
characterized at VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

Symbol Parameter Min Typ Max Unit Notes

Switch mode supply SW2 (continued)

Efficiency
• VIN = 3.6 V, fSW2 = 2.0 MHz, LSW2 = 1.0 μH
• PFM, 3.15 V, 1.0 mA – 94 –
• PFM, 3.15 V, 50 mA – 95 –
ηSW2 %
• APS, PWM, 3.15 V, 400 mA – 96 –
• APS, PWM, 3.15 V, 600 mA – 94 –
• APS, PWM, 3.15 V, 1000 mA – 92 –
• APS, PWM, 3.15 V, 2000 mA – 86 –

ΔVSW2 Output ripple – 10 – mV

VSW2LIR Line regulation (APS, PWM) – – 20 mV

VSW2LOR DC load regulation (APS, PWM) – – 20 mV

Transient load regulation

• Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/μs
VSW2LOTR mV
• Overshoot – – 50
• Undershoot – – 50

Quiescent current
• PFM mode – 23 –
ISW2Q µA
• APS mode (low output voltage settings) – 145 –
• APS mode (high output voltage settings) – 305 –

SW2 P-MOSFET RDS(on)

RONSW2P – 190 209 mΩ
• at VIN = VINSW2 = 3.3 V

SW2 N-MOSFET RDS(on)

RONSW2N – 212 255 mΩ
• at VIN = VINSW2 = 3.3 V
SW2 P-MOSFET leakage current
ISW2PQ – – 12 µA
• VIN = VINSW2 = 4.5 V

SW2 N-MOSFET leakage current

ISW2NQ – – 4.0 µA
• VIN = VINSW2 = 4.5 V

RSW2DIS Discharge resistance – 600 – Ω

Notes
50. When output is set to > 2.6 V the output follows the input down when VIN gets near 2.8 V.
51. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation:
(VINSW2 - VSW2) = ISW2* (DCR of Inductor +RONSW2P + PCB trace resistance).
52. Applies to NP, F9, and FA Industrial versions only (ANES suffix)

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NXP Semiconductors 57
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100 100
90 90
80 80

Efficiency (%)
) 70 ) 70
Efficiency (%)

%
( %
(
y 60 y 60
c c
n 50 n 50
e
i e
i
ic
ff 40 ic
ff 40
E 30 E 30
PFM APS
20 20
10 10 PWM
0 0
0.1 1 10 100 1000 10 100 1000 10000
Load Current (mA) Load Current (mA)

Figure 19. sw2 Efficiency Waveforms: VIN = 4.2 V; VOUT = 3.0 V; consumer version

100 100
90 90
80 80
Efficiency (%)

Efficiency (%)
) 70 ) 70
%
( %
(
y 60 y 60
c c
n 50 n 50
e
i e
i
c
if 40 ic
f ff 40
E 30 E 30
20 PFM APS
20
10 10 PWM
0 0
0.1 1 10 100 1000 10 100 1000 10000
Load Current (mA) Load Current (mA)

Figure 20. sw2 efficiency waveforms: vin = 4.2 v; vout = 3.0 v; Extended Industrial Version

6.4.4.4.4 SW3A/B
SW3A/B are 1.25 to 2.5 A rated buck regulators, depending on the configuration. Table 30 describes the available switching modes and
Table 31 show the actual configuration options for the SW3xMODE[3:0] bits. SW3A/B can be configured in various phasing schemes,
depending on the desired cost/performance trade-offs. The following configurations are available:
• A single phase
• A dual phase
• Independent regulators
The desired configuration is programmed in OTP by using the SW3_CONFIG[1:0] bits.Table 64 shows the options for the SW3CFG[1:0]
bits.

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Table 64. SW3 configuration

SW3_CONFIG[1:0] Description

00 A/B single phase

01 A/B single phase

10 A/B dual phase

11 A/B independent

6.4.4.4.5 SW3A/B single phase

In this configuration, SW3ALX and SW3BLX are connected in single phase with a single inductor a shown in Figure 21. This configuration
reduces cost and component count. Feedback is taken from the SW3AFB pin and the SW3BFB pin must be left open. Although control
is from SW3A, registers of both regulators, SW3A and SW3B, must be identically set.

VIN
SW3AIN SW3AMODE
ISENSE
CINSW3A

SW3 Controller
SW3ALX
Driver
LSW3A
COSW3A SW3AFAULT

Internal I2C
Compensation Z2
SW3AFB Z1 I2C
VREF Interface
EA
DAC

VIN
SW3BIN SW3BMODE
ISENSE
CINSW3B
Controller
SW3BLX
Driver

EP SW3BFAULT

I2C
Internal
Compensation Z2
SW3BFB VREF
Z1 DAC
EA

Figure 21. SW3A/B single phase block diagram

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6.4.4.4.6 SW3A/B dual phase

SW3A/B can be connected in dual phase configuration using one inductor per switching node, as shown in Figure 22. This mode allows
a smaller output voltage ripple. Feedback is taken from pin SW3AFB and pin SW3BFB must be left open. Although control is from SW3A,
registers of both regulators, SW3A and SW3B, must be identically set. In this configuration, the regulators switch 180 degrees apart.

VIN
SW3AIN SW3AMODE
ISENSE
CINSW3A

SW3 Controller
SW3ALX
Driver
LSW3A
COSW3A SW3AFAULT

Internal I2C
Compensation Z2
SW3AFB I2C
Z1 Interface
VREF
EA
DAC

VIN
SW3BIN SW3BMODE
ISENSE
CINSW3B

Controller
SW3BLX
Driver
LSW3B
COSW3B SW3BFAULT
EP

I2C
Internal
Compensation Z2
SW3BFB VREF
Z1 DAC
EA

Figure 22. SW3A/B dual phase block diagram

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6.4.4.4.7 SW3A - SW3B independent outputs

SW3A and SW3B can be configured as independent outputs as shown in Figure 23, providing flexibility for applications requiring more
voltage rails with less current capability. Each output is configured and controlled independently by its respective I2C registers as shown
in Table 66.

VIN
SW3AIN SW3AMODE
ISENSE
CINSW3A

SW3A Controller
SW3ALX
Driver
LSW3A
COSW3A SW3AFAULT

Internal I2C
Compensation Z2
SW3AFB
Z1
VREF
EA
DAC

VIN I2C
SW3BIN Interface
SW3BMODE
ISENSE
CINSW3B

SW3B Controller
SW3BLX
Driver
LSW3B
COSW3B SW3BFAULT
EP

Internal I2C
Compensation Z2
SW3BFB
Z1
VREF
EA
DAC

Figure 23. SW3A/B independent output block diagram

6.4.4.4.8 SW3A/B Setup and Control Registers

SW3A/B output voltage is programmable from 0.400 V to 3.300 V; however, bit SW3x[6] in register SW3xVOLT is read-only during normal
operation. Its value is determined by the default configuration, or may be changed by using the OTP registers. Therefore, once SW3x[6]
is set to “0”, the output is limited to the lower output voltages from 0.40 V to 1.975 V with 25 mV increments, as determined by bits
SW3x[5:0]. Likewise, once bit SW3x[6] is set to "1", the output voltage is limited to the higher output voltage range from 0.800 V to 3.300 V
with 50 mV increments, as determined by bits SW3x[5:0].
In order to optimize the performance of the regulator, it is recommended only voltages from 2.00 V to 3.300 V be used in the high range
and the lower range be used for voltages from 0.400 V to 1.975 V.
The output voltage set point is independently programmed for normal, standby, and sleep mode by setting the SW3x[5:0],
SW3xSTBY[5:0], and SW3xOFF[5:0] bits respectively; however, the initial state of the SW3x[6] bit is copied into the SW3xSTBY[6] and
SW3xOFF[6] bits. Therefore, the output voltage range remains the same on all three operating modes. Table 65 shows the output voltage
coding valid for SW3x.
Note: Voltage set points of 0.6 V and below are not supported.

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Table 65. SW3A/B output voltage configuration

Low output voltage range (53) High output voltage range

Set point SW3x[6:0] SW3x output Set point SW3x[6:0] SW3x output

0 0000000 0.4000 64 1000000 0.8000

1 0000001 0.4250 65 1000001 0.8500

2 0000010 0.4500 66 1000010 0.9000

3 0000011 0.4750 67 1000011 0.9500

4 0000100 0.5000 68 1000100 1.0000

5 0000101 0.5250 69 1000101 1.0500

6 0000110 0.5500 70 1000110 1.1000

7 0000111 0.5750 71 1000111 1.1500

8 0001000 0.6000 72 1001000 1.2000

9 0001001 0.6250 73 1001001 1.2500

10 0001010 0.6500 74 1001010 1.3000

11 0001011 0.6750 75 1001011 1.3500

12 0001100 0.7000 76 1001100 1.4000

13 0001101 0.7250 77 1001101 1.4500

14 0001110 0.7500 78 1001110 1.5000

15 0001111 0.7750 79 1001111 1.5500

16 0010000 0.8000 80 1010000 1.6000

17 0010001 0.8250 81 1010001 1.6500

18 0010010 0.8500 82 1010010 1.7000

19 0010011 0.8750 83 1010011 1.7500

20 0010100 0.9000 84 1010100 1.8000

21 0010101 0.9250 85 1010101 1.8500

22 0010110 0.9500 86 1010110 1.9000

23 0010111 0.9750 87 1010111 1.9500

24 0011000 1.0000 88 1011000 2.0000

25 0011001 1.0250 89 1011001 2.0500

26 0011010 1.0500 90 1011010 2.1000

27 0011011 1.0750 91 1011011 2.1500

28 0011100 1.1000 92 1011100 2.2000

29 0011101 1.1250 93 1011101 2.2500

30 0011110 1.1500 94 1011110 2.3000

31 0011111 1.1750 95 1011111 2.3500

32 0100000 1.2000 96 1100000 2.4000

33 0100001 1.2250 97 1100001 2.4500

34 0100010 1.2500 98 1100010 2.5000

35 0100011 1.2750 99 1100011 2.5500

36 0100100 1.3000 100 1100100 2.6000

37 0100101 1.3250 101 1100101 2.6500

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Table 65. SW3A/B output voltage configuration

Low output voltage range (53) High output voltage range

Set point SW3x[6:0] SW3x output Set point SW3x[6:0] SW3x output

38 0100110 1.3500 102 1100110 2.7000

39 0100111 1.3750 103 1100111 2.7500

40 0101000 1.4000 104 1101000 2.8000

41 0101001 1.4250 105 1101001 2.8500

42 0101010 1.4500 106 1101010 2.9000

43 0101011 1.4750 107 1101011 2.9500

44 0101100 1.5000 108 1101100 3.0000

45 0101101 1.5250 109 1101101 3.0500

46 0101110 1.5500 110 1101110 3.1000

47 0101111 1.5750 111 1101111 3.1500

48 0110000 1.6000 112 1110000 3.2000

49 0110001 1.6250 113 1110001 3.2500

50 0110010 1.6500 114 1110010 3.3000

51 0110011 1.6750 115 1110011 Reserved

52 0110100 1.7000 116 1110100 Reserved

53 0110101 1.7250 117 1110101 Reserved

54 0110110 1.7500 118 1110110 Reserved

55 0110111 1.7750 119 1110111 Reserved

56 0111000 1.8000 120 1111000 Reserved

57 0111001 1.8250 121 1111001 Reserved

58 0111010 1.8500 122 1111010 Reserved

59 0111011 1.8750 123 1111011 Reserved

60 0111100 1.9000 124 1111100 Reserved

61 0111101 1.9250 125 1111101 Reserved

62 0111110 1.9500 126 1111110 Reserved

63 0111111 1.9750 127 1111111 Reserved

Notes
53. For voltages less than 2.0 V, only use set points 0 to 63.

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Table 66 provides a list of registers used to configure and operate SW3A/B. A detailed description on each of these register is provided
on Tables 67 through Table 76.

Table 66. SW3AB register summary

Register Address Output

SW3AVOLT 0x3C SW3A output voltage set point on normal operation

SW3ASTBY 0x3D SW3A output voltage set point on standby

SW3AOFF 0x3E SW3A output voltage set point on sleep

SW3AMODE 0x3F SW3A switching mode selector register

SW3ACONF 0x40 SW3A DVS, phase, frequency and ILIM configuration

SW3BVOLT 0x43 SW3B output voltage set point on normal operation

SW3BSTBY 0x44 SW3B output voltage set point on standby

SW3BOFF 0x45 SW3B output voltage set point on sleep

SW3BMODE 0x46 SW3B switching mode selector register

SW3BCONF 0x47 SW3B DVS, phase, frequency and ILIM configuration

Table 67. Register SW3AVOLT - ADDR 0x3C

Name Bit # R/W Default Description

Sets the SW3A output voltage (independent) or

SW3A/B output voltage (single/dual phase),
SW3A 5:0 R/W 0x00
during normal operation mode. See Table 65 for
all possible configurations.

Sets the operating output voltage range for SW3A

(independent) or SW3A/B (single/dual phase).
SW3A 6 R 0x00
Set during OTP or TBB configuration only. See
Table 65 for all possible configurations.

UNUSED 7 – 0x00 unused

Table 68. Register SW3ASTBY - ADDR 0x3D

Name Bit # R/W Default Description

Sets the SW3A output voltage (independent) or

SW3A/B output voltage (single/dual phase),
SW3ASTBY 5:0 R/W 0x00
during standby mode. See Table 65 for all
possible configurations.

Sets the operating output voltage range for SW3A

(independent) or SW3A/B (single/dual phase) on
standby mode. This bit inherits the value
SW3ASTBY 6 R 0x00
configured on bit SW3A[6] during OTP or TBB
configuration. See Table 65 for all possible
configurations.

UNUSED 7 – 0x00 unused

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Table 69. Register SW3AOFF - ADDR 0x3E

Name Bit # R/W Default Description

Sets the SW3A output voltage (independent) or

SW3A/B output voltage (Single/Dual phase),
SW3AOFF 5:0 R/W 0x00
during Sleep mode. See Table 65 for all possible
configurations.

Sets the operating output voltage range for SW3A

(independent) or SW3A/B (single/dual phase) on
SW3AOFF 6 R 0x00 sleep mode. This bit inherits the value configured
on bit SW3A[6] during OTP or TBB configuration.
See Table 65 for all possible configurations.

UNUSED 7 – 0x00 unused

Table 70. Register SW3AMODE - ADDR 0x3F

Name Bit # R/W Default Description

Sets the SW3A (independent) or SW3A/B (single/

SW3AMODE 3:0 R/W 0x08 dual phase) switching operation mode.
See Table 30 for all possible configurations.

UNUSED 4 – 0x00 unused

Set status of SW3A (independent) or SW3A/B

(single/dual phase) when in sleep mode.
SW3AOMODE 5 R/W 0x00
• 0 = OFF
• 1 = PFM

UNUSED 7:6 – 0x00 unused

Table 71. Register SW3ACONF - ADDR 0x40

Name Bit # R/W Default Description

SW3A current limit level selection

SW3AILIM 0 R/W 0x00 • 0 = High level current limit
• 1 = Low level current limit

UNUSED 1 R/W 0x00 unused

SW3A switching frequency selector. See

SW3AFREQ 3:2 R/W 0x00
Table 38.

SW3APHASE 5:4 R/W 0x00 SW3A phase clock selection. See Table 36.

SW3ADVSSPEED 7:6 R/W 0x00 SW3A DVS speed selection. See Table 35.

Table 72. Register SW3BVOLT - ADDR 0x43

Name Bit # R/W Default Description

Sets the SW3B output voltage (independent)

SW3B 5:0 R/W 0x00 during normal operation mode. See Table 65 for
all possible configurations.

Sets the operating output voltage range for SW3B

(independent). Set during OTP or TBB
SW3B 6 R 0x00
configuration only. See Table 65 for all possible
configurations.

UNUSED 7 – 0x00 unused

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Table 73. Register SW3BSTBY - ADDR 0x44

Name Bit # R/W Default Description

Sets the SW3B output voltage (independent)

SW3BSTBY 5:0 R/W 0x00 during standby mode. See Table 65 for all
possible configurations.

Sets the operating output voltage range for SW3B

(Independent) on standby mode. This bit inherits
SW3BSTBY 6 R 0x00 the value configured on bit SW3B[6] during OTP
or TBB configuration. See Table 65 for all
possible configurations.

UNUSED 7 – 0x00 unused

Table 74. Register SW3BOFF - ADDR 0x45

Name Bit # R/W Default Description

Sets the SW3B output voltage (independent)

SW3BOFF 5:0 R/W 0x00 during sleep mode. See Table 65 for all possible
configurations.
Sets the operating output voltage range for SW3B
(independent) on sleep mode. This bit inherits the
SW3BOFF 6 R 0x00 value configured on bit SW3B[6] during OTP or
TBB configuration. See Table 65 for all possible
configurations.
UNUSED 7 – 0x00 unused

Table 75. Register SW3BMODE - ADDR 0x46

Name Bit # R/W Default Description

Sets the SW3B (independent) switching

SW3BMODE 3:0 R/W 0x08 operation mode. See Table 30 for all possible
configurations.
UNUSED 4 – 0x00 unused
Set status of SW3B (independent) when in sleep
mode.
SW3BOMODE 5 R/W 0x00
• 0 = OFF
• 1 = PFM
UNUSED 7:6 – 0x00 unused

Table 76. Register SW3BCONF - ADDR 0x47

Name Bit # R/W Default Description

SW3B current limit level selection

SW3BILIM 0 R/W 0x00 • 0 = High level Current limit
• 1 = Low level Current limit
UNUSED 1 R/W 0x00 Unused
SW3BFREQ 3:2 R/W 0x00 SW3B switching frequency selector. See Table 38.
SW3BPHASE 5:4 R/W 0x00 SW3B phase clock selection. See Table 36.
SW3BDVSSPEED 7:6 R/W 0x00 SW3B DVS speed selection. See Table 35.

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6.4.4.4.9 SW3A/B external components

Table 77. SW3A/B external component requirements

Mode
Components Description SW3A/B single SW3A/B dual SW3A independent
phase phase SW3B independent

CINSW3A(54) SW3A input capacitor 4.7 μF 4.7 μF 4.7 μF

CIN3AHF(54) SW3A decoupling input capacitor 0.1 μF 0.1 μF 0.1 μF

CINSW3B(54) SW3B input capacitor 4.7 μF 4.7 μF 4.7 μF

CIN3BHF(54) SW3B decoupling input capacitor 0.1 μF 0.1 μF 0.1 μF

COSW3A(54) SW3A output capacitor 3 x 22 μF 2 x 22 μF 2 x 22 μF

COSW3B(54) SW3B output capacitor – 2 x 22 μF 2 x 22 μF

LSW3A SW3A inductor 1.0 μH 1.0 μH 1.0 μH

LSW3B SW3B inductor – 1.0 μH 1.0 μH

Notes
54. Use X5R or X7R capacitors.

6.4.4.4.10 SW3A/B specifications

Table 78. SW3A/B electrical characteristics

All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA,
SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single/dual phase and independent mode unless,
otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111],
and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

Switch mode supply SW3a/B
(55)
VINSW3x Operating input voltage 2.8 – 4.5 V
VSW3x Nominal output voltage - Table 65 - V
Output voltage accuracy
• PWM, APS 2.8 V < VIN < 4.5 V, 0 < ISW3x < ISW3xMAX
• 0.625 V < VSW3x < 0.85 V -25 – 25
• 0.875 V < VSW3x < 1.975 V -3.0% – 3.0%
• 2.0 V < VSW3x < 3.3 V -6.0% – 6.0%
mV
VSW3xACC •
%
• PFM , steady state (2.8 V < VIN < 4.5 V, 0 < ISW3x < 50 mA)
• 0.625 V < VSW3x < 0.675 V -65 – 65
• 0.7 V < VSW3x < 0.85 V -45 – 45
• 0.875 V < VSW3x < 1.975 V -3.0% – 3.0%
• 2.0 V < VSW3x < 3.3 V -3.0% – 3.0%

Rated output load current

• 2.8 V < VIN < 4.5 V, 0.625 V < VSW3x < 3.3 V (56)
ISW3x mA
• PWM, APS mode single/dual phase – – 2500
• PWM, APS mode independent (per phase) – – 1250

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Table 78. SW3A/B electrical characteristics (continued)

All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA,
SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single/dual phase and independent mode unless,
otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111],
and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

Switch mode supply SW3a/B (continued)
Current limiter peak current detection
• Single phase (current through inductor)
• SW3xILIM = 0 3.5 5.0 6.5
• SW3xILIM = 1 2.7 3.8 4.9
ISW3xLIM A
• Independent mode or dual phase (current through inductor per
phase)
• SW3xILIM = 0 1.8 2.5 3.3
• SW3xILIM = 1 1.3 1.9 2.5
Start-up overshoot
VSW3xOSH • ISW3x = 0.0 mA – – 66 mV
• DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V
Turn-on time
• Enable to 90% of end value
tONSW3x – – 500 µs
• ISW3x = 0 mA
• DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V
Switching frequency
• SW3xFREQ[1:0] = 00 – 1.0 –
fSW3x MHz
• SW3xFREQ[1:0] = 01 – 2.0 –
• SW3xFREQ[1:0] = 10 – 4.0 –
Efficiency (single phase)
• fSW3 = 2.0 MHz, LSW3x 1.0 μH
• PFM, 1.5 V, 1.0 mA – 84 –
• PFM, 1.5 V, 50 mA – 85 –
ηSW3AB %
• APS, PWM 1.5 V, 500 mA – 85 –
• APS, PWM 1.5 V, 750 mA – 84 –
• APS, PWM 1.5 V, 1250 mA – 80 –
• APS, PWM 1.5 V, 2500 mA – 74 –

ΔVSW3x Output ripple – 10 – mV

VSW3xLIR Line regulation (APS, PWM) – – 20 mV
VSW3xLOR DC load regulation (APS, PWM) – – 20 mV
Transient load regulation
• Transient load = 0.0 mA to ISW3x/2, di/dt = 100 mA/μs
VSW3xLOTR mV
• Overshoot – – 50
• Undershoot – – 50

Quiescent current
• PFM mode (single/dual phase) – 22 –
• APS mode (single/dual phase) – 300 –
ISW3xQ µA
• PFM mode (independent mode) – 50 –
• APS mode (SW3A independent mode) – 250 –
• APS mode (SW3B independent mode) – 150 –
SW3A P-MOSFET RDS(on)
RONSW3AP – mΩ
• at VIN = VINSW3A = 3.3 V 215 245
SW3A N-MOSFET RDS(on)
RONSW3AN – mΩ
• at VIN = VINSW3A = 3.3 V 258 326

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68 NXP Semiconductors
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Table 78. SW3A/B electrical characteristics (continued)

All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA,
SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single/dual phase and independent mode unless,
otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111],
and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

Switch Mode Supply SW3a/B (Continued)
SW3A P-MOSFET leakage current
ISW3APQ – – 7.5 µA
• VIN = VINSW3A = 4.5 V
SW3A N-MOSFET leakage current
ISW3ANQ – – 2.5 µA
• VIN = VINSW3A = 4.5 V
SW3B P-MOSFET RDS(on)
RONSW3BP – mΩ
• at VIN = VINSW3B = 3.3 V 215 245
SW3B N-MOSFET RDS(on)
RONSW3BN – mΩ
• at VIN = VINSW3B = 3.3 V 258 326
SW3B P-MOSFET leakage current
ISW3BPQ – – 7.5 µA
• VIN = VINSW3B = 4.5 V
SW3B N-MOSFET leakage current
ISW3BPQ – – 2.5 µA
• VIN = VINSW3B = 4.5 V
RSW3xDIS Discharge resistance – 600 – Ω
Notes
55. When output is set to > 2.6 V the output follows the input down when VIN gets near 2.8 V.
56. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation:
(VINSW3x - VSW3x) = ISW3x* (DCR of inductor +RONSW3xP + PCB trace resistance).

100 100
90 90
80 80
Efficiency (%)
Efficiency (%)

) 70 ) 70
%
( %
(
y 60 y 60
c c
n 50 n 50
e
i e
i
c
if 40 c
if 40
f f
E 30 E 30
PFM APS
20 20
10 10 PWM
0 0
0.1 1 10 100 1000 10 100 1000 10000
Load Current (mA) Load Current (mA)

Figure 24. SW3AB efficiency waveforms: VIN = 4.2 V; VOUT = 1.5 V; consumer version

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NXP Semiconductors 69
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

100 100
90 90
80 80
Efficiency (%)

Efficiency (%)
) 70 ) 70
(% %
(
y 60 y 60
c c
n 50 n 50
e
i e
i
c c
fif 40 if 40
f
E 30 E 30
20 PFM APS
20
10 10 PWM
0 0
0.1 1 10 100 1000 10 100 1000 10000
Load Current (mA) Load Current (mA)

Figure 25. SW3AB efficiency waveforms: VIN = 4.2 V; VOUT = 1.5 V; extended industrial version

6.4.4.5 SW4
SW4 is a 1.0 A rated single phase buck regulator capable of operating in two modes. In its default mode, it operates as a normal buck
regulator with a programmable output between 0.400 V and 3.300 V. It is capable of operating in the three available switching modes:
PFM, APS, and PWM, described on Table 30 and configured by the SW4MODE[3:0] bits, as shown in Table 31.
If the system requires DDR memory termination, SW4 can be used in its VTT mode. In the VTT mode, its reference voltage tracks the
output voltage of SW3A, scaled by 0.5. Furthermore, when in VTT mode, only the PWM switching mode is allowed. The VTT mode can
be configured by use of VTT bit in the OTP_SW4_CONFIG register.
Figure 26 shows the block diagram and the external component connections for the SW4 regulator.

VIN
SW4IN SW4MODE
ISENSE
CINSW4

SW4 Controller
SW4LX
Driver
LSW4
COSW4 SW4FAULT
EP
I2C
Interface

Internal I2C
Compensation Z2
SW4FB
Z1
VREF
EA
DAC

Figure 26. SW4 block diagram

6.4.4.5.1 SW4 setup and control registers

To set the SW4 in regulator or VTT mode, bit VTT of the register OTP_SW4_CONF register in Table 137. Extended page 1, page 111, is
programmed during OTP or TBB configuration; setting bit VTT to “1” enables SW4 to operate in VTT mode and “0” in regulator mode. See
6.1.2 One time programmability (OTP), page 21 for detailed information on OTP configuration.
In regulator mode, the SW4 output voltage is programmable from 0.400 V to 3.300 V; however, bit SW4[6] in the SW4VOLT register is
read-only during normal operation. Its value is determined by the default configuration, or may be changed by using the OTP registers.
Once SW4[6] is set to “0”, the output is limited to the lower output voltages, from 0.400 V to 1.975 V with 25 mV increments, as determined
by the SW4[5:0] bits. Likewise, once the SW4[6] bit is set to "1", the output voltage is limited to the higher output voltage range from 0.800 V
to 3.300 V with 50 mV increments, as determined by the SW4[5:0] bits.
To optimize the performance of the regulator, it is recommended only voltages from 2.000 V to 3.300 V be used in the high range and the
lower range be used for voltages from 0.400 V to 1.975 V.

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The output voltage set point is independently programmed for normal, standby, and sleep mode by setting the SW4[5:0], SW4STBY[5:0],
and SW4OFF[5:0] bits, respectively. However, the initial state of the SW4[6] bit is copied into bits SW4STBY[6], and SW4OFF[6] bits, so
the output voltage range remains the same on all three operating modes. Table 79 shows the output voltage coding valid for SW4.
Note: Voltage set points of 0.6 V and below are not supported, except in the VTT mode.

Table 79. SW4 output voltage configuration

Low output voltage range(57) High output voltage range

Set point SW4[6:0] SW4 output Set point SW4[6:0] SW4 output

0 0000000 0.4000 64 1000000 0.8000

1 0000001 0.4250 65 1000001 0.8500

2 0000010 0.4500 66 1000010 0.9000

3 0000011 0.4750 67 1000011 0.9500

4 0000100 0.5000 68 1000100 1.0000

5 0000101 0.5250 69 1000101 1.0500

6 0000110 0.5500 70 1000110 1.1000

7 0000111 0.5750 71 1000111 1.1500

8 0001000 0.6000 72 1001000 1.2000

9 0001001 0.6250 73 1001001 1.2500

10 0001010 0.6500 74 1001010 1.3000

11 0001011 0.6750 75 1001011 1.3500

12 0001100 0.7000 76 1001100 1.4000

13 0001101 0.7250 77 1001101 1.4500

14 0001110 0.7500 78 1001110 1.5000

15 0001111 0.7750 79 1001111 1.5500

16 0010000 0.8000 80 1010000 1.6000

17 0010001 0.8250 81 1010001 1.6500

18 0010010 0.8500 82 1010010 1.7000

19 0010011 0.8750 83 1010011 1.7500

20 0010100 0.9000 84 1010100 1.8000

21 0010101 0.9250 85 1010101 1.8500

22 0010110 0.9500 86 1010110 1.9000

23 0010111 0.9750 87 1010111 1.9500

24 0011000 1.0000 88 1011000 2.0000

25 0011001 1.0250 89 1011001 2.0500

26 0011010 1.0500 90 1011010 2.1000

27 0011011 1.0750 91 1011011 2.1500

28 0011100 1.1000 92 1011100 2.2000

29 0011101 1.1250 93 1011101 2.2500

30 0011110 1.1500 94 1011110 2.3000

31 0011111 1.1750 95 1011111 2.3500

32 0100000 1.2000 96 1100000 2.4000

33 0100001 1.2250 97 1100001 2.4500

34 0100010 1.2500 98 1100010 2.5000

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Table 79. SW4 output voltage configuration (continued)

Low output voltage range(57) High output voltage range

Set point SW4[6:0] SW4 output Set point SW4[6:0] SW4 output

35 0100011 1.2750 99 1100011 2.5500

36 0100100 1.3000 100 1100100 2.6000

37 0100101 1.3250 101 1100101 2.6500

38 0100110 1.3500 102 1100110 2.7000

39 0100111 1.3750 103 1100111 2.7500

40 0101000 1.4000 104 1101000 2.8000

41 0101001 1.4250 105 1101001 2.8500

42 0101010 1.4500 106 1101010 2.9000

43 0101011 1.4750 107 1101011 2.9500

44 0101100 1.5000 108 1101100 3.0000

45 0101101 1.5250 109 1101101 3.0500

46 0101110 1.5500 110 1101110 3.1000

47 0101111 1.5750 111 1101111 3.1500

48 0110000 1.6000 112 1110000 3.2000

49 0110001 1.6250 113 1110001 3.2500

50 0110010 1.6500 114 1110010 3.3000

51 0110011 1.6750 115 1110011 Reserved

52 0110100 1.7000 116 1110100 Reserved

53 0110101 1.7250 117 1110101 Reserved

54 0110110 1.7500 118 1110110 Reserved

55 0110111 1.7750 119 1110111 Reserved

56 0111000 1.8000 120 1111000 Reserved

57 0111001 1.8250 121 1111001 Reserved

58 0111010 1.8500 122 1111010 Reserved

59 0111011 1.8750 123 1111011 Reserved

60 0111100 1.9000 124 1111100 Reserved

61 0111101 1.9250 125 1111101 Reserved

62 0111110 1.9500 126 1111110 Reserved

63 0111111 1.9750 127 1111111 Reserved

Notes
57. For voltages less than 2.0 V, only use set points 0 to 63.

PF0100

72 NXP Semiconductors
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Full setup and control of SW4 is done through the I2C registers listed on Table 80, and a detailed description of each one of the registers
is provided in Tables 81 to Table 85.

Table 80. SW4 register summary

Register Address Description

SW4VOLT 0x4A Output voltage set point on normal operation

SW4STBY 0x4B Output voltage set point on standby

SW4OFF 0x4C Output voltage set point on sleep

SW4MODE 0x4D Switching mode selector register

SW4CONF 0x4E DVS, phase, frequency and ILIM configuration

Table 81. Register SW4VOLT - ADDR 0x4A

Name Bit # R/W Default Description

Sets the SW4 output voltage during normal

SW4 5:0 R/W 0x00 operation mode. See Table 79 for all possible
configurations.

Sets the operating output voltage range for SW4.

SW4 6 R 0x00 Set during OTP or TBB configuration only. See
Table 79 for all possible configurations.

UNUSED 7 – 0x00 unused

Table 82. Register SW4STBY - ADDR 0x4B

Name Bit # R/W Default Description

Sets the SW4 output voltage during standby

SW4STBY 5:0 R/W 0x00 mode. See Table 79 for all possible
configurations.

Sets the operating output voltage range for SW4

on standby mode. This bit inherits the value
SW4STBY 6 R 0x00 configured on bit SW4[6] during OTP or TBB
configuration. See Table 79 for all possible
configurations.

UNUSED 7 – 0x00 unused

Table 83. Register SW4OFF - ADDR 0x4C

Name Bit # R/W Default Description

Sets the SW4 output voltage during sleep mode.

SW4OFF 5:0 R/W 0x00
See Table 79 for all possible configurations.

Sets the operating output voltage range for SW4

on sleep mode. This bit inherits the value
SW4OFF 6 R 0x00 configured on bit SW4[6] during OTP or TBB
configuration. See Table 79 for all possible
configurations.
UNUSED 7 – 0x00 unused

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Table 84. Register SW4MODE - ADDR 0x4D

Name Bit # R/W Default Description

Sets the SW4 switching operation mode.

SW4MODE 3:0 R/W 0x08
See Table 30 for all possible configurations.

UNUSED 4 – 0x00 unused

Set status of SW4 when in sleep mode

SW4OMODE 5 R/W 0x00 • 0 = OFF
• 1 = PFM

UNUSED 7:6 – 0x00 unused

Table 85. Register SW4CONF - ADDR 0x4E

Name Bit # R/W Default Description

SW4 current limit level selection

SW4ILIM 0 R/W 0x00 • 0 = High level current limit
• 1 = Low level current limit

UNUSED 1 R/W 0x00 unused

SW4FREQ 3:2 R/W 0x00 SW4 switching frequency selector. See Table 38.

SW4PHASE 5:4 R/W 0x00 SW4 phase clock selection. See Table 36.
SW4DVSSPEED 7:6 R/W 0x00 SW4 DVS speed selection. See Table 35.

6.4.4.5.2 SW4 external components

Table 86. SW4 external component requirements

Components Description Values

CINSW4(58) SW4 input capacitor 4.7 μF

(58)
CIN4HF SW4 decoupling input capacitor 0.1 μF
(58)
COSW4 SW4 output capacitor 3 x 22 μF

LSW4 SW4 inductor 1.0 μH

Notes
58. Use X5R or X7R capacitors

PF0100

74 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.4.4.5.3 SW4 specifications

Table 87. SW4 electrical characteristics

All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA,
SW4_PWRSTG[2:0] = [101], typical external component values, fSW4 = 2.0 MHz, single/dual phase and independent mode unless,
otherwise noted. Typical values are characterized at VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, SW4_PWRSTG[2:0] = [101],
and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

Switch mode supply SW4

(59)
VINSW4 Operating input voltage 2.8 – 4.5 V

Nominal output voltage

VSW4 • Normal operation – Table 79 – V
• VTT mode – VSW3AFB/2 –

Output voltage accuracy

• PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 1.0 A
• 0.625 V < VSW4 < 0.85 V -25 – 25 mV
• 0.875 V < VSW4 < 1.975 V -3.0 – 3.0 %
• 2.0 V < VSW4 < 3.3 V -6.0 – 6.0 %
VSW4ACC
• PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 50 mA
• 0.625 V < VSW4 < 0.675 V -65 – 65 mV
• 0.7 V < VSW4 < 0.85 V -45 – 45 mV
• 0.875 V < VSW4 < 1.975 V -3.0 – 3.0 %
• 2.0 V < VSW4 < 3.3 V -3.0 – 3.0 %
• VTT Mode , 2.8 V < VIN < 4.5 V, 0 < ISW4 < 1.0 A -40 – 40 mV

Rated output load current (60)

ISW4 – – 1000 mA
• 2.8 V < VIN < 4.5 V, 0.625 V < VSW4 < 3.3 V

Current limiter peak current detection

Current through inductor
ISW4LIM A
• SW4ILIM = 0 1.4 2.0 3.0
• SW4ILIM = 1 1.0 1.5 2.4
Start-up overshoot
VSW4OSH • ISW4 = 0.0 mA – – 66 mV
• DVS clk = 25 mV/4 μs, VIN = VINSW4 = 4.5 V

Turn-on time
• Enable to 90% of end value
tONSW4 – – 500 µs
• ISW4 = 0.0 mA
• DVS clk = 25 mV/4 μs, VIN = VINSW4 = 4.5 V

Switching frequency
• SW4FREQ[1:0] = 00 – 1.0 –
fSW4 MHz
• SW4FREQ[1:0] = 01 – 2.0 –
• SW4FREQ[1:0] = 10 – 4.0 –

Efficiency
• fSW4 = 2.0 MHz, LSW4 = 1.0 μH
• PFM, 1.8 V, 1.0 mA – 81 –
• PFM, 1.8 V, 50 mA – 78 –
• APS, PWM 1.8 V, 200 mA – 87 –
ηSW4 • APS, PWM 1.8 V, 500 mA – 88 – %
• APS, PWM 1.8 V, 1000 mA – 83 –

• PWM 0.75 V, 200 mA – 78 –

• PWM 0.75 V, 500 mA – 76 –
• PWM 0.75 V, 1000 mA – 66 –

ΔVSW4 Output ripple – 10 – mV

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Table 87. SW4 electrical characteristics (continued)

All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA,
SW4_PWRSTG[2:0] = [101], typical external component values, fSW4 = 2.0 MHz, single/dual phase and independent mode unless,
otherwise noted. Typical values are characterized at VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, SW4_PWRSTG[2:0] = [101],
and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

Switch mode supply SW4 (continued)

VSW4LIR Line regulation (APS, PWM) – – 20 mV

VSW4LOR DC load regulation (APS, PWM) – – 20 mV

Transient load regulation

• Transient load = 0.0 mA to 500 mA, di/dt = 100 mA/μs
VSW4LOTR mV
• Overshoot – – 50
• Undershoot – – 50

Quiescent current
ISW4Q • PFM mode – 22 – µA
• APS mode – 145 –

SW4 P-MOSFET RDS(on)

RONSW4P – 236 274 mΩ
• at VIN = VINSW4 = 3.3 V

SW4 N-MOSFET RDS(on)

RONSW4N – 293 378 mΩ
• at VIN = VINSW4 = 3.3 V
SW4 P-MOSFET leakage current
ISW4PQ – – 6.0 µA
• VIN = VINSW4 = 4.5 V

SW4 N-MOSFET leakage current

ISW4NQ – – 2.0 µA
• VIN = VINSW4 = 4.5 V

RSW4DIS Discharge resistance – 600 – Ω

Notes
59. When output is set to > 2.6 V the output follows the input down when VIN gets near 2.8 V.
60. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation:
(VINSW4 - VSW4) = ISW4* (DCR of inductor +RONSW4P + PCB trace resistance).

90 100
80 90
70 80
Efficiency (%)
Efficiency (%)

) ) 70
( 60
% %
(
y 50 y 60
c c
n n 50
e
i 40 e
i
ic
ff 30 ic
ff 40
E E 30
20 PFM APS
20
10 10 PWM
0 0
0.1 1 10 100 1000 10 100 1000 10000
Load Current (mA) Load Current (mA)

Figure 27. SW4 efficiency waveforms: VIN = 4.2 V; VOUT = 1.8 V; consumer version

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90 100
80 90
70 80

Efficiency (%)
Efficiency (%)

) ) 70
( 60
% %
(
y y 60
c 50 c
n n 50
e
i 40 e
i
ic
ff ic
ff 40 APS
E 30 E 30
20 PFM PWM
20
10 10
0 0
0.1 1 10 100 1000 10 100 1000 10000
Load Current (mA) Load Current (mA)

Figure 28. SW4 efficiency waveforms: VIN = 4.2 V; VOUT = 1.8 V; extended industrial version

6.4.5 Boost regulator

SWBST is a boost regulator with a programmable output from 5.0 V to 5.15 V. SWBST can supply the VUSB regulator for the USB PHY
in OTG mode, as well as the VBUS voltage. Note that the parasitic leakage path for a boost regulator causes the SWBSTOUT and
SWBSTFB voltage to be a Schottky drop below the input voltage whenever SWBST is disabled. The switching NMOS transistor is
integrated on-chip. Figure 29 shows the block diagram and component connection for the boost regulator.

VIN

CINBST SWBSTIN
LBST

DBST SWBSTMODE
VOBST
SWBSTLX
Driver

OC Controller SWBSTFAULT I2C

EP RSENSE
Interface

VREFSC
SC
VREFUV
UV

SWBSTFB
COSWBST Internal
Compensation Z2

Z1
EA

VREF

Figure 29. Boost regulator architecture

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6.4.5.1 SWBST setup and control

Boost regulator control is done through a single register SWBSTCTL described in Table 88. SWBST is included in the power-up sequence
if its OTP power-up timing bits, SWBST_SEQ[4:0], are not all zeros.

Table 88. Register SWBSTCTL - ADDR 0x66

Name Bit # R/W Default Description

Set the output voltage for SWBST

• 00 = 5.000 V
SWBST1VOLT 1:0 R/W 0x00 • 01 = 5.050 V
• 10 = 5.100 V
• 11 = 5.150 V

Set the Switching mode on normal operation

• 00 = OFF
SWBST1MODE 3:2 R 0x02 • 01 = PFM
• 10 = Auto (Default)(61)
• 11 = APS

UNUSED 4 – 0x00 unused

Set the switching mode on standby

• 00 = OFF
SWBST1STBYMODE 6:5 R/W 0x02 • 01 = PFM
• 10 = Auto (Default)(61)
• 11 = APS

UNUSED 7 – 0x00 unused

Notes
61. In auto mode, the controller automatically switches between PFM and APS modes depending on the load current.
The SWBST regulator starts up by default in the auto mode if SWBST is part of the startup sequence.

6.4.5.2 SWBST external components

Table 89. SWBST external component requirements

Components Description Values

CINBST(62) SWBST input capacitor 10 μF

(62)
CINBSTHF SWBST decoupling input capacitor 0.1 μF
(62)
COBST SWBST output capacitor 2 x 22 μF
LSBST SWBST inductor 2.2 μH

DBST SWBST boost diode 1.0 A, 20 V Schottky

Notes
62. Use X5R or X7R capacitors.

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6.4.5.3 SWBST specifications

Table 90. SWBST Electrical Specifications
All parameters are specified at TMIN to TMAX (See Table 3), VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, typical external
component values, fSWBST = 2.0 MHz, otherwise noted. Typical values are characterized at VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V,
ISWBST = 100 mA, and 25 °C, unless otherwise noted.

Symbol Parameters Min. Typ. Max. Units Notes

Switch mode supply SWBST
VINSWBST Input voltage range 2.8 – 4.5 V
VSWBST Nominal output voltage – Table 88 – V
Output voltage accuracy
VSWBSTACC • 2.8 V ≤ VIN ≤ 4.5 V -4.0 – 3.0 %
• 0 < ISWBST < ISWBSTMAX
Output ripple
• 2.8 V ≤ VIN ≤ 4.5 V
ΔVSWBST – – 120 mV Vp-p
• 0 < ISWBST < ISWBSTMAX, excluding reverse recovery of
Schottky diode
DC load regulation
VSWBSTLOR – 0.5 – mV/mA
• 0 < ISWBST < ISWBSTMAX
DC line regulation
VSWBSTLIR – 50 – mV
• 2.8 V ≤ VIN ≤ 4.5 V, ISWBST = ISWBSTMAX
Continuous load current
ISWBST • 2.8 V ≤ VIN ≤ 3.0 V – – 500 mA
• 3.0 V ≤ VIN ≤ 4.5 V – – 600
Quiescent current
ISWBSTQ – 222 289 μA
• Auto
RDSONBST MOSFET on resistance – 206 306 mΩ
(63)
ISWBSTLIM Peak current limit 1400 2200 3200 mA
Start-up overshoot
VSWBSTOSH – – 500 mV
• ISWBST = 0.0 mA
Transient load response
VSWBSTTR • ISWBST from 1.0 mA to 100 mA in 1.0 µs – – 300 mV
• Maximum transient amplitude
Transient load response
VSWBSTTR • ISWBST from 100 mA to 1.0 mA in 1.0 µs – – 300 mV
• Maximum transient amplitude
Transient load response
tSWBSTTR • ISWBST from 1.0 mA to 100 mA in 1.0 µs – – 500 µs
• Time to settle 80% of transient
Transient load response
tSWBSTTR • ISWBST from 100 mA to 1.0 mA in 1.0 µs – – 20 ms
• Time to settle 80% of transient
NMOS Off leakage
ISWBSTHSQ – 1.0 5.0 µA
• SWBSTIN = 4.5 V, SWBSTMODE [1:0] = 00
Turn-on time
tONSWBST – – 2.0 ms
• Enable to 90% of VSWBST, ISWBST = 0.0 mA
fSWBST Switching frequency – 2.0 – MHz
Efficiency
ηSWBST – 86 – %
• ISWBST = ISWBSTMAX
Notes
63. Only in auto mode.

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6.4.6 LDO regulators description

This section describes the LDO regulators provided by the PF0100. All regulators use the main bandgap as reference. Refer to 6.3 Bias
and references block description, page 24 for further information on the internal reference voltages.
A low-power mode is automatically activated by reducing bias currents when the load current is less than I_Lmax/5. However, the lowest
bias currents may be attained by forcing the part into its low-power mode by setting the VGENxLPWR bit. The use of this bit is only
recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded.
When a regulator is disabled, the output is discharged by an internal pull-down. The pull-down is also activated when RESETBMCU is low.

VINx

VINx VREF

_ VGENxEN

+ VGENxLPWR
VGENx VGENx

I2C
Interface
CGENx

VGENx

Discharge

Figure 30. General LDO block diagram

6.4.6.1 Transient response waveforms

Idealized stimulus and response waveforms for transient line and transient load tests are depicted in Figure 31. Note that the transient line
and load response refers to the overshoot, or undershoot only, excluding the DC shift.

IMAX IL = IMAX/10 IL = IMAX

Overshoot

ILOAD
VOUT
IMAX/10
1.0 us 1.0 us Undershoot

Transient Load Stimulus

VOUT Transient Load Response
VINx_FINAL
VINx_INITIAL Overshoot
VINx_INITIAL

VINx VOUT
VINx_FINAL
Undershoot
10 us 10 us
Transient Line Stimulus
VOUT Transient Line Response
Figure 31. Transient waveforms

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6.4.6.2 Short-circuit protection

All general purpose LDOs have short-circuit protection capability. The short-circuit protection (SCP) system includes debounced fault
condition detection, regulator shutdown, and processor interrupt generation, to contain failures and minimize the chance of product
damage. If a short-circuit condition is detected, the LDO is disabled by resetting its VGENxEN bit, while at the same time, an interrupt
VGENxFAULTI is generated to flag the fault to the system processor. The VGENxFAULTI interrupt is maskable through the
VGENxFAULTM mask bit.
The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, the regulators do not automatically disable upon a short-
circuit detection. However, the current limiter continues to limit the output current of the regulator. By default, the REGSCPEN is not set;
therefore, at start-up none of the regulators is disabled if an overloaded condition occurs. A fault interrupt, VGENxFAULTI, is generated
in an overload condition regardless of the state of the REGSCPEN bit. See Table 91 for SCP behavior configuration.

Table 91. Short-circuit behavior

REGSCPEN[0] Short-circuit behavior

0 Current limit

1 Shutdown

6.4.6.3 LDO regulator control

Each LDO is fully controlled through its respective VGENxCTL register. This register enables the user to set the LDO output voltage
according to Table 92 for VGEN1 and VGEN2; and uses the voltage set point on Table 93 for VGEN3 through VGEN6.

Table 92. VGEN1, VGEN2 output voltage configuration

Set point VGENx[3:0] VGENx output (V)

0 0000 0.800

1 0001 0.850

2 0010 0.900

3 0011 0.950

4 0100 1.000

5 0101 1.050

6 0110 1.100

7 0111 1.150

8 1000 1.200

9 1001 1.250

10 1010 1.300

11 1011 1.350

12 1100 1.400

13 1101 1.450

14 1110 1.500

15 1111 1.550

Table 93. VGEN3/ 4/ 5/ 6 output voltage configuration

Set point VGENx[3:0] VGENx output (V)

0 0000 1.80

1 0001 1.90

2 0010 2.00

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Table 93. VGEN3/ 4/ 5/ 6 output voltage configuration (continued)

Set point VGENx[3:0] VGENx output (V)

3 0011 2.10

4 0100 2.20

5 0101 2.30

6 0110 2.40

7 0111 2.50

8 1000 2.60

9 1001 2.70
10 1010 2.80

11 1011 2.90

12 1100 3.00

13 1101 3.10

14 1110 3.20

15 1111 3.30

Besides the output voltage configuration, the LDOs can be enabled or disabled at anytime during normal mode operation, as well as
programmed to stay “ON” or be disabled when the PMIC enters Standby mode. Each regulator has associated I2C bits for this. Table 94
presents a summary of all valid combinations of the control bits on VGENxCTL register and the expected behavior of the LDO output.

Table 94. LDO control

VGENxEN VGENxLPWR VGENxSTBY STANDBY(64) VGENxOUT

0 X X X Off

1 0 0 X On
1 1 0 X Low power

1 X 1 0 On

1 0 1 1 Off
1 1 1 1 Low power

Notes
64. STANDBY refers to a standby event as described earlier.

For more detail information, Table 95 through Table 100 provide a description of all registers necessary to operate all six general purpose
LDO regulators.

Table 95. Register VGEN1CTL - ADDR 0x6C

Name Bit # R/W Default Description

Sets VGEN1 output voltage.

VGEN1 3:0 R/W 0x80
See Table 92 for all possible configurations.
Enables or disables VGEN1 output
VGEN1EN 4 – 0x00 • 0 = OFF
• 1 = ON
Set VGEN1 output state when in standby. Refer
VGEN1STBY 5 R/W 0x00
to Table 94.
Enable low-power mode for VGEN1. Refer to
VGEN1LPWR 6 R/W 0x00
Table 94.
UNUSED 7 – 0x00 unused

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Table 96. Register VGEN2CTL - ADDR 0x6D

Name Bit # R/W Default Description

Sets VGEN2 output voltage.

VGEN2 3:0 R/W 0x80
See Table 92 for all possible configurations.

Enables or disables VGEN2 output

VGEN2EN 4 – 0x00 • 0 = OFF
• 1 = ON

Set VGEN2 output state when in standby. Refer

VGEN2STBY 5 R/W 0x00
to Table 94.

Enable low-power mode for VGEN2. Refer to

VGEN2LPWR 6 R/W 0x00
Table 94.

UNUSED 7 – 0x00 unused

Table 97. Register VGEN3CTL - ADDR 0x6E

Name Bit # R/W Default Description

Sets VGEN3 output voltage.

VGEN3 3:0 R/W 0x80
See Table 93 for all possible configurations.

Enables or disables VGEN3 output

VGEN3EN 4 – 0x00 • 0 = OFF
• 1 = ON

Set VGEN3 output state when in standby. Refer

VGEN3STBY 5 R/W 0x00
to Table 94.

Enable low-power mode for VGEN3. Refer to

VGEN3LPWR 6 R/W 0x00
Table 94.

UNUSED 7 – 0x00 unused

Table 98. Register VGEN4CTL - ADDR 0x6F

Name Bit # R/W Default Description

Sets VGEN4 output voltage.

VGEN4 3:0 R/W 0x80
See Table 93 for all possible configurations.
Enables or disables VGEN4 output
VGEN4EN 4 – 0x00 • 0 = OFF
• 1 = ON
Set VGEN4 output state when in standby. Refer
VGEN4STBY 5 R/W 0x00
to Table 94.
Enable low-power mode for VGEN4. Refer to
VGEN4LPWR 6 R/W 0x00
Table 94.
UNUSED 7 – 0x00 unused

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Table 99. Register VGEN5CTL - ADDR 0x70

Name Bit # R/W Default Description

Sets VGEN5 output voltage.

VGEN5 3:0 R/W 0x80
See Table 93 for all possible configurations.
Enables or disables VGEN5 output
VGEN5EN 4 – 0x00 • 0 = OFF
• 1 = ON
Set VGEN5 output state when in standby. Refer
VGEN5STBY 5 R/W 0x00
to Table 94.
Enable low-power mode for VGEN5. Refer to
VGEN5LPWR 6 R/W 0x00
Table 94.
UNUSED 7 – 0x00 unused

Table 100. Register VGEN6CTL - ADDR 0x71

Name Bit # R/W Default Description

Sets VGEN6 output voltage.

VGEN6 3:0 R/W 0x80
See Table 93 for all possible configurations.

Enables or disables VGEN6 output

VGEN6EN 4 – 0x00 • 0 = OFF
• 1 = ON

Set VGEN6 output state when in standby. Refer

VGEN6STBY 5 R/W 0x00
to Table 94.
Enable low-power mode for VGEN6. Refer to
VGEN6LPWR 6 R/W 0x00
Table 94.

UNUSED 7 – 0x00 unused

6.4.6.4 External components

Table 101 lists the typical component values for the general purpose LDO regulators.

Table 101. LDO external components

Regulator Output capacitor (μF)(65)

VGEN1 2.2
VGEN2 4.7

VGEN3 2.2

VGEN4 4.7

VGEN5 2.2

VGEN6 2.2

Notes
65. Use X5R/X7R ceramic capacitors.

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6.4.6.5 LDO specifications

6.4.6.5.1 VGEN1

Table 102. VGEN1 electrical characteristics

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IN1 = 3.0 V, VGEN1[3:0] = 1111,
IGEN1 = 10 mA, and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

VGEN1

VIN1 Operating input voltage 1.75 – 3.40 V

VGEN1NOM Nominal output voltage – Table 92 – V

IGEN1 Operating load current 0.0 – 100 mA

VGEN1 DC

Output voltage tolerance

• 1.75 V < VIN1 < 3.4 V
VGEN1TOL -3.0 – 3.0 %
• 0.0 mA < IGEN1 < 100 mA
• VGEN1[3:0] = 0000 to 1111

Load regulation
VGEN1LOR • (VGEN1 at IGEN1 = 100 mA) - (VGEN1 at IGEN1 = 0.0 mA) – 0.15 – mV/mA
• For any 1.75 V < VIN1 < 3.4 V

Line regulation
VGEN1LIR • (VGEN1 at VIN1 = 3.4 V) - (VGEN1 at VIN1 = 1.75 V) – 0.30 – mV/mA
• For any 0.0 mA < IGEN1 < 100 mA

Current limit
IGEN1LIM 122 167 200 mA
• IGEN1 when VGEN1 is forced to VGEN1NOM/2

Overcurrent protection threshold

IGEN1OCP • IGEN1 required to cause the SCP function to disable LDO when 115 – 200 mA
REGSCPEN = 1

Quiescent current
IGEN1Q • No load, change in IVIN and IVIN1 – 14 – μA
• When VGEN1 enabled
VGEN1 AC and transient

PSRR
• IGEN1 = 75 mA, 20 Hz to 20 kHz (66)
PSRRVGEN1 dB
• VGEN1[3:0] = 0000 - 1101 50 60 –
• VGEN1[3:0] = 1110, 1111 37 45 –

Output noise density

• VIN1 = 1.75 V, IGEN1 = 75 mA
dBV/
NOISEVGEN1 • 100 Hz – <1.0 kHz – -108 -100
√Hz
• 1.0 kHz – <10 kHz – -118 -108
• 10 kHz – 1.0 MHz – -124 -112

Turn-on slew rate

• 10% to 90% of end value
SLWRVGEN1 • 1.75 V ≤ VIN1 ≤ 3.4 V, IGEN1 = 0.0 mA mV/μs
• VGEN1[3:0] = 0000 to 0111 – – 12.5
• VGEN1[3:0] = 1000 to 1111 – – 16.5

Turn-on time
GEN1tON • Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V 60 – 500 μs
• IGEN1 = 0.0 mA

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Table 102. VGEN1 electrical characteristics (continued)

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IN1 = 3.0 V, VGEN1[3:0] = 1111,
IGEN1 = 10 mA, and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

VGEN1 AC and transient (continued)

Turn-off time
GEN1tOFF • Disable to 10% of initial value, VIN1 = 1.75 V – – 10 ms
• IGEN1 = 0.0 mA

Start-up overshoot
GEN1OSHT – 1.0 2.0 %
• VIN1 = 1.75 V, 3.4 V, IGEN1 = 0.0 mA

Transient load response

• VIN1 = 1.75 V, 3.4 V
VGEN1LOTR • IGEN1 = 10 mA to 100 mA in 1.0 μs. Peak of overshoot or – – 3.0 %
undershoot of VGEN1 with respect to final value
• Refer to Figure 31

Transient line response

• IGEN1 = 75 mA
• VIN1INITIAL = 1.75 V to VIN1FINAL = 2.25 V for
VGEN1LITR VGEN1[3:0] = 0000 to 1101 – 5.0 8.0 mV
• VIN1INITIAL = VGEN1+0.3 V to VIN1FINAL = VGEN1+0.8 V for
VGEN1[3:0] = 1110, 1111
• Refer to Figure 31
Notes
66. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test.

6.4.6.5.2 VGEN2

Table 103. VGEN2 electrical characteristics

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN1 = 3.0 V, VGEN2[3:0] = 1111, IGEN2 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN1 = 3.0 V, VGEN2[3:0] = 1111,
IGEN2 = 10 mA and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

VGEN2

VIN1 Operating input voltage 1.75 – 3.40 V

VGEN2NOM Nominal output voltage – Table 92 – V

IGEN2 Operating load current 0.0 – 250 mA

VGEN2 active mode - DC

Output voltagetolerance
• 1.75 V < VIN1 < 3.4 V
VGEN2TOL -3.0 – 3.0 %
• 0.0 mA < IGEN2 < 250 mA
• VGEN2[3:0] = 0000 to 1111

Load regulation
VGEN2LOR • (VGEN2 at IGEN2 = 250 mA) - (VGEN2 at IGEN2 = 0.0 mA) – 0.05 – mV/mA
• For any 1.75 V < VIN1 < 3.4 V
Line regulation
VGEN2LIR • (VGEN2 at VIN1 = 3.4 V) - (VGEN2 at VIN1 = 1.75 V) – 0.50 – mV/mA
• For any 0.0 mA < IGEN2 < 250 mA

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86 NXP Semiconductors
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Table 103. VGEN2 electrical characteristics

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN1 = 3.0 V, VGEN2[3:0] = 1111, IGEN2 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN1 = 3.0 V, VGEN2[3:0] = 1111,
IGEN2 = 10 mA and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

VGEN2 active mode - DC (continued)

Current limit
• IGEN2 when VGEN2 is forced to VGEN2NOM/2
IGEN2LIM mA
• MMPF0100 333 417 510
• MMPF0100A 305 417 510

Overcurrent protection threshold

• IGEN2 required to cause the SCP function to disable LDO when
IGEN2OCP REGSCPEN = 1 mA
• MMPF0100 300 – 500
• MMPF0100A 290 – 500
Quiescent current
IGEN2Q • No load, change in IVIN and IVIN1 – 16 – μA
• When VGEN2 enabled
VGEN2 AC and transient

PSRR
• IGEN2 = 187.5 mA, 20 Hz to 20 kHz (67)
PSRRVGEN2 dB
• VGEN2[3:0] = 0000 - 1101 50 60 –
• VGEN2[3:0] = 1110, 1111 37 45 –

Output noise density

• VIN1 = 1.75 V, IGEN2 = 187.5 mA
NOISEVGEN2 • 100 Hz – <1.0 kHz – -108 -100 dBV/√Hz
• 1.0 kHz – <10 kHz – -118 -108
• 10 kHz – 1.0 MHz – -124 -112

Turn-on slew rate

• 10% to 90% of end value
SLWRVGEN2 • 1.75 V ≤ VIN1 ≤ 3.4 V, IGEN2 = 0.0 mA mV/μs
• VGEN2[3:0] = 0000 to 0111 – – 12.5
• VGEN2[3:0] = 1000 to 1111 – – 16.5

Turn-on time
GEN2tON • Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V 60 – 500 μs
• IGEN2 = 0.0 mA

Turn-off time
GEN2tOFF • Disable to 10% of initial value, VIN1 = 1.75 V – – 10 ms
• IGEN2 = 0.0 mA

Start-up overshoot
GEN2OSHT – 1.0 2.0 %
• VIN1 = 1.75 V, 3.4 V, IGEN2 = 0.0 mA
Transient load response
• VIN1 = 1.75 V, 3.4 V
• IGEN2 = 25 to 250 mA in 1.0 μs
VGEN2LOTR – – 3.0 %
• Peak of overshoot or undershoot of VGEN2 with respect to final
value
• Refer to Figure 31

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Table 103. VGEN2 electrical characteristics

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN1 = 3.0 V, VGEN2[3:0] = 1111, IGEN2 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN1 = 3.0 V, VGEN2[3:0] = 1111,
IGEN2 = 10 mA and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

VGEN2 AC and transient (continued)

Transient line response

• IGEN2 = 187.5 mA
• VIN1INITIAL = 1.75 V to VIN1FINAL = 2.25 V for
VGEN2LITR VGEN2[3:0] = 0000 to 1101 – 5.0 8.0 mV
• VIN1INITIAL = VGEN2+0.3 V to VIN1FINAL = VGEN2+0.8 V for
VGEN2[3:0] = 1110, 1111
• Refer to Figure 31

Notes
67. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test.

6.4.6.5.3 VGEN3

Table 104. VGEN3 electrical characteristics

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN2 = 3.6 V, VGEN3[3:0] = 1111, IGEN3 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN2 = 3.6 V, VGEN3[3:0] = 1111,
IGEN3 = 10 mA, and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

VGEN3

Operating input voltage

2.8
VIN2 • 1.8 V ≤ VGEN3NOM ≤ 2.5 V – 3.6 V —
VGEN3NO (68)
• 2.6 V ≤ VGEN3NOM ≤ 3.3 V – 3.6
M+ 0.250

VGEN3NOM Nominal output voltage – Table 93 – V

IGEN3 Operating load current 0.0 – 100 mA

VGEN3 DC

Output voltage tolerance

• VIN2MIN < VIN2 < 3.6 V
VGEN3TOL -3.0 – 3.0 %
• 0.0 mA < IGEN3 < 100 mA
• VGEN3[3:0] = 0000 to 1111
Load regulation
VGEN3LOR • (VGEN3 at IGEN3 = 100 mA) - (VGEN3 at IGEN3 = 0.0 mA) – 0.07 – mV/mA
• For any VIN2MIN < VIN2 < 3.6 V

Line regulation
VGEN3LIR • (VGEN3 at VIN2 = 3.6 V) - (VGEN3 at VIN2MIN ) – 0.8 – mV/mA
• For any 0.0 mA < IGEN3 < 100 mA

Current limit
IGEN3LIM 127 167 200 mA
• IGEN3 when VGEN3 is forced to VGEN3NOM/2

Overcurrent protection threshold

IGEN3OCP • IGEN3 required to cause the SCP function to disable LDO when 120 – 200 mA
REGSCPEN = 1

Quiescent current
IGEN3Q • No load, Change in IVIN and IVIN2 – 13 – μA
• When VGEN3 enabled

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Table 104. VGEN3 electrical characteristics (continued)

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN2 = 3.6 V, VGEN3[3:0] = 1111, IGEN3 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN2 = 3.6 V, VGEN3[3:0] = 1111,
IGEN3 = 10 mA, and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

VGEN3 AC and transient

PSRR
• IGEN3 = 75 mA, 20 Hz to 20 kHz (69)
PSRRVGEN3 dB
• VGEN3[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV 35 40 –
• VGEN3[3:0] = 0000 - 1000, VIN2 = VGEN3NOM + 1.0 V 55 60 –

Output noise density

• VIN2 = VIN2MIN, IGEN3 = 75 mA
NOISEVGEN3 • 100 Hz – <1.0 kHz – -114 -102 dBV/√Hz
• 1.0 kHz – <10 kHz – -129 -123
• 10 kHz – 1.0 MHz – -135 -130

Turn-on slew rate

• 10% to 90% of end value
• VIN2MIN ≤ VIN2 ≤ 3.6 V, IGEN3 = 0.0 mA
SLWRVGEN3 • VGEN3[3:0] = 0000 to 0011 – – 22.0 mV/μs
• VGEN3[3:0] = 0100 to 0111 – – 26.5
• VGEN3[3:0] = 1000 to 1011 – – 30.5
• VGEN3[3:0] = 1100 to 1111 – – 34.5

Turn-on time
GEN3tON • Enable to 90% of end value, VIN2 = VIN2MIN, 3.6 V 60 – 500 μs
• IGEN3 = 0.0 mA

Turn-off time
GEN3tOFF • Disable to 10% of initial value, VIN2 = VIN2MIN – – 10 ms
• IGEN3 = 0.0 mA
Start-up overshoot
GEN3OSHT – 1.0 2.0 %
• VIN2 = VIN2MIN, 3.6 V, IGEN3 = 0.0 mA

Transient load response

• VIN2 = VIN2MIN, 3.6 V
VGEN3LOTR • IGEN3 = 10 to 100 mA in 1.0μs – – 3.0 %
• Peak of overshoot or undershoot of VGEN3 with respect to final
value. Refer to Figure 31

Transient line response

• IGEN3 = 75 mA
• VIN2INITIAL = 2.8 V to VIN2FINAL = 3.3 V for GEN3[3:0] = 0000 to
0111
VGEN3LITR • VIN2INITIAL = VGEN3+0.3 V to VIN2FINAL = VGEN3+0.8 V for – 5.0 8.0 mV
VGEN3[3:0] = 1000 to 1010
• VIN2INITIAL = VGEN3+0.25 V to VIN2FINAL = 3.6 V for VGEN3[3:0]
= 1011 to 1111
• Refer to Figure 31

Notes
68. When the LDO output voltage is set above 2.6 V, the minimum allowed input voltage needs to be at least the output voltage plus 0.25 V, for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
69. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VIN2MIN refers to the minimum allowed input voltage for a particular output voltage.

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6.4.6.5.4 VGEN4

Table 105. VGEN4 electrical characteristics

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN2 = 3.6 V, VGEN4[3:0] = 1111, IGEN4 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN2 = 3.6 V, VGEN4[3:0] = 1111,
IGEN4 = 10 mA, and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

VGEN4

Operating input voltage

2.8
VIN2 • 1.8 V ≤ VGEN4NOM ≤ 2.5 V – 3.6 V —
VGEN4NO (70)
• 2.6 V ≤ VGEN4NOM ≤ 3.3 V – 3.6
M+ 0.250

VGEN4NOM Nominal output voltage – Table 93 – V

IGEN4 Operating load current 0.0 – 350 mA

VGEN4 DC

Output voltage tolerance

• VIN2MIN < VIN2 < 3.6 V
VGEN4TOL -3.0 – 3.0 %
• 0.0 mA < IGEN4 < 350 mA
• VGEN4[3:0] = 0000 to 1111

Load regulation
VGEN4LOR • (VGEN4 at IGEN4 = 350 mA) - (VGEN4 at IGEN4 = 0.0 mA ) – 0.07 – mV/mA
• For any VIN2MIN < VIN2 < 3.6 V

Line regulation
VGEN4LIR • (VGEN4 at 3.6 V) - (VGEN4 at VIN2MIN) – 0.80 – mV/mA
• For any 0.0 mA < IGEN4 < 350 mA

Current limit
IGEN4LIM 435 584.5 700 mA
• IGEN4 when VGEN4 is forced to VGEN4NOM/2
Overcurrent protection threshold
IGEN4OCP • IGEN4 required to cause the SCP function to disable LDO when 420 – 700 mA
REGSCPEN = 1

Quiescent current
IGEN4Q • No load, Change in IVIN and IVIN2 – 13 – μA
• When VGEN4 enabled
VGEN4 AC and transient

PSRR
• IGEN4 = 262.5 mA, 20 Hz to 20 kHz (71)
PSRRVGEN4 dB
• VGEN4[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV 35 40 –
• VGEN4[3:0] = 0000 - 1000, VIN2 = VGEN4NOM + 1.0 V 55 60 –

Output noise density

• VIN2 = VIN2MIN, IGEN4 = 262.5 mA
NOISEVGEN4 • 100 Hz – <1.0 kHz – -114 -102 dBV/√Hz
• 1.0 kHz – <10 kHz – -129 -123
• 10 kHz – 1.0 MHz – -135 -130

Turn-on slew rate

• 10% to 90% of end value
• VIN2MIN ≤ VIN2 ≤ 3.6 V, IGEN4 = 0.0 mA
SLWRVGEN4 • VGEN4[3:0] = 0000 to 0011 – – 22.0 mV/μs
• VGEN4[3:0] = 0100 to 0111 – – 26.5
• VGEN4[3:0] = 1000 to 1011 – – 30.5
• VGEN4[3:0] = 1100 to 1111 – – 34.5

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Table 105. VGEN4 electrical characteristics (continued)

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN2 = 3.6 V, VGEN4[3:0] = 1111, IGEN4 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN2 = 3.6 V, VGEN4[3:0] = 1111,
IGEN4 = 10 mA, and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

VGEN4 AC AND tRANSIENT (Continued)

Turn-on time
GEN4tON • Enable to 90% of end value, VIN2 = VIN2MIN, 3.6 V 60 – 500 μs
• IGEN4 = 0.0 mA

Turn-off time
GEN4tOFF • Disable to 10% of initial value, VIN2 = VIN2MIN – – 10 ms
• IGEN4 = 0.0 mA

Start-up overshoot
GEN4OSHT – 1.0 2.0 %
• VIN2 = VIN2MIN, 3.6 V, IGEN4 = 0.0 mA

Transient load response

• VIN2 = VIN2MIN, 3.6 V
VGEN4LOTR • IGEN4 = 35 to 350 mA in 1.0 μs – – 3.0 %
• Peak of overshoot or undershoot of VGEN4 with respect to final
value. Refer to Figure 31

Transient line response

• IGEN4 = 262.5 mA
• VIN2INITIAL = 2.8 V to VIN2FINAL = 3.3 V for VGEN4[3:0] = 0000
to 0111
VGEN4LITR • VIN2INITIAL = VGEN4+0.3 V to VIN2FINAL = VGEN4+0.8 V for – 5.0 8.0 mV
VGEN4[3:0] = 1000 to 1010
• VIN2INITIAL = VGEN4+0.25 V to VIN2FINAL = 3.6 V for VGEN4[3:0]
= 1011 to 1111
• Refer to Figure 31
Notes
70. When the LDO output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
71. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VIN2MIN refers to the minimum allowed input voltage for a particular output voltage.

6.4.6.5.5 VGEN5

Table 106. VGEN5 electrical characteristics

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN3 = 3.6 V, VGEN5[3:0] = 1111, IGEN5 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN3 = 3.6 V, VGEN5[3:0] = 1111,
IGEN5 = 10 mA, and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

VGEN5

Operating input voltage

2.8
VIN3 • 1.8 V ≤ VGEN5NOM ≤ 2.5 V – 4.5 V —
VGEN5NO (72)
• 2.6 V ≤ VGEN5NOM ≤ 3.3 V – 4.5
M+ 0.250

VGEN5NOM Nominal output voltage – Table 93 – V

IGEN5 Operating load current 0.0 – 100 mA

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Table 106. VGEN5 electrical characteristics (continued)

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN3 = 3.6 V, VGEN5[3:0] = 1111, IGEN5 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN3 = 3.6 V, VGEN5[3:0] = 1111,
IGEN5 = 10 mA, and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

VGEN5 active mode – DC

Output voltage tolerance

• VIN3MIN < VIN3 < 4.5 V
VGEN5TOL -3.0 – 3.0 %
• 0.0 mA < IGEN5 < 100 mA
• VGEN5[3:0] = 0000 to 1111

Load regulation
VGEN5LOR • (VGEN5 at IGEN5 = 100 mA) - (VGEN5 at IGEN5 = 0.0 mA) – 0.10 – mV/mA
• For any VIN3MIN < VIN3 < 4.5 mV

Line regulation
VGEN5LIR • (VGEN5 at VIN3 = 4.5 V) - (VGEN5 at VIN3MIN) – 0.50 – mV/mA
• For any 0.0 mA < IGEN5 < 100 mA
Current limit
IGEN5LIM 122 167 200 mA
• IGEN5 when VGEN5 is forced to VGEN5NOM/2

Overcurrent protection threshold

IGEN5OCP • IGEN5 required to cause the SCP function to disable LDO when 120 – 200 mA
REGSCPEN = 1

Quiescent current
IGEN5Q • No load, Change in IVIN and IVIN3 – 13 – μA
• When VGEN5 enabled
VGEN5 AC and transient

PSRR
• IGEN5 = 75 mA, 20 Hz to 20 kHz (73)
PSRRVGEN5 dB
• VGEN5[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV 35 40 –
• VGEN5[3:0] = 0000 - 1111, VIN3 = VGEN5NOM + 1.0 V 52 60 –

Output noise density

• VIN3 = VIN3MIN, IGEN5 = 75 mA
NOISEVGEN5 • 100 Hz – <1.0 kHz – -114 -102 dBV/√Hz
• 1.0 kHz – <10 kHz – -129 -123
• 10 kHz – 1.0 MHz – -135 -130

Turn-on slew rate

• 10% to 90% of end value
• VIN3MIN ≤ VIN3 ≤ 4.5 mV, IGEN5 = 0.0 mA
SLWRVGEN5 • VGEN5[3:0] = 0000 to 0011 – – 22.0 mV/μs
• VGEN5[3:0] = 0100 to 0111 – – 26.5
• VGEN5[3:0] = 1000 to 1011 – – 30.5
• VGEN5[3:0] = 1100 to 1111 – – 34.5

Turn-on time
GEN5tON • Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V 60 – 500 μs
• IGEN5 = 0.0 mA
Turn-off time
GEN5tOFF • Disable to 10% of initial value, VIN3 = VIN3MIN – – 10 ms
• IGEN5 = 0.0 mA

Start-up overshoot
GEN5OSHT – 1.0 2.0 %
• VIN3 = VIN3MIN, 4.5 V, IGEN5 = 0.0 mA

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Table 106. VGEN5 electrical characteristics (continued)

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN3 = 3.6 V, VGEN5[3:0] = 1111, IGEN5 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN3 = 3.6 V, VGEN5[3:0] = 1111,
IGEN5 = 10 mA, and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

VGEN5 active mode – DC (continued)

Transient load response

• VIN3 = VIN3MIN, 4.5 V
• IGEN5 = 10 to 100 mA in 1.0 μs
VGEN5LOTR – – 3.0 %
• Peak of overshoot or undershoot of VGEN5 with respect to final
value.
• Refer to Figure 31

Transient line response

• IGEN5 = 75 mA
• VIN3INITIAL = 2.8 V to VIN3FINAL = 3.3 V for VGEN5[3:0] = 0000 to
VGEN5LITR 0111 - 5.0 8.0 mV
• VIN3INITIAL = VGEN5+0.3 V to VIN3FINAL = VGEN5+0.8 V for
VGEN5[3:0] = 1000 to 1111
• Refer to Figure 31

Notes
72. When the LDO output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
73. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage.

6.4.6.5.6 VGEN6

Table 107. VGEN6 electrical characteristics

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN3 = 3.6 V, VGEN6[3:0] = 1111, IGEN6 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN3 = 3.6 V, VGEN6[3:0] = 1111,
IGEN6 = 10 mA, and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

VGEN6
Operating input voltage 2.8
VIN3 • 1.8 V ≤ VGEN6NOM ≤ 2.5 V VGEN6NO – 4.5 V —
(74)
• 2.6 V ≤ VGEN6NOM ≤ 3.3 V M+ 0.250 – 4.5
VGEN6NOM Nominal output voltage – Table 93 – V
IGEN6 Operating load current 0.0 – 200 mA
VGEN6 DC
Output voltage tolerance
• VIN3MIN < VIN3 < 4.5 V
VGEN6TOL -3.0 – 3.0 %
• 0.0 mA < IGEN6 < 200 mA
• VGEN6[3:0] = 0000 to 1111
Load regulation
VGEN6LOR • (VGEN6 at IGEN6 = 200 mA) - (VGEN6 at IGEN6 = 0.0 mA) – 0.10 – mV/mA
• For any VIN3MIN < VIN3 < 4.5 V
Line regulation
VGEN6LIR • (VGEN6 at VIN3 = 4.5 V) - (VGEN6 at VIN3MIN) – 0.50 – mV/mA
• For any 0.0 mA < IGEN6 < 200 mA
Current limit
• IGEN6 when VGEN6 is forced to VGEN6NOM/2
IGEN6LIM mA
• MMPF0100 232 333 400
• MMPF0100A 232 333 475

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Table 107. VGEN6 electrical characteristics (continued)

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN3 = 3.6 V, VGEN6[3:0] = 1111, IGEN6 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN3 = 3.6 V, VGEN6[3:0] = 1111,
IGEN6 = 10 mA, and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

VGEN6 DC (continued)
Overcurrent protection threshold
• IGEN6 required to cause the SCP function to disable LDO when
IGEN6OCP REGSCPEN = 1 mA
• MMPF0100 220 – 400
• MMPF0100A 220 – 475
Quiescent current
IGEN6Q • No load, Change in IVIN and IVIN3 – 13 – μA
• When VGEN6 enabled
VGEN6 AC and transient
PSRR
• IGEN6 = 150 mA, 20 Hz to 20 kHz (75)
PSRRVGEN6 dB
• VGEN6[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV 35 40 –
• VGEN6[3:0] = 0000 - 1111, VIN3 = VGEN6NOM + 1.0 V 52 60 –

Output noise density

• VIN3 = VIN3MIN, IGEN6 = 150 mA
NOISEVGEN6 • 100 Hz – <1.0 kHz – -114 -102 dBV/√Hz
• 1.0 kHz – <10 kHz – -129 -123
• 10 kHz – 1.0 MHz – -135 -130

Turn-on slew rate

• 10% to 90% of end value
• VIN3MIN ≤ VIN3 ≤ 4.5 V. IGEN6 = 0.0 mA
SLWRVGEN6 • VGEN6[3:0] = 0000 to 0011 – – 22.0 mV/μs
• VGEN6[3:0] = 0100 to 0111 – – 26.5
• VGEN6[3:0] = 1000 to 1011 – – 30.5
• VGEN6[3:0] = 1100 to 1111 – – 34.5

Turn-on time
GEN6tON • Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V 60 – 500 μs
• IGEN6 = 0.0 mA
Turn-off time
GEN6tOFF • Disable to 10% of initial value, VIN3 = VIN3MIN – – 10 ms
• IGEN6 = 0.0 mA
Start-up overshoot
GEN6OSHT – 1.0 2.0 %
• VIN3 = VIN3MIN, 4.5 V, IGEN6 = 0 mA
Transient load response
• VIN3 = VIN3MIN, 4.5 V
VGEN6LOTR • IGEN6 = 20 to 200 mA in 1.0 μs – – 3.0 %
• Peak of overshoot or undershoot of VGEN6 with respect to final
value. Refer to Figure 31

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Table 107. VGEN6 electrical characteristics (continued)

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VIN3 = 3.6 V, VGEN6[3:0] = 1111, IGEN6 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VIN3 = 3.6 V, VGEN6[3:0] = 1111,
IGEN6 = 10 mA, and 25 °C, unless otherwise noted.

Symbol Parameter Min. Typ. Max. Unit Notes

VGEN6 AC and transient (continued)
Transient line response
• IGEN6 = 150 mA
• VIN3INITIAL = 2.8 V to VIN3FINAL = 3.3 V for VGEN6[3:0] = 0000
VGEN6LITR to 0111 – 5.0 8.0 mV
• VIN3INITIAL = VGEN6+0.3 V to VIN3FINAL = VGEN6+0.8 V for
VGEN6[3:0] = 1000 to 1111
• Refer to Figure 31
Notes
74. When the LDO output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
75. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage.

6.4.7 VSNVS LDO/switch

VSNVS powers the low-power, SNVS/RTC domain on the processor. It derives its power from either VIN, or coin cell, and cannot be
disabled. When powered by both, VIN takes precedence when above the appropriate comparator threshold. When powered by VIN,
VSNVS is an LDO capable of supplying seven voltages: 3.0, 1.8, 1.5, 1.3, 1.2, 1.1, and 1.0 V. The bits VSNVSVOLT[2:0] in register
VSNVS_CONTROL determine the output voltage. When powered by coin cell, VSNVS is an LDO capable of supplying 1.8, 1.5, 1.3, 1.2,
1.1, or 1.0 V as shown in Table 108. If the 3.0 V option is chosen with the coin cell, VSNVS tracks the coin cell voltage by means of a
switch, whose maximum resistance is 100 Ω. In this case, the VSNVS voltage is simply the coin cell voltage minus the voltage drop across
the switch, which is 40 mV at a rated maximum load current of 400 μA.
The default setting of the VSNVSVOLT[2:0] is 110, or 3.0 V, unless programmed otherwise in OTP. However, when the coin cell is applied
for the very first time, VSNVS outputs 1.0 V. Only when VIN is applied thereafter does VSNVS transition to its default, or programmed
value if different. Upon subsequent removal of VIN, with the coin cell attached, VSNVS changes configuration from an LDO to a switch for
the “110” setting, and remains as an LDO for the other settings, continuing to output the same voltages as when VIN is applied, providing
certain conditions are met as described in Table 108.

PF0100
VIN
2.25 V (VTL0) -
4.5 V LDO/SWITCH
Input
LICELL Sense/ VREF _

Charger Selector
LDO\ +
VSNVS
Z
Coin Cell
1.8 - 3.3 V

I2C Interface

Figure 32. VSNVS supply switch architecture

Table 108 provides a summary of the VSNVS operation at different input voltage VIN and with or without coin cell connected to the system.

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Table 108. VSNVS modes of operation

VSNVSVOLT[2:0] VIN Mode

110 > VTH1 VIN LDO 3.0 V

110 < VTL1 Coin cell switch

000 – 101 > VTH0 VIN LDO

000 – 101 < VTL0 Coin cell LDO

6.4.7.0.1 VSNVS control

The VSNVS output level is configured through the VSNVSVOLT[2:0]bits on VSNVSCTL register as shown in Table 109.

Table 109. Register VSNVSCTL - ADDR 0x6B

Name Bit # R/W Default Description

Configures VSNVS output voltage.(76)

• 000 = 1.0 V
• 001 = 1.1 V
• 010 = 1.2 V
VSNVSVOLT 2:0 R/W 0x80 • 011 = 1.3 V
• 100 = 1.5 V
• 101 = 1.8 V
• 110 = 3.0 V
• 111 = RSVD

UNUSED 7:3 – 0x00 unused

Notes
76. Only valid when a valid input voltage is present.

6.4.7.0.2 VSNVS external components

Table 110. VSNVS external components

Capacitor Value (μF)

VSNVS 0.47

6.4.7.0.3 VSNVS specifications

Table 111. VSNVS electrical characteristics

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 μA, typical external component values,
unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise
noted.

Symbol Parameter Min Typ Max Unit Notes

VSNVS

Operating Input Voltage

VINSNVS • Valid coin cell range 1.8 – 3.3 V
• Valid VIN 2.25 – 4.5
Operating load current
ISNVS 5.0 – 400 μA
• VINMIN < VIN < VINMAX

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 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 111. VSNVS electrical characteristics (continued)

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 μA, typical external component values,
unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise
noted.

Symbol Parameter Min Typ Max Unit Notes

VSNVS DC, LDO

Output voltage
• 5.0 μA < ISNVS < 400 μA (OFF)
• 3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110 -5.0% 3.0 7.0%
• VTL0/VTH < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101] -8.0% 1.0 - 1.8 7.0%

• 5.0μA < ISNVS < 400 μA (ON)

VSNVS V
• 3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110 -5.0% 3.0 5.0%
• UVDET < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101] -4.0% 1.0 - 1.8 4.0%

• 5.0 μA < ISNVS < 400 μA (Coin Cell mode)

• 2.84 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = 110 VCOIN-0.04 – VCOIN
(77)
• 1.8 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = [000] - [101] -8.0% 1.0 - 1.8 7.0%

Dropout voltage
VSNVSDROP – – 50 mV
• VIN = VCOIN = 2.85 V, VSNVSVOLT[2:0] = 110, ISNVS = 400 μA

Current limit
• MMPF0100
• VIN > VTH1, VSNVSVOLT[2:0] = 110 750 – 5900
• VIN > VTH0, VSNVSVOLT[2:0] = 000 to 101 500 – 5900
ISNVSLIM • VIN < VTL0, VSNVSVOLT[2:0] = 000 to 101 480 – 3600 μA
• MMPF0100A
• VIN > VTH1, VSNVSVOLT[2:0] = 110 1100 – 6750
• VIN > VTH0, VSNVSVOLT[2:0] = 000 to 101 500 – 6750
• VIN < VTL0, VSNVSVOLT[2:0] = 000 to 101 480 – 4500

VIN Threshold (coin cell powered to VIN powered) VIN going high with
VTH0 valid coin cell V
• VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101 2.25 2.40 2.55

VIN threshold (VIN powered to coin cell powered) VIN going low with
VTL0 valid coin cell V
• VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101 2.20 2.35 2.50

VHYST1 VIN threshold hysteresis for VTH1-VTL1 5.0 – – mV

VHYST0 VIN threshold hysteresis for VTH0-VTL0 5.0 – – mV

Output voltage during crossover

• VSNVSVOLT[2:0] = 110
(80)
VSNVSCROSS • VCOIN > 2.9 V 2.7 – – V
• Switch to LDO: VIN > 2.825 V, ISNVS = 100 μA
• LDO to Switch: VIN < 3.05 V, ISNVS = 100 μA
VSNVS AC and transient

Turn-on time (load capacitor, 0.47 μF)

• VIN > UVDET to 90% of VSNVS (78),(79)
tONSNVS – – 24 ms
• VCOIN = 0.0 V, ISNVS = 5.0 μA
• VSNVSVOLT[2:0] = 000 to 110

Start-up overshoot
• VSNVSVOLT[2:0] = 000 to 110
VSNVSOSH – 40 70 mV
• ISNVS = 5.0 μA
• dVIN/dt = 50 mV/μs
Transient line response ISNVS = 75% of ISNVSMAX
– 32 –
VSNVSLITR • 3.2 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110 mV
– 22 –
• 2.45 V < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]

PF0100

NXP Semiconductors 97
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 111. VSNVS electrical characteristics (continued)

All parameters are specified at TMIN to TMAX (See Table 3), VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 μA, typical external component values,
unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise
noted.

Symbol Parameter Min Typ Max Unit Notes

VSNVS AC and transient (continued)

Transient load response

• VSNVSVOLT[2:0] = 110
2.8 – – V
• 3.1 V (UVDETL)< VIN ≤ 4.5 V
• ISNVS = 75 to 750 μA
VSNVSLOTR • VSNVSVOLT[2:0] = 000 to 101
– 1.0 2.0 %
• 2.45 V < VIN ≤ 4.5 V
• VTL0 > VIN, 1.8 V ≤ VCOIN ≤ 3.3 V
• ISNVS = 40 to 400 μA
• Refer to Figure 31
VSNVS DC, switch

Operating input voltage

VINSNVS 1.8 – 3.3 V
• Valid coin cell range

ISNVS Operating load current 5.0 – 400 μA

Internal switch RDS(on)
RDSONSNVS – – 100 Ω
• VCOIN = 2.6 V

VIN threshold (VIN powered to coin cell powered) (80)

VTL1 2.725 2.90 3.00 V
• VSNVSVOLT[2:0] = 110

VIN threshold (coin cell powered to VIN powered)

VTH1 2.775 2.95 3.1 V
• VSNVSVOLT[2:0] = 110

Notes
77. For 1.8 V ISNVS limited to 100 μA for VCOIN < 2.1 V
78. The start-up of VSNVS is not monotonic. It first rises to 1.0 V and then settles to its programmed value within the specified tr1 time.
79. From coin cell insertion to VSNVS =1.0 V, the delay time is typically 400 ms.
80. During crossover from VIN to LICELL, the VSNVS output voltage may drop to 2.7 V before going to the LICELL voltage. Though this is outside
the specified DC voltage level for the VDD_SNVS_IN pin of the i.MX 6, this momentary drop does not cause any malfunction. The i.MX 6’s RTC
continues to operate through the transition, and as a worst case it may switch to the internal RC oscillator for a few clock cycles before switching
back to the external crystal oscillator.

6.4.7.1 Coin cell battery backup

The LICELL pin provides for a connection of a coin cell backup battery or a “super” capacitor. If the voltage at VIN goes below the VIN
threshold (VTL1 and VTL0), contact-bounced, or removed, the coin cell maintained logic is powered by the voltage applied to LICELL. The
supply for internal logic and the VSNVS rail switches over to the LICELL pin when VIN goes below VTL1 or VTL0, even in the absence of
a voltage at the LICELL pin, resulting in clearing of memory and turning off of VSNVS. When system operation below VTL1 is required,
for systems not utilizing a coin cell, connect the LICELL pin to any system voltage between 1.8 V and 3.0 V. A small capacitor should be
placed from LICELL to ground under all circumstances.

6.4.7.1.1 Coin cell charger control

The coin cell charger circuit functions as a current-limited voltage source, resulting in the CC/CV taper characteristic typically used for
rechargeable Lithium-Ion batteries. The coin cell charger is enabled via the COINCHEN bit while the coin cell voltage is programmable
through the VCOIN[2:0] bits on register COINCTL on Table 113. The coin cell charger voltage is programmable. In the on state, the
charger current is fixed at ICOINHI. In Sleep and Standby modes, the charger current is reduced to a typical 10 μA. In the off state, coin
cell charging is not available as the main battery could be depleted unnecessarily. The coin cell charging stops when VIN is below UVDET.

PF0100

98 NXP Semiconductors
 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 112. Coin cell charger voltage

VCOIN[2:0] VCOIN (V)(81)

000 2.50

001 2.70

010 2.80

011 2.90

100 3.00

101 3.10

110 3.20

111 3.30
Notes
81. Coin cell voltages selected based on the
type of LICELL used on the system.

Table 113. Register COINCTL - ADDR 0x1A

Name Bit # R/W Default Description

Coin cell charger output voltage selection.

VCOIN 2:0 R/W 0x00 See Table 112 for all options selectable through
these bits.

COINCHEN 3 R/W 0x00 Enable or disable the coin cell charger

UNUSED 7:4 – 0x00 unused

6.4.7.1.2 External components

Table 114. Coin cell charger external components

Component Value Units

LICELL bypass capacitor 100 nF

6.4.7.1.3 Coin cell specifications

Table 115. Coin cell charger specifications

Parameter Typ Unit

Voltage accuracy 100 mV

Coin cell charge current in on mode ICOINHI 60 μA

Current accuracy 30 %

PF0100

NXP Semiconductors 99
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.5 Control interface I2C block description

The PF0100 contains an I2C interface port which allows access by a processor, or any I2C master, to the register set. Via these registers
the resources of the IC can be controlled. The registers also provide status information about how the IC is operating.
The SCL and SDA lines should be routed away from noisy signals and planes to minimize noise pick up. To prevent reflections in the SCL
and SDA traces from creating false pulses, the rise and fall times of the SCL and SDA signals must be greater than 20 ns. This can be
accomplished by reducing the drive strength of the I2C master via software. The i.MX6 I2C driver defaults to a 40 Ω drive strength. It is
recommended to use a drive strength of 80 Ω or higher to increase the edge times. Alternatively, this can be accomplished by using small
capacitors from SCL and SDA to ground. For example, use 5.1 pF capacitors from SCL and SDA to ground for bus pull-up resistors of
4.8 kΩ.

6.5.1 I2C device ID

I2C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing for bus
conflict avoidance, fuse programmability is provided to allow configuration for the lower 3 address LSB(s). Refer to 6.1.2 One time
programmability (OTP), page 21 for more details. This product supports 7-bit addressing only; support is not provided for 10-bit or general
call addressing. Note, when the TBB bits for the I2C slave address are written, the next access to the chip, must then use the new slave
address; these bits take affect right away.

6.5.2 I2C operation

The I2C mode of the interface is implemented generally following the fast mode definition which supports up to 400 kbits/s operation
(exceptions to the standard are noted to be 7-bit only addressing and no support for general call addressing.) Timing diagrams, electrical
specifications, and further details can be found in the I2C specification, which is available for download at:
http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf
I2C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB and each byte
is sent out unless a STOP command or NACK is received prior to completion.
The following examples show how to write and read data to and from the IC. The host initiates and terminates all communication. The host
sends a master command packet after driving the start condition. The device responds to the host if the master command packet contains
the corresponding slave address. In the following examples, the device is shown always responding with an ACK to transmissions from
the host. If at any time a NACK is received, the host should terminate the current transaction and retry the transaction.

Host can
Packet Device Master Driven Data
also drive
Type Add ress
Reg ister Addre ss
( byte 0 ) another
Start instead
7 0 7 0 7 0 of Stop
Host SDA START 0 STOP

R/W

A A A
Slave SDA C
K
C
K
C
K

Figure 33. I2C write example

Host can also

Packet Device
Register Address Device Address
Address PMIC Driven Data drive another
Type
Start instead of
23 16 15 8 7 0 Stop
Host SDA START 0 START 1 NA STOP
CK

R/W R/W
7 0
A A A
Slave SDA C C C
K K K

Figure 34. I2C read example

PF0100

100 NXP Semiconductors

 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.5.3 Interrupt handling

The system is informed about important events based on interrupts. Unmasked interrupt events are signaled to the processor by driving
the INTB pin low.
Each interrupt is latched so even if the interrupt source becomes inactive, the interrupt remains set until cleared. Each interrupt can be
cleared by writing a “1” to the appropriate bit in the Interrupt Status register; this also causes the INTB pin to go high. If there are multiple
interrupt bits set the INTB pin remains low until all are either masked or cleared. If a new interrupt occurs while the processor clears an
existing interrupt bit, the INTB pin remains low.
Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high, the INTB
pin does not go low. A masked interrupt can still be read from the Interrupt Status register. This gives the processor the option of polling
for status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the device to determine if any
interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked interrupt bit was already high, the
INTB pin goes low after unmasking.
The sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources. They are
read only, and not latched or clearable.
Interrupts generated by external events are debounced; therefore, the event needs to be stable throughout the debounce period before
an interrupt is generated. Nominal debounce periods for each event are documented in the INT summary Table 116. Due to the
asynchronous nature of the debounce timer, the effective debounce time can vary slightly.

6.5.4 Interrupt bit summary

Table 116 summarizes all interrupt, mask, and sense bits associated with INTB control. For more detailed behavioral descriptions, refer
to the related chapters.

Table 116. Interrupt, mask and sense bits

Interrupt Mask Sense Purpose Trigger Debounce time (ms)

Low input voltage detect

LOWVINI LOWVINM LOWVINS H to L 3.9(82)
Sense is 1 if below 2.80 V threshold
Power on button event H to L 31.25(82)
PWRONI PWRONM PWRONS
Sense is 1 if PWRON is high. L to H 31.25

Thermal 110 °C threshold

THERM110 THERM110M THERM110S Dual 3.9
Sense is 1 if above threshold

Thermal 120 °C threshold

THERM120 THERM120M THERM120S Dual 3.9
Sense is 1 if above threshold
Thermal 125 °C threshold
THERM125 THERM125M THERM125S Dual 3.9
Sense is 1 if above threshold

Thermal 130 °C threshold

THERM130 THERM130M THERM130S Dual 3.9
Sense is 1 if above threshold

Regulator 1A overcurrent limit

SW1AFAULTI SW1AFAULTM SW1AFAULTS L to H 8.0
Sense is 1 if above current limit
Regulator 1B overcurrent limit
SW1BFAULTI SW1BFAULTM SW1BFAULTS L to H 8.0
Sense is 1 if above current limit

Regulator 1C overcurrent limit

SW1CFAULTI SW1CFAULTM SW1CFAULTS L to H 8.0
Sense is 1 if above current limit

Regulator 2 overcurrent limit

SW2FAULTI SW2FAULTM SW2FAULTS L to H 8.0
Sense is 1 if above current limit
Regulator 3A overcurrent limit
SW3AFAULTI SW3AFAULTM SW3AFAULTS L to H 8.0
Sense is 1 if above current limit

Regulator 3B overcurrent limit

SW3BFAULTI SW3BFAULTM SW3BFAULTS L to H 8.0
Sense is 1 if above current limit

Regulator 4 overcurrent limit

SW4FAULTI SW4FAULTM SW4FAULTS L to H 8.0
Sense is 1 if above current limit

PF0100

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Table 116. Interrupt, mask and sense bits (continued)

Interrupt Mask Sense Purpose Trigger Debounce time (ms)

SWBST overcurrent limit

SWBSTFAULTI SWBSTFAULTM SWBSTFAULTS L to H 8.0
Sense is 1 if above current limit
VGEN1 overcurrent limit
VGEN1FAULTI VGEN1FAULTM VGEN1FAULTS L to H 8.0
Sense is 1 if above current limit

VGEN2 overcurrent limit

VGEN2FAULTI VGEN2FAULTM VGEN2FAULTS L to H 8.0
Sense is 1 if above current limit

VGEN3 overcurrent limit

VGEN3FAULTI VGEN3FAULTM VGEN3FAULTS L to H 8.0
Sense is 1 if above current limit
VGEN4 overcurrent limit
VGEN4FAULTI VGEN4FAULTM VGEN4FAULTS L to H 8.0
Sense is 1 if above current limit

VGEN5 overcurrent limit

VGEN5FAULTI VGEN5FAULTM VGEN1FAULTS L to H 8.0
Sense is 1 if above current limit

VGEN6 overcurrent limit

VGEN6FAULTI VGEN6FAULTM VGEN6FAULTS L to H 8.0
Sense is 1 if above current limit
1 or 2 bit error detected in OTP registers
OTP_ECCI OTP_ECCM OTP_ECCS L to H 8.0
Sense is 1 if error detected

Notes
82. Debounce timing for the falling edge can be extended with PWRONDBNC[1:0].

A full description of all interrupt, mask, and sense registers is provided in Tables 117 to 128.

Table 117. Register INTSTAT0 - ADDR 0x05

Name Bit # R/W Default Description

PWRONI 0 R/W1C 0 Power on interrupt bit

LOWVINI 1 R/W1C 0 Low-voltage interrupt bit

THERM110I 2 R/W1C 0 110 °C Thermal interrupt bit

THERM120I 3 R/W1C 0 120 °C Thermal interrupt bit

THERM125I 4 R/W1C 0 125 °C Thermal interrupt bit

THERM130I 5 R/W1C 0 130 °C Thermal interrupt bit

UNUSED 7:6 – 00 unused

Table 118. Register INTMASK0 - ADDR 0x06

Name Bit # R/W Default Description

PWRONM 0 R/W1C 1 Power on interrupt mask bit

LOWVINM 1 R/W1C 1 Low-voltage interrupt mask bit

THERM110M 2 R/W1C 1 110 °C thermal interrupt mask bit

THERM120M 3 R/W1C 1 120 °C thermal interrupt mask bit

THERM125M 4 R/W1C 1 125 °C thermal interrupt mask bit

THERM130M 5 R/W1C 1 130 °C thermal interrupt mask bit

UNUSED 7:6 – 00 unused

PF0100

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 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 119. Register INTSENSE0 - ADDR 0x07

Name Bit # R/W Default Description

Power on sense bit

PWRONS 0 R 0 • 0 = PWRON low
• 1 = PWRON high

Low-voltage sense bit

LOWVINS 1 R 0 • 0 = VIN > 2.8 V
• 1 = VIN ≤ 2.8 V

110 °C thermal sense bit

THERM110S 2 R 0 • 0 = Below threshold
• 1 = Above threshold

120 °C thermal sense bit

THERM120S 3 R 0 • 0 = Below threshold
• 1 = Above threshold

125 °C thermal sense bit

THERM125S 4 R 0 • 0 = Below threshold
• 1 = Above threshold

130 °C thermal sense bit

THERM130S 5 R 0 • 0 = Below threshold
• 1 = Above threshold

UNUSED 6 – 0 unused

Additional VDDOTP voltage sense pin

VDDOTPS 7 R 00 • 0 = VDDOTP grounded
• 1 = VDDOTP to VCOREDIG or greater

Table 120. Register INTSTAT1 - ADDR 0x08

Name Bit # R/W Default Description

SW1AFAULTI 0 R/W1C 0 SW1A overcurrent interrupt bit

SW1BFAULTI 1 R/W1C 0 SW1B overcurrent interrupt bit

SW1CFAULTI 2 R/W1C 0 SW1C overcurrent interrupt bit

SW2FAULTI 3 R/W1C 0 SW2 overcurrent interrupt bit

SW3AFAULTI 4 R/W1C 0 SW3A overcurrent interrupt bit

SW3BFAULTI 5 R/W1C 0 SW3B overcurrent interrupt bit

SW4FAULTI 6 R/W1C 0 SW4 overcurrent interrupt bit

UNUSED 7 – 0 unused

Table 121. Register INTMASK1 - ADDR 0x09

Name Bit # R/W Default Description

SW1AFAULTM 0 R/W 1 SW1A overcurrent interrupt mask bit

SW1BFAULTM 1 R/W 1 SW1B overcurrent interrupt mask bit

SW1CFAULTM 2 R/W 1 SW1C overcurrent interrupt mask bit

SW2FAULTM 3 R/W 1 SW2 overcurrent interrupt mask bit

SW3AFAULTM 4 R/W 1 SW3A overcurrent interrupt mask bit

SW3BFAULTM 5 R/W 1 SW3B overcurrent interrupt mask bit

PF0100

NXP Semiconductors 103

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 121. Register INTMASK1 - ADDR 0x09 (continued)

Name Bit # R/W Default Description

SW4FAULTM 6 R/W 1 SW4 overcurrent interrupt mask bit

UNUSED 7 – 0 unused

Table 122. Register INTSENSE1 - ADDR 0x0A

Name Bit # R/W Default Description

SW1A overcurrent sense bit

SW1AFAULTS 0 R 0 • 0 = Normal operation
• 1 = Above current limit

SW1B overcurrent sense bit

SW1BFAULTS 1 R 0 • 0 = Normal operation
• 1 = Above current limit

SW1C overcurrent sense bit

SW1CFAULTS 2 R 0 • 0 = Normal operation
• 1 = Above current limit

SW2 overcurrent sense bit

SW2FAULTS 3 R 0 • 0 = Normal operation
• 1 = Above current limit
SW3A overcurrent sense bit
SW3AFAULTS 4 R 0 • 0 = Normal operation
• 1 = Above current limit

SW3B overcurrent sense bit

SW3BFAULTS 5 R 0 • 0 = Normal operation
• 1 = Above current limit

SW4 overcurrent sense bit

SW4FAULTS 6 R 0 • 0 = Normal operation
• 1 = Above current limit

UNUSED 7 – 0 unused

Table 123. Register INTSTAT3 - ADDR 0x0E

Name Bit # R/W Default Description

SWBSTFAULTI 0 R/W1C 0 SWBST overcurrent limit interrupt bit

UNUSED 6:1 – 0x00 unused

OTP_ECCI 7 R/W1C 0 OTP error interrupt bit

Table 124. Register INTMASK3 - ADDR 0x0F

Name Bit # R/W Default Description

SWBSTFAULTM 0 R/W 1 SWBST overcurrent limit interrupt mask bit

UNUSED 6:1 – 0x00 unused

OTP_ECCM 7 R/W 1 OTP error interrupt mask bit

PF0100

104 NXP Semiconductors

 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 125. Register INTSENSE3 - ADDR 0x10

Name Bit # R/W Default Description

SWBST overcurrent limit sense bit

SWBSTFAULTS 0 R 0 • 0 = Normal operation
• 1 = Above current limit

UNUSED 6:1 – 0x00 unused

OTP error sense bit

OTP_ECCS 7 R 0 • 0 = No error detected
• 1 = OTP error detected

Table 126. Register INTSTAT4 - ADDR 0x11

Name Bit # R/W Default Description

VGEN1FAULTI 0 R/W1C 0 VGEN1 overcurrent interrupt bit

VGEN2FAULTI 1 R/W1C 0 VGEN2 overcurrent interrupt bit

VGEN3FAULTI 2 R/W1C 0 VGEN3 overcurrent interrupt bit

VGEN4FAULTI 3 R/W1C 0 VGEN4 overcurrent interrupt bit

VGEN5FAULTI 4 R/W1C 0 VGEN5 overcurrent interrupt bit

VGEN6FAULTI 5 R/W1C 0 VGEN6 overcurrent interrupt bit

UNUSED 7:6 – 00 unused

Table 127. Register INTMASK4 - ADDR 0x12

Name Bit # R/W Default Description

VGEN1FAULTM 0 R/W 1 VGEN1 overcurrent interrupt mask bit

VGEN2FAULTM 1 R/W 1 VGEN2 overcurrent interrupt mask bit

VGEN3FAULTM 2 R/W 1 VGEN3 overcurrent interrupt mask bit

VGEN4FAULTM 3 R/W 1 VGEN4 overcurrent interrupt mask bit

VGEN5FAULTM 4 R/W 1 VGEN5 overcurrent interrupt mask bit

VGEN6FAULTM 5 R/W 1 VGEN6 overcurrent interrupt mask bit

UNUSED 7:6 – 00 unused

Table 128. Register INTSENSE4 - ADDR 0x13

Name Bit # R/W Default Description

VGEN1 overcurrent sense bit

VGEN1FAULTS 0 R 0 • 0 = Normal operation
• 1 = Above current limit

VGEN2 overcurrent sense bit

VGEN2FAULTS 1 R 0 • 0 = Normal operation
• 1 = Above current limit

VGEN3 overcurrent sense bit

VGEN3FAULTS 2 R 0 • 0 = Normal operation
• 1 = Above current limit

VGEN4 overcurrent sense bit

VGEN4FAULTS 3 R 0 • 0 = Normal operation
• 1 = Above current limit

PF0100

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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 128. Register INTSENSE4 - ADDR 0x13 (continued)

Name Bit # R/W Default Description

VGEN5 overcurrent sense bit

VGEN5FAULTS 4 R 0 • 0 = Normal operation
• 1 = Above current limit

VGEN6 overcurrent sense bit

VGEN6FAULTS 5 R 0 • 0 = Normal operation
• 1 = Above current limit

UNUSED 7:6 – 00 unused

6.5.5 Specific registers

6.5.5.1 IC and version identification

The IC and other version details can be read via identification bits. These are hard-wired on chip and described in Tables 129 to 131.

Table 129. Register DEVICEID - ADDR 0x00

Name Bit # R/W Default Description

Die version.
DEVICEID 3:0 R 0x00
• 0000 = PF0100

UNUSED 7:4 – 0x01 unused

Table 130. Register SILICON REV- ADDR 0x03

Name Bit # R/W Default Description

Represents the metal mask revision

• Pass 0.0 = 0000
METAL_LAYER_REV 3:0 R 0x00 •.
•.
• Pass 0.15 = 1111

Represents the full mask revision

• Pass 1.0 = 0001
FULL_LAYER_REV 7:4 R 0x01 •.
•.
• Pass 15.0 = 1111

Table 131. Register FABID - ADDR 0x04

Name Bit # R/W Default Description

Allows for characterizing different options within

FIN 1:0 R 0x00
the same reticule

FAB 3:2 R 0x00 Represents the wafer manufacturing facility

Unused 7:0 R 0x00 unused

6.5.5.2 Embedded memory

There are four register banks of general purpose embedded memory to store critical data. The data written to MEMA[7:0], MEMB[7:0],
MEMC[7:0], and MEMD[7:0] is maintained by the coin cell when the main battery is deeply discharged, removed, or contact-bounced. The
contents of the embedded memory are reset by COINPORB. The banks can be used for any system need for bit retention with coin cell
backup.

PF0100

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Table 132. Register MEMA ADDR 0x1C

Name Bit # R/W Default Description

MEMA 7:0 R/W 0 Memory bank A

Table 133. Register MEMB ADDR 0x1D

Name Bit # R/W Default Description

MEMB 7:0 R/W 0 Memory bank B

Table 134. Register MEMC ADDR 0x1E

Name Bit # R/W Default Description

MEMC 7:0 R/W 0 Memory bank C

Table 135. Register MEMD ADDR 0x1F

Name Bit # R/W Default Description

MEMD 7:0 R/W 0 Memory bank D

6.5.6 Register bitmap

The register map is comprised of thirty-two pages, and its address and data fields are each eight bits wide. Only the first two pages can
be accessed. On each page, registers 0 to 0x7F are referred to as 'functional', and registers 0x80 to 0xFF as 'extended'. On each page,
the functional registers are the same, but the extended registers are different. To access registers in Table 137. Extended page 1, page
111, one must first write 0x01 to the page register at address 0x7F, and to access registers in Table 138. Extended Page 2, page 115,
one must first write 0x02 to the page register at address 0x7F. To access Table 136. Functional page, page 108 from one of the extended
pages, no write to the page register is necessary.
Registers missing in the sequence are reserved; reading from them returns a value 0x00, and writing to them has no effect.
The contents of all registers are given in the tables defined in this chapter; each table is structure as follows:
Name: Name of the bit.
Bit #: The bit location in the register (7-0)
R/W: Read / Write access and control
• R is read-only access
• R/W is read and write access
• RW1C is read and write access with write 1 to clear
Reset: Reset signals are color coded based on the following legend.

Bits reset by SC and VCOREDIG_PORB

Bits reset by PWRON or loaded default or OTP configuration
Bits reset by DIGRESETB
Bits reset by PORB or RESETBMCU
Bits reset by VCOREDIG_PORB
Bits reset by POR or OFFB

Default: The value after reset, as noted in the default column of the memory map.
• Fixed defaults are explicitly declared as 0 or 1.
• “X” corresponds to read/write bits which are initialized at start-up, based on the OTP fuse settings or default if VDDOTP = 1.5 V. Bits
are subsequently I2C modifiable, when their reset has been released. “X” may also refer to bits which may have other dependencies.
For example, some bits may depend on the version of the IC, or a value from an analog block, for instance the sense bits for the
interrupts.

PF0100

NXP Semiconductors 107

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.5.6.1 Register map

Table 136. Functional page

BITS[7:0]

Add Register name R/W Default 7 6 5 4 3 2 1 0

– – – – DEVICE ID [3:0]
00 DeviceID R 8'b0001_0000
0 0 0 1 0 0 0 0

FULL_LAYER_REV[3:0] METAL_LAYER_REV[3:0]
03 SILICONREVID R 8'b0001_0000
X X X X X X X X

– – – – FAB[1:0] FIN[1:0]
04 FABID R 8'b0000_0000
0 0 0 0 0 0 0 0

– – THERM130I THERM125I THERM120I THERM110I LOWVINI PWRONI

05 INTSTAT0 RW1C 8'b0000_0000
0 0 0 0 0 0 0 0

– – THERM130M THERM125M THERM120M THERM110M LOWVINM PWRONM

06 INTMASK0 R/W 8'b0011_1111
0 0 1 1 1 1 1 1

VDDOTPS RSVD THERM130S THERM125S THERM120S THERM110S LOWVINS PWRONS

07 INTSENSE0 R 8'b00xx_xxxx
0 0 x x x x x x

– SW4FAULTI SW3BFAULTI SW3AFAULTI SW2FAULTI SW1CFAULTI SW1BFAULTI SW1AFAULTI

08 INTSTAT1 RW1C 8'b0000_0000
0 0 0 0 0 0 0 0

– SW4FAULTM SW3BFAULTM SW3AFAULTM SW2FAULTM SW1CFAULTM SW1BFAULTM SW1AFAULTM

09 INTMASK1 R/W 8'b0111_1111
0 1 1 1 1 1 1 1

– SW4FAULTS SW3BFAULTS SW3AFAULTS SW2FAULTS SW1CFAULTS SW1BFAULTS SW1AFAULTS

0A INTSENSE1 R 8'b0xxx_xxxx
0 x x x x x x x

OTP_ECCI – – – – – – SWBSTFAULTI
0E INTSTAT3 RW1C 8'b0000_0000
0 0 0 0 0 0 0 0

OTP_ECCM – – – – – – SWBSTFAULTM
0F INTMASK3 R/W 8'b1000_0001
1 0 0 0 0 0 0 1

OTP_ECCS – – – – – – SWBSTFAULTS
10 INTSENSE3 R 8'b0000_000x
0 0 0 0 0 0 0 x

– – VGEN6FAULTI VGEN5FAULTI VGEN4FAULTI VGEN3FAULTI VGEN2FAULTI VGEN1FAULTI

11 INTSTAT4 RW1C 8'b0000_0000
0 0 0 0 0 0 0 0

VGEN6 VGEN5 VGEN4 VGEN3 VGEN2 VGEN1

– –
FAULTM FAULTM FAULTM FAULTM FAULTM FAULTM
12 INTMASK4 R/W 8'b0011_1111
0 0 1 1 1 1 1 1

VGEN6 VGEN5 VGEN4 VGEN3 VGEN2 VGEN1

– –
FAULTS FAULTS FAULTS FAULTS FAULTS FAULTS
13 INTSENSE4 R 8'b00xx_xxxx
0 0 x x x x x x

– – – – COINCHEN VCOIN[2:0]
1A COINCTL R/W 8'b0000_0000
0 0 0 0 0 0 0 0

PF0100

108 NXP Semiconductors

 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 136. Functional page (continued)

BITS[7:0]

Add Register name R/W Default 7 6 5 4 3 2 1 0

REGSCPEN STANDBYINV STBYDLY[1:0] PWRONBDBNC[1:0] PWRONRSTEN RESTARTEN

1B PWRCTL R/W 8'b0001_0000
0 0 0 1 0 0 0 0

MEMA[7:0]
1C MEMA R/W 8'b0000_0000
0 0 0 0 0 0 0 0

MEMB[7:0]
1D MEMB R/W 8'b0000_0000
0 0 0 0 0 0 0 0

MEMC[7:0]
1E MEMC R/W 8'b0000_0000
0 0 0 0 0 0 0 0

MEMD[7:0]
1F MEMD R/W 8'b0000_0000
0 0 0 0 0 0 0 0

– – SW1AB[5:0]
20 SW1ABVOLT R/W/M 8'b00xx_xxxx
0 0 x x x x x x

– – SW1ABSTBY[5:0]
21 SW1ABSTBY R/W 8'b00xx_xxxx
0 0 x x x x x x

– – SW1ABOFF[5:0]
22 SW1ABOFF R/W 8'b00xx_xxxx
0 0 x x x x x x

– – SW1ABOMODE – SW1ABMODE[3:0]
23 SW1ABMODE R/W 8'b0000_1000
0 0 0 0 1 0 0 0

SW1ABDVSSPEED[1:0] SW1BAPHASE[1:0] SW1ABFREQ[1:0] – SW1ABILIM

24 SW1ABCONF R/W 8'bxx00_xx00
x x 0 0 x x 0 0

– – SW1C[5:0]
2E SW1CVOLT R/W 8'b00xx_xxxx
0 0 x x x x x x

– – SW1CSTBY[5:0]
2F SW1CSTBY R/W 8'b00xx_xxxx
0 0 x x x x x x

– – SW1COFF[5:0]
30 SW1COFF R/W 8'b00xx_xxxx
0 0 x x x x x x

– – SW1COMODE – SW1CMODE[3:0]
31 SW1CMODE R/W 8'b0000_1000
0 0 0 0 1 0 0 0

SW1CDVSSPEED[1:0] SW1CPHASE[1:0] SW1CFREQ[1:0] – SW1CILIM

32 SW1CCONF R/W 8'bxx00_xx00
x x 0 0 x x 0 0

– SW2[6:0]
35 SW2VOLT R/W 8'b0xxx_xxxx
0 x x x x x x x

– SW2STBY[6:0]
36 SW2STBY R/W 8'b0xxx_xxxx
0 x x x x x x x

– SW2OFF[6:0]
37 SW2OFF R/W 8'b0xxx_xxxx
0 x x x x x x x

PF0100

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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 136. Functional page (continued)

BITS[7:0]

Add Register name R/W Default 7 6 5 4 3 2 1 0

– – SW2OMODE – SW2MODE[3:0]
38 SW2MODE R/W 8'b0000_1000
0 0 0 0 1 0 0 0

SW2DVSSPEED[1:0] SW2PHASE[1:0] SW2FREQ[1:0] – SW2ILIM

39 SW2CONF R/W 8'bxx01_xx00
x x 0 1 x x 0 0

– SW3A[6:0]
3C SW3AVOLT R/W 8'b0xxx_xxxx
0 x x x x x x x

– SW3ASTBY[6:0]
3D SW3ASTBY R/W 8'b0xxx_xxxx
0 x x x x x x x

– SW3AOFF[6:0]
3E SW3AOFF R/W 8'b0xxx_xxxx
0 x x x x x x x

SW3AOMODE – SW3AMODE[3:0]
3F SW3AMODE R/W 8'b0000_1000
0 0 0 0 1 0 0 0

SW3ADVSSPEED[1:0] SW3APHASE[1:0] SW3AFREQ[1:0] – SW3AILIM

40 SW3ACONF R/W 8'bxx10_xx00
x x 1 0 x x 0 0

– SW3B[6:0]
43 SW3BVOLT R/W 8'b0xxx_xxxx
0 x x x x x x x

– SW3BSTBY[6:0]
44 SW3BSTBY R/W 8'b0xxx_xxxx
0 x x x x x x x

– SW3BOFF[6:0]
45 SW3BOFF R/W 8'b0xxx_xxxx
0 x x x x x x x

– – SW3BOMODE – SW3BMODE[3:0]
46 SW3BMODE R/W 8'b0000_1000
0 0 0 0 1 0 0 0

SW3BDVSSPEED[1:0] SW3BPHASE[1:0] SW3BFREQ[1:0] – SW3BILIM

47 SW3BCONF R/W 8'bxx10_xx00
x x 1 0 x x 0 0

– SW4[6:0]
4A SW4VOLT R/W 8'b0xxx_xxxx
0 x x x x x x x

– SW4STBY[6:0]
4B SW4STBY R/W 8'b0xxx_xxxx
0 x x x x x x x

– SW4OFF[6:0]
4C SW4OFF R/W 8'b0xxx_xxxx
0 x x x x x x x

– – SW4OMODE – SW4MODE[3:0]
4D SW4MODE R/W 8'b0000_1000
0 0 0 0 1 0 0 0

SW4DVSSPEED[1:0] SW4PHASE[1:0] SW4FREQ[1:0] – SW4ILIM

4E SW4CONF R/W 8'bxx11_xx00
x x 1 1 x x 0 0

PF0100

110 NXP Semiconductors

 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 136. Functional page (continued)

BITS[7:0]

Add Register name R/W Default 7 6 5 4 3 2 1 0

– SWBST1STBYMODE[1:0] – SWBST1MODE[1:0] SWBST1VOLT[1:0]

66 SWBSTCTL R/W 8'b0xx0_10xx
0 x x 0 1 0 x x

– – – VREFDDREN – – – –
6A VREFDDRCTL R/W 8'b000x_0000
0 0 0 x 0 0 0 0

– – – – – VSNVSVOLT[2:0]
6B VSNVSCTL R/W 8'b0000_0xxx
0 0 0 0 0 0 x x

– VGEN1LPWR VGEN1STBY VGEN1EN VGEN1[3:0]

6C VGEN1CTL R/W 8'b000x_xxxx
0 0 0 x x x x x

– VGEN2LPWR VGEN2STBY VGEN2EN VGEN2[3:0]

6D VGEN2CTL R/W 8'b000x_xxxx
0 0 0 x x x x x

– VGEN3LPWR VGEN3STBY VGEN3EN VGEN3[3:0]

6E VGEN3CTL R/W 8'b000x_xxxx
0 0 0 x x x x x

– VGEN4LPWR VGEN4STBY VGEN4EN VGEN4[3:0]

6F VGEN4CTL R/W 8'b000x_xxxx
0 0 0 x x x x x

– VGEN5LPWR VGEN5STBY VGEN5EN VGEN5[3:0]

70 VGEN5CTL R/W 8'b000x_xxxx
0 0 0 x x x x x

– VGEN6LPWR VGEN6STBY VGEN6EN VGEN6[3:0]

71 VGEN6CTL R/W 8'b000x_xxxx
0 0 0 x x x x x

– – – PAGE[4:0]
7F Page Register R/W 8'b0000_0000
0 0 0 0 0 0 0 0

Table 137. Extended page 1

BITS[7:0]
Address Register name TYPE Default
7 6 5 4 3 2 1 0

OTP FUSE
– – – – – – –
OTP FUSE READ READ EN
80 R/W 8'b000x_xxx0
EN
0 0 0 x x x x 0

RL TRIM
START RL PWBRTN FORCE PWRCTL RL PWRCTL RL OTP RL OTP ECC RL OTP FUSE
FUSE
84 OTP LOAD MASK R/W 8'b0000_0000
0 0 0 0 0 0 0 0

– – – ECC5_SE ECC4_SE ECC3_SE ECC2_SE ECC1_SE

8A OTP ECC SE1 R 8'bxxx0_0000
x x x 0 0 0 0 0

– – – ECC10_SE ECC9_SE ECC8_SE ECC7_SE ECC6_SE

8B OTP ECC SE2 R 8'bxxx0_0000
x x x 0 0 0 0 0

– – – ECC5_DE ECC4_DE ECC3_DE ECC2_DE ECC1_DE

8C OTP ECC DE1 R 8'bxxx0_0000
x x x 0 0 0 0 0

PF0100

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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 137. Extended page 1 (continued)

BITS[7:0]
Address Register name TYPE Default
7 6 5 4 3 2 1 0

– – – ECC10_DE ECC9_DE ECC8_DE ECC7_DE ECC6_DE

8D OTP ECC DE2 R 8'bxxx0_0000
x x x 0 0 0 0 0

– – SW1AB_VOLT[5:0]
A0 OTP SW1AB VOLT R/W 8'b00xx_xxxx
0 0 x x x x x x

– SW1AB_SEQ[4:0]
A1 OTP SW1AB SEQ R/W 8'b000x_xxXx
0 0 0 x x x X x

– – – – SW1_CONFIG[1:0] SW1AB_FREQ[1:0]
OTP SW1AB
A2 R/W 8'b0000_xxxx
CONFIG
0 0 0 0 x x x x

– – SW1C_VOLT[5:0]
A8 OTP SW1C VOLT R/W 8'b00xx_xxxx
0 0 x x x x x x

– SW1C_SEQ[4:0]
A9 OTP SW1C SEQ R/W 8'b000x_xxxx
0 0 0 x x x x x

– – – – – – SW1C_FREQ[1:0]
OTP SW1C
AA R/W 8'b0000_00xx
CONFIG
0 0 0 0 0 0 x x

– SW2_VOLT[5:0]
AC OTP SW2 VOLT R/W 8'b0xxx_xxxx
0 x x x x x x x

– – SW2_SEQ[4:0]
AD OTP SW2 SEQ R/W 8'b000x_xxxx
0 0 0 x x x x x

– – – – – – SW2_FREQ[1:0]
AE OTP SW2 CONFIG R/W 8'b0000_00xx
0 0 0 0 0 0 x x

– SW3A_VOLT[6:0]
B0 OTP SW3A VOLT R/W 8'b0xxx_xxxx
0 x x x x x x x

– – SW3A_SEQ[4:0]
B1 OTP SW3A SEQ R/W 8'b000x_xxxx
0 0 0 x x x x x

– – – – SW3_CONFIG[1:0] SW3A_FREQ[1:0]
OTP SW3A
B2 R/W 8'b0000_xxxx
CONFIG
0 0 0 0 x x x x

– SW3B_VOLT[6:0]
B4 OTP SW3B VOLT R/W 8'b0xxx_xxxx
0 x x x x x x x

– – SW3B_SEQ[4:0]
B5 OTP SW3B SEQ R/W 8'b000x_xxxx
0 0 0 x x x x x

– – – – – – SW3B_CONFIG[1:0]
OTP SW3B
B6 R/W 8'b0000_00xx
CONFIG
0 0 0 0 0 0 x x

PF0100

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Table 137. Extended page 1 (continued)

BITS[7:0]
Address Register name TYPE Default
7 6 5 4 3 2 1 0

– SW4_VOLT[6:0]
B8 OTP SW4 VOLT R/W 8'b00xx_xxxx
0 0 x x x x x x

– – – SW4_SEQ[4:0]
B9 OTP SW4 SEQ R/W 8'b000x_xxxx
0 0 0 x x x x x

– – – VTT – – SW4_FREQ[1:0]
BA OTP SW4 CONFIG R/W 8'b000x_xxxx
0 0 0 x x x x x

– – – – – – SWBST_VOLT[1:0]
BC OTP SWBST VOLT R/W 8'b0000_00xx
0 0 0 0 0 0 x x

– – – SWBST_SEQ[4:0]
BD OTP SWBST SEQ R/W 8'b0000_xxxx
0 0 0 0 x x x x

– – – – – VSNVS_VOLT[2:0]
C0 OTP VSNVS VOLT R/W 8'b0000_0xxx
0 0 0 0 0 0 x x

– – – VREFDDR_SEQ[4:0]
OTP VREFDDR
C4 R/W 8'b000x_x0xx
SEQ
0 0 0 x x 0 x x

– – – – VGEN1_VOLT[3:0]
C8 OTP VGEN1 VOLT R/W 8'b0000_xxxx
0 0 0 0 x x x x

– – – VGEN1_SEQ[4:0]
C9 OTP VGEN1 SEQ R/W 8'b000x_xxxx
0 0 0 x x x x x

– – – – VGEN2_VOLT[3:0]
CC OTP VGEN2 VOLT R/W 8'b0000_xxxx
0 0 0 0 x x x x

– – – VGEN2_SEQ[4:0]
CD OTP VGEN2 SEQ R/W 8'b000x_xxxx
0 0 0 x x x x x

– – – – VGEN3_VOLT[3:0]
D0 OTP VGEN3 VOLT R/W 8'b0000_xxxx
0 0 0 0 x x x x

– – – VGEN3_SEQ[4:0]
D1 OTP VGEN3 SEQ R/W 8'b000x_xxxx
0 0 0 x x x x x

– – – – VGEN4_VOLT[3:0]
D4 OTP VGEN4 VOLT R/W 8'b0000_xxxx
0 0 0 0 x x x x

– – – VGEN4_SEQ[4:0]
D5 OTP VGEN4 SEQ R/W 8'b000x_xxxx
0 0 0 x x x x x

PF0100

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Table 137. Extended page 1 (continued)

BITS[7:0]
Address Register name TYPE Default
7 6 5 4 3 2 1 0

– – – – VGEN5_VOLT[3:0]
D8 OTP VGEN5 VOLT R/W 8'b0000_xxxx
0 0 0 0 x x x x

– – – VGEN5_SEQ[4:0]
D9 OTP VGEN5 SEQ R/W 8'b000x_xxxx
0 0 0 x x x x x

– – – – VGEN6_VOLT[3:0]
DC OTP VGEN6 VOLT R/W 8'b0000_xxxx
0 0 0 0 x x x x

– – – VGEN6_SEQ[4:0]
DD OTP VGEN6 SEQ R/W 8'b000x_xxxx
0 0 0 x x x x x

PWRON_
– – – SWDVS_CLK1[1:0] SEQ_CLK_SPEED1[1:0]
CFG1
E0 OTP PU CONFIG1 R/W 8'b000x_xxxx
0 0 0 x x x x x

PWRON_
– – – SWDVS_CLK2[1:0] SEQ_CLK_SPEED2[1:0]
CFG2
E1 OTP PU CONFIG2 R/W 8'b000x_xxxx
0 0 0 x x x x x

PWRON_
– – – SWDVS_CLK3[1:0] SEQ_CLK_SPEED3[1:0]
CFG3
E2 OTP PU CONFIG3 R/W 8'b000x_xxxx
0 0 0 x x x x x

PWRON_CFG
– – – SWDVS_CLK3_XOR SEQ_CLK_SPEED_XOR
OTP PU CONFIG _XOR
E3 R 8'b000x_xxxx
XOR
0 0 0 x x x x x

SOFT_FUSE_
TBB_POR – – – – FUSE_POR1 –
POR
E4 (83) OTP FUSE POR1 R/W 8'b0000_00x0
0 0 0 0 0 0 x 0

RSVD RSVD – – – – FUSE_POR2 –

E5 OTP FUSE POR1 R/W 8'b0000_00x0
0 0 0 0 0 0 x 0

RSVD RSVD – – – – FUSE_POR3 –

E6 OTP FUSE POR1 R/W 8'b0000_00x0
0 0 0 0 0 0 x 0

FUSE_POR_X
RSVD RSVD – – – – –
OTP FUSE POR OR
E7 R 8'b0000_00x0
XOR
0 0 0 0 0 0 x 0

– – – – – – – OTP_PG_EN
E8 OTP PWRGD EN R/W/M 8'b0000_000x
0 0 0 0 0 0 x 0

EN_ECC_ EN_ECC_ EN_ECC_ EN_ECC_ EN_ECC_

– – –
BANK5 BANK4 BANK3 BANK2 BANK1
F0 OTP EN ECCO R/W 8'b000x_xxxx
0 0 0 x x x x x

EN_ECC_ EN_ECC_ EN_ECC_ EN_ECC_ EN_ECC_

– – –
BANK10 BANK9 BANK8 BANK7 BANK6
F1 OTP EN ECC1 R/W 8'b000x_xxxx
0 0 0 x x x x x

– – – – RSVD
F4 OTP SPARE2_4 R/W 8'b0000_xxxx
0 0 0 0 x x x x

PF0100

114 NXP Semiconductors

 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 137. Extended page 1 (continued)

BITS[7:0]
Address Register name TYPE Default
7 6 5 4 3 2 1 0

– – – – – RSVD
F5 OTP SPARE4_3 R/W 8'b0000_0xxx
0 0 0 0 0 x x x

– – – – – – RSVD
F6 OTP SPARE6_2 R/W 8'b0000_00xx
0 0 0 0 0 0 x x

– – – – – – – RSVD
F7 OTP SPARE7_1 R/W 8'b0000_0xxx
0 0 0 0 0 x x x

– – – – – – – OTP_DONE
FE OTP DONE R/W 8'b0000_000x
0 0 0 0 0 0 0 x

I2C_SLV
– – – – I2C_SLV ADDR[2:0]
ADDR[3]
FF OTP I2C ADDR R/W 8'b0000_0xxx
0 0 0 0 1 x x x

Notes
83. In the MMPF0100 FUSE_POR1, FUSE_POR2, and FUSE_POR3 are XOR’ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR has to be 1
for fuses to be loaded. This can be achieved by setting any one or all of the FUSE_PORx bits. In MMPF0100A, the XOR function is removed. It is
required to set all of the FUSE_PORx bits to be able to load the fuses.

Table 138. Extended Page 2

BITS[7:0]
Address Register name TYPE Default
7 6 5 4 3 2 1 0

RSVD RSVD RSVD RSVD RSVD SW1AB_PWRSTG[2:0]

81 SW1AB PWRSTG R/W 8'b1111_1111
1 1 1 1 1 1 1 1

PWRSTGRSVD
82 PWRSTG RSVD R 8'b0000_0000
0 0 0 0 0 0 0 0

RSVD RSVD RSVD RSVD RSVD SW1C_PWRSTG[2:0]

83 SW1C PWRSTG R 8'b1111_1111
1 1 1 1 1 1 1 1

RSVD RSVD RSVD RSVD RSVD SW2_PWRSTG[2:0]

84 SW2 PWRSTG R 8'b1111_1111
1 1 1 1 1 1 1 1

RSVD RSVD RSVD RSVD RSVD SW3A_PWRSTG[2:0]

85 SW3A PWRSTG R 8'b1111_1111
1 1 1 1 1 1 1 1

RSVD RSVD RSVD RSVD RSVD SW3B_PWRSTG[2:0]

86 SW3B PWRSTG R 8'b1111_1111
1 1 1 1 1 1 1 1

FSLEXT_ PWRGD_
THERM_ SHDWN_ RSVD RSVD RSVD SW4_PWRSTG[2:0]
87 SW4 PWRSTG R 8'b0111_1111 DISABLE DISABLE

0 0 1 1 1 1 1 1

OTP_
– – – – – – PWRGD_EN
PWRCTRL OTP SHDWN_EN
88 R/W 8'b0000_0001
CTRL
0 0 0 0 0 0 0 1

I2C_WRITE_ADDRESS_TRAP[7:0]
I2C WRITE
8D R/W 8'b0000_0000
ADDRESS TRAP
0 0 0 0 0 0 0 0

PF0100

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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 138. Extended Page 2 (continued)

BITS[7:0]
Address Register name TYPE Default
7 6 5 4 3 2 1 0

LET_IT_ ROLL RSVD RSVD I2C_TRAP_PAGE[4:0]

8E I2C TRAP PAGE R/W 8'b0000_0000
0 0 0 0 0 0 0 0

I2C_WRITE_ADDRESS_COUNTER[7:0]
8F I2C TRAP CNTR R/W 8'b0000_0000
0 0 0 0 0 0 0 0

SDA_DRV[1:0] SDWNB_DRV[1:0] INTB_DRV[1:0] RESETBMCU_DRV[1:0]

90 IO DRV R/W 8'b00xx_xxxx
0 0 x x x x x x

AUTO_ECC AUTO_ECC AUTO_ECC_B AUTO_ECC AUTO_ECC_B

– – –
_BANK5 _BANK4 ANK3 _BANK2 ANK1
DO OTP AUTO ECC0 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

AUTO_ECC_B AUTO_ECC AUTO_ECC_B AUTO_ECCBA AUTO_ECC_B

– – –
ANK10 _BANK9 ANK8 NK7 ANK6
D1 OTP AUTO ECC1 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

RSVD
D8 (84) Reserved – 8'b0000_0000
0 0 0 0 0 0 0 0

RSVD
D9 (84) Reserved – 8'b0000_0000
0 0 0 0 0 0 0 0

ECC1_EN_ ECC1_CALC_
ECC1_CIN_TBB[5:0]
TBB CIN
E1 OTP ECC CTRL1 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ECC2_EN_ ECC2_CALC_
ECC2_CIN_TBB[5:0]
TBB CIN
E2 OTP ECC CTRL2 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ECC3_EN_ ECC3_CALC_
ECC3_CIN_TBB[5:0]
TBB CIN
E3 OTP ECC CTRL3 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ECC4_EN_ ECC4_CALC_
ECC4_CIN_TBB[5:0]
TBB CIN
E4 OTP ECC CTRL4 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ECC5_EN_ ECC5_CALC_
ECC5_CIN_TBB[5:0]
TBB CIN
E5 OTP ECC CTRL5 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ECC6_EN_ ECC6_CALC_
ECC6_CIN_TBB[5:0]
TBB CIN
E6 OTP ECC CTRL6 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ECC7_EN_ ECC7_CALC_
ECC7_CIN_TBB[5:0]
TBB CIN
E7 OTP ECC CTRL7 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ECC8_EN_ ECC8_CALC_
ECC8_CIN_TBB[5:0]
TBB CIN
E8 OTP ECC CTRL8 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

PF0100

116 NXP Semiconductors

 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 138. Extended Page 2 (continued)

BITS[7:0]
Address Register name TYPE Default
7 6 5 4 3 2 1 0

ECC9_EN_ ECC9_CALC_
ECC9_CIN_TBB[5:0]
TBB CIN
E9 OTP ECC CTRL9 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ECC10_EN_T ECC10_CALC
ECC10_CIN_TBB[5:0]
BB _CIN
EA OTP ECC CTRL10 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ANTIFUSE1_E ANTIFUSE1_L ANTIFUSE1_R

– – – – BYPASS1
N OAD W
F1 OTP FUSE CTRL1 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ANTIFUSE2_E ANTIFUSE2_L ANTIFUSE2_R

– – – – BYPASS2
N OAD W
F2 OTP FUSE CTRL2 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ANTIFUSE3_E ANTIFUSE3_L ANTIFUSE3_R

– – – – BYPASS3
N OAD W
F3 OTP FUSE CTRL3 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ANTIFUSE4_E ANTIFUSE4_L ANTIFUSE4_R

– – – – BYPASS4
N OAD W
F4 OTP FUSE CTRL4 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ANTIFUSE5_E ANTIFUSE5_L ANTIFUSE5_R

– – – – BYPASS5
N OAD W
F5 OTP FUSE CTRL5 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ANTIFUSE6_E ANTIFUSE6_L ANTIFUSE6_R

– – – – BYPASS6
N OAD W
F6 OTP FUSE CTRL6 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ANTIFUSE7_E ANTIFUSE7_L ANTIFUSE7_R

– – – – BYPASS7
N OAD W
F7 OTP FUSE CTRL7 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ANTIFUSE8_E ANTIFUSE8_L ANTIFUSE8_R

– – – – BYPASS8
N OAD W
F8 OTP FUSE CTRL8 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ANTIFUSE9_E ANTIFUSE99_ ANTIFUSE9_R

– – – – BYPASS9
N LOAD W
F9 OTP FUSE CTRL9 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

ANTIFUSE10_ ANTIFUSE10_ ANTIFUSE10_

– – – – BYPASS10
EN LOAD RW
FA OTP FUSE CTRL10 R/W 8'b0000_0000
0 0 0 0 0 0 0 0

Notes
84. Do not write in reserved registers.

PF0100

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TYPICAL APPLICATIONS

7 Typical applications

7.1 Introduction
Figure 35 provides a typical application diagram of the PF0100 PMIC together with its functional components. For details on component
references and additional components such as filters, refer to the individual sections.

7.1.1 Application diagram

VIN1
SW1FB SW1AB Output

PF0100
1.0uF
VIN1 Vin
VGEN1 4.7uF
SW1AIN
2.2uF VGEN1 100mA O/P
SW1A/B 1.0uH
Drive SW1ALX
Single/Dual
4.7uF VGEN2 VGEN2 2500 mA
Buck SW1BLX 2 x22uF
250mA
O/P
VIN2 Drive SW1BIN
1.0uF VIN2
4.7uF
VGEN3 Vin SW1C Output
VGEN3
2.2uF 100mA
SW1CLX 1.0uH
O/P
Drive SW1CIN
VGEN4 SW1C
4.7uF VGEN4 2000 mA 3 x 22uF
350mA 4.7uF
Buck Vin
SW1CFB
VIN3
1.0uF VIN3 Core Control logic SW1VSSSNS

VGEN5
SW2 Output
100mA
2.2uF
VGEN5 1.0uH
SW2LX
Initialization State Machine SW2 O/P SW2IN
VGEN6 2000 mA Drive
2.2uF VGEN6 Buck SW2IN 3 x 22uF
200mA Vin 4.7uF
SW2FB

OTP Supplies SW3AFB

SW3A Output
Control Vin
4.7uF
VDDOTP SW3AIN
O/P 2 x 22uF
VDDOTP 1.0uH
VDDIO SW3A/B Drive SW3ALX
VDDIO CONTROL Single/Dual
DDR
I2C 2500 mA
SW3BLX
0.1uF
4.7k

O/P
4.7k

Interface Buck Drive SW3BIN 1.0uH 2 x 22uF

SCL
To 4.7uF
MCU SDA Vin
SW3BFB SW3B Output
DVS CONTROL
SW3VSSSNS
DVS Control
SW4FB
SW4 Output
Vin
4.7uF
SW4 SW4IN
1000 mA O/P 3 x 22uF
I2C Buck Drive SW4LX
1.0uH
1uF
VCOREDIG
Register Trim-In-Package GNDREF1 Vin
10uF
2.2uH
220nF VCOREREF map
Reference SWBSTLX
Clocks and SWBST
1uF VCORE Generation SWBST O/P Vin Output
resets 600 mA Drive SWBSTIN
Boost 2 x 22uF
GNDREF
SWBSTFB 2.2uF

1uF VREFDDR
VSW3A
VINREFDDR

100nF Clocks
32kHz and 16MHz Package Pin Legend
VHALF

100nF Output Pin

Input Pin
Bi-directional Pin
Vin
VIN
1uF Best
Li Cell
of
Charger
LICELL Supply

100nF
VSNVS
Coin Cell
Battery
RESETBMCU
VSNVS

STANDBY

VSW2 VSW2 VSW2 VSW2

PWRON

SDWNB
ICTEST

100k

0.47uF
100k

100k

INTB

100k

To/From
AP

Figure 35. Typical application schematic

PF0100

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7.1.2 Bill of materials

The following table provides a complete list of the recommended components on a full featured system using the PF0100 Device for -40
°C to 85 °C applications. Components are provided with an example part number; equivalent components may be used.

Table 139. Bill of materials -40 °C to 85 °C applications (85)

Value Qty Description Part# Manufacturer Component/pin

PMIC

1 Power management IC MMPF0100 NXP

Buck, SW1AB - (0.300-1.875 V), 2.5 A

2.5 x 2 x 1.2
1.0 μH 1 ISAT = 3.4 A for 10% drop, DFE252012R-H-1R0M TOKO INC. Output inductor
DCRMAX = 49 mΩ

22 μH 4 10 V X5R 0603 GRM188R61A226ME15 Murata Output capacitance

4.7 μF 2 10 V X5R 0402 GRM155R61A475MEAA Murata Input capacitance

0.1 μF 1 10 V X5R 0201 GRM033R61A104ME84 Murata Input capacitance

Buck, SW1C - (0.300-1.875 V), 2.0 A

2.5 x 2 x 1.2
1.0 μH 1 ISAT = 3.0 A for 10% drop, DFE252012C-1R0M TOKO INC. Output inductor
DCRMAX = 59 mΩ

22 μF 3 10 V X5R 0603 GRM188R61A226ME15 Murata Output capacitance

4.7 μF 1 10 V X5R 0402 GRM155R61A475MEAA Murata Input capacitance

0.1 μF 1 10 V X5R 0201 GRM033R61A104ME84 Murata Input capacitance
Buck, SW2 - (0.400-3.300 V), 2.0 A

2.5 x 2 x 1.2
1.0 μH 1 ISAT = 3.0 A for 10% drop, DFE252012C-1R0M TOKO INC. Output inductor
DCRMAX = 59 mΩ

22 μF 3 10 V X5R 0603 GRM188R61A226ME15 Murata Output capacitance

4.7 μF 1 10 V X5R 0402 GRM155R61A475MEAA Murata Input capacitance

0.1 μF 1 10 V X5R 0201 GRM033R61A104ME84 Murata Input capacitance

Buck, SW3AB - (0.400-3.300 V), 2.5 A

2.5 x 2 x 1.2
1.0 μH 1 ISAT = 3.4 A for 10% drop, DFE252012R-1R0M TOKO INC. Output inductor
DCRMAX = 49 mΩ

22 μF 3 10 V X5R 0603 GRM188R61A226ME15 Murata Output capacitance

4.7 μF 2 10 V X5R 0402 GRM155R61A475MEAA Murata Input capacitance

0.1 μF 1 10 V X5R 0201 GRM033R61A104ME84 Murata Input capacitance

Buck, SW4 - (0.400-3.300V), 1.0 A

2 x 1.6 x 0.9
1.0 μH 1 ISAT = 2.0 A for 30% drop, LQM2MPN1R0MGH Murata Output inductor
DCRMAX = 80 mΩ

22 μF 3 10 V X5R 0603 GRM188R61A226ME15 Murata Output capacitance

4.7 μF 2 10 V X5R 0402 GRM155R61A475MEAA Murata Input capacitance

0.1 μF 1 10 V X5R 0201 GRM033R61A104ME84 Murata Input capacitance

PF0100

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Table 139. Bill of materials -40 °C to 85 °C applications (continued) (85)

Value Qty Description Part# Manufacturer Component/pin

BOOST, SWBST - 5.0 V, 600 mA

2 x 1.6 x 1
2.2 μH 1 DFE201610E-2R2M TOKO INC. Output inductor
ISAT = 2.4 A for 10% drop
22 μF 2 10 V X5R 0603 GRM188R61A226ME15D Murata Output capacitance

10 μF 3 10 V X5R 0402 GRM155R61A106ME11 Murata Input capacitance

2.2 μF 1 10 V X5R 0201 GRM033R61A225ME47 Murata Input capacitance

0.1 μF 1 10 V X5R 0201 GRM033R61A104KE84 Murata Input capacitance

1.0 A 1 DIODE SCH PWR RECT 1.0 A 20V SMT MBR120LSFT3G ON Semiconductor Schottky diode
LDO, VGEN1, 2, 3, 4, 5, 6

4.7 μF 1 10 V X5R 0402 GRM155R61A475MEAA Murata VGEN2,4 output capacitors

VGEN1,3,5,6 output
2.2 μF 1 10 V X5R 0201 GRM033R61A225ME47 Murata
capacitors

VGEN1,2,3,4,5,6 input
1.0 μF 1 10 V X5R 0402 GRM033R61A105ME44 Murata
capacitors
Miscellaneous

VCORE, VCOREDIG,
1.0 μF 1 10 V X5R 0402 GRM033R61A105ME44 Murata VREFDDR, VINREFDDR,
VIN capacitors

0.22 μF 1 10 V X5R 0201 GRM033R61A224ME90 Murata VCOREREF output capacitor

0.47 μF 1 10 V X5R 0201 GRM033R61A474ME90 Murata VSNVS output capacitor

VHALF, VINREFDDR,
0.1 μF 1 10 V X5R 0201 GRM033R61A104KE84 Murata
VDDIO, LICELL capacitors

100 kΩ 2 RES MF 100 k 1/16 W 1% 0402 RC0402FR-07100KL Yageo America Pull-up resistors
4.7 kΩ 2 RES MF 4.70K 1/20W 1% 0201 RC0201FR-074K7L Yageo America I2C pull-up resistors

Notes
85. NXP does not assume liability, endorse, or warrant components from external manufacturers referenced in circuit drawings or tables. While NXP
offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.

PF0100

120 NXP Semiconductors

 TYPICAL APPLICATIONS

The following table provides a complete list of the recommended components on a full featured system using the PF0100 Device for -40
°C to 105 °C applications. Components are provided with an example part number; equivalent components may be used.

Table 140. Bill of materials -40 °C to 105 °C applications (86)

Value Qty Description Part# Manufacturer Component/pin

PMIC

1 Power management IC MMPF0100 NXP

Buck, SW1AB - (0.300-1.875 V), 2.5 A

2.5 x 2 x 1.2
1.0 μH 1 ISAT = 3.4 A for 10% drop DFE252012R-H-1R0M TOKO INC. Output inductor
DCRMAX = 49 mΩ

22 μH 4 10 V X7T 0805 GRM21BD71A226ME44 Murata Output capacitance

4.7 μF 2 10 V X7S 0603 GRM188C71A475KE11 Murata Input capacitance

0.1 μF 1 10 V X7S 0201 GRM033C71A104KE14 Murata Input capacitance

Buck, SW1C - (0.300-1.875 V), 2.0 A

2 x 1.6 x 1
1.0 μH 1 DFE201610E-1R0M TOKO INC. Output inductor
ISAT = 2.9 A for 10% drop
22 μF 3 10 V X7T 0805 GRM21BD71A226ME44 Murata Output capacitance

4.7 μF 1 10 V X7S 0603 GRM188C71A475KE11 Murata Input capacitance

0.1 μF 1 10 V X7S 0201 GRM033C71A104KE14 Murata Input capacitance

Buck, SW1ABC - (0.300-1.875 V), 4.5 A

4.2 x 4.2 x 2
1.0 μH 1 ISAT = 5.1 A for 10% drop, FDSD0420-H-1R0M TOKO INC. Output inductor
DCRMAX = 29 mΩ

22 μF 6 10 V X7T 0805 GRM21BD71A226ME44 Murata Output capacitance

4.7 μF 2 10 V X7S 0603 GRM188C71A475KE11 Murata Input capacitance

0.1 μF 1 10 V X7S 0201 GRM033C71A104KE14 Murata Input capacitance

Buck, SW2 - (0.400-3.300 V), 2.0 A

2 x 1.6 x 1
1.0 μH 1 DFE201610E-1R0M TOKO INC. Output inductor
ISAT = 2.9 A for 10% drop

22 μF 3 10 V X7T 0805 GRM21BD71A226ME44 Murata Output capacitance

4.7 μF 1 10 V X7S 0603 GRM188C71A475KE11 Murata Input capacitance

0.1 μF 1 10 V X7S 0201 GRM033C71A104KE14 Murata Input capacitance

Buck, SW3AB - (0.400-3.300 V), 2.5 A

2 x 1.6 x 1
1.0 μH 1 DFE201610E-1R0M TOKO INC. Output inductor
ISAT = 2.9 A for 10% drop

22 μF 3 10 V X7T 0805 GRM21BD71A226ME44 Murata Output capacitance

4.7 μF 1 10 V X7S 0603 GRM188C71A475KE11 Murata Input capacitance

0.1 μF 1 10 V X7S 0201 GRM033C71A104KE14 Murata Input capacitance

Buck, SW4 - (0.400-3.300V), 1.0 A

2 x 1.6 x 1
1.0 μH 1 DFE201610E-1R0M Murata Output inductor
ISAT = 2.9 A for 30% drop
22 μF 3 10 V X7T 0805 GRM21BD71A226ME44 Murata Output capacitance

4.7 μF 1 10 V X7S 0603 GRM188C71A475KE11 Murata Input capacitance

0.1 μF 1 10 V X7S 0201 GRM033C71A104KE14 Murata Input capacitance

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Table 140. Bill of materials -40 °C to 105 °C applications (continued) (86)

Value Qty Description Part# Manufacturer Component/pin

BOOST, SWBST - 5.0 V, 600 mA

2 x 1.6 x 1
2.2 μH 1 DFE201610E-2R2M TOKO INC. Output inductor
ISAT = 2.4 A for 10% drop
22 μF 2 10 V X7T 0805 GRM21BD71A226ME44 Murata Output capacitance

10 μF 3 10 V X7T 0603 GRM188D71A106MA73 Murata Input capacitance

2.2 μF 1 10 V X7S 0402 GRM155C71A225KE11 Murata Input capacitance

0.1 μF 1 10 V X7S 0201 GRM033C71A104KE14 Murata Input capacitance

1.0 A 1 DIODE SCH PWR RECT 1A 20V SMT MBR120LSFT3G ON Semiconductor Schottky diode
LDO, VGEN1, 2, 3, 4, 5, 6

4.7 μF 1 10 V X7S 0603 GRM188C71A475KE11 Murata VGEN2,4 output capacitors

VGEN1,3,5,6 output
2.2 μF 1 10 V X7S 0402 GRM155C71A225KE11 Murata
capacitors

VGEN1,2,3,4,5,6 input
1.0 μF 1 10 V X7S 0402 GRM155C71A105KE11 Murata
capacitors
Miscellaneous

VCORE, VCOREDIG,
1.0 μF 1 10 V X7S 0402 GRM155C71A105KE11 Murata VREFDDR, VINREFDDR,
VIN capacitors

0.22 μF 1 10 V X7R 0402 GRM155R71A224KE01 Murata VCOREREF output capacitor

0.47 μF 1 10 V X7R 0402 GRM155R71A474KE01 Murata VSNVS output capacitor

VHALF, VINREFDDR,
0.1 μF 1 10 V X7S 0201 GRM033C71A104KE14 Murata
VDDIO, LICELL capacitors

100 kΩ 2 RES MF 100 k 1/16 W 1% 0402 RC0402FR-07100KL Yageo America Pull-up resistors
4.7 kΩ 2 RES MF 4.70K 1/20W 1% 0201 RC0201FR-074K7L Yageo America I2C pull-up resistors

Notes
86. NXP does not assume liability, endorse, or warrant components from external manufacturers referenced in circuit drawings or tables. While NXP
offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.

PF0100

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 TYPICAL APPLICATIONS

7.2 PF0100 layout guidelines

7.2.1 General board recommendations

1. It is recommended to use an eight layer board stack-up arranged as follows:
• High current signal
• GND
• Signal
• Power
• Power
• Signal
• GND
• High current signal
2. Allocate TOP and BOTTOM PCB Layers for POWER ROUTING (high current signals), copper-pour the unused area.
3. Use internal layers sandwiched between two GND planes for the SIGNAL routing.

7.2.2 Component placement

It is desirable to keep all component related to the power stage as close to the PMIC as possible, specially decoupling input and output
capacitors.

7.2.3 General routing requirements

1. Some recommended things to keep in mind for manufacturability:
• Via in pads require a 4.5 mil minimum annular ring. Pad must be 9.0 mils larger than the hole
• Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper
• Minimum allowed spacing between line and hole pad is 3.5 mils
• Minimum allowed spacing between line and line is 3.0 mils
2. Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from power,
clock, or high power signals, like the ones on the SWxIN, SWx, SWxLX, SWBSTIN, SWBST, and SWBSTLX pins. They could be
also shielded.
3. Shield feedback traces of the regulators and keep them as short as possible (trace them on the bottom so the ground and power
planes shield these traces).
4. Avoid coupling traces between important signal/low noise supplies (like REFCORE, VCORE, VCOREDIG) from any switching node
(i.e. SW1ALX, SW1BLX, SW1CLX, SW2LX, SW3ALX, SW3BLX, SW4LX, and SWBSTLX).
5. Make sure all components related to a specific block are referenced to the corresponding ground.

7.2.4 Parallel routing requirements

1. I2C signal routing
• CLK is the fastest signal of the system, so it must be given special care.
• To avoid contamination of these delicate signals by nearby high power or high frequency signals, it is a good practice to
shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole signal
trace length.

PF0100

NXP Semiconductors 123

TYPICAL APPLICATIONS

Figure 36. Recommended shielding for critical signals

• These signals can be placed on an outer layer of the board to reduce their capacitance with respect to the ground plane.
• Care must be taken with these signals not to contaminate analog signals, as they are high frequency signals. Another good
practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals.

7.2.5 Switching regulator layout recommendations

1. Per design, the switching regulators in PF0100 are designed to operate with only one input bulk capacitor. However, it is
recommended to add a high frequency filter input capacitor (CIN_hf), to filter out any noise at the regulator input. This capacitor
should be in the range of 100 nF and should be placed right next to or under the IC, closest to the IC pins.
2. Make high-current ripple traces low-inductance (short, high W/L ratio).
3. Make high-current traces wide or copper islands.
4. Make high-current traces symetrical for dual–phase regulators (SW1, SW3).

VIN

SWxIN

CIN_HF CIN

SWxLX SWx
Driver Controller
L

COUT

SWxFB
Compensation

Figure 37. Generic buck regulator architecture

PF0100

124 NXP Semiconductors

 TYPICAL APPLICATIONS

Figure 38. Layout example for buck regulators

7.3 Thermal information

7.3.1 Rating data

The thermal rating data of the packages has been simulated with the results listed in Table 6.
Junction to ambient thermal resistance nomenclature: the JEDEC specification reserves the symbol RθJA or θJA (Theta-JA) strictly for
junction-to-ambient thermal resistance on a 1s test board in natural convection environment. RθJMA or θJMA (Theta-JMA) is used for both
junction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and 2s2p
test boards. It is anticipated the generic name, Theta-JA, continues to be commonly used.
The JEDEC standards can be consulted at http://www.jedec.org.

7.3.2 Estimation of junction temperature

An estimation of the chip junction temperature TJ can be obtained from the equation:
TJ = TA + (RθJA x PD)
with:
TA = Ambient temperature for the package in °C
RθJA = Junction to ambient thermal resistance in °C/W
PD = Power dissipation in the package in W
The junction to ambient thermal resistance is an industry standard value providing a quick and easy estimation of thermal performance.
Unfortunately, there are two values in common usage: the value determined on a single layer board RθJA and the value obtained on a four
layer board RθJMA. Actual application PCBs show a performance close to the simulated four layer board value although this may be
somewhat degraded in case of significant power dissipated by other components placed close to the device.
At a known board temperature, the junction temperature TJ is estimated using the following equation
TJ = TB + (RθJB x PD) with
TB = Board temperature at the package perimeter in °C
RθJB = Junction to board thermal resistance in °C/W
PD = Power dissipation in the package in W
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.
See 6 Functional block requirements and behaviors, page 18 for more details on thermal management.

PF0100

NXP Semiconductors 125

PACKAGING

8 Packaging

8.1 Packaging dimensions

Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and
perform a keyword search for the drawing’s document number. See the 4.2 Thermal characteristics, page 11 section for specific thermal
characteristics for each package.

Table 141. Package drawing information

Package Suffix Package outline drawing number

56 QFN 8x8 mm - 0.5 mm pitch. E-Type (full lead) EP 98ASA00405D
56 QFN 8x8 mm - 0.5 mm pitch. WF-Type (wettable flank) ES 98ASA00589D

PF0100

126 NXP Semiconductors

 PACKAGING

PF0100

NXP Semiconductors 127

PACKAGING

PF0100

128 NXP Semiconductors

 PACKAGING

PF0100

NXP Semiconductors 129

PACKAGING

PF0100

130 NXP Semiconductors

 PACKAGING

PF0100

NXP Semiconductors 131

PACKAGING

PF0100

132 NXP Semiconductors

 PACKAGING

PF0100

NXP Semiconductors 133

REFERENCE SECTION

9 Reference section

9.1 Reference documents

Table 142. PF0100 reference documents

Reference Description
AN4536 MMPF0100 OTP programming instructions

PF0100

134 NXP Semiconductors

 REVISION HISTORY

10 Revision history

Revision Date Description of changes

1 7/2011 • Preliminary specification release

2 8/2012 • NPI phase: prototype major updates throughout cycle

3 10/2012 • Initial production release

4 5/2013 • Table 4. Added recommended pin connection when regulators are unused
• Update Table 9. Current Consumption summary
• Table 10. Removed VREFDDR_VOLT row
• Removed automatic fuse programming feature
• Updated Max frequency specification for the 16 MHz clock to 17.2 MHz
• Table 17. Added specification for derived 2.0 Mhz clock
• Added Clock adjustment
• Table 22. Updated VREFDDR minimum Current limit specification
• Updated Block diagram for all Switching Regulators
• Updated current limit and overcurrent protection minimum specification on LDOS
• Table 111. Update VTH0 and VTL0 specification on VSNVS
• Updated Table 137, Address FF
• Updated Table 138, address D8 and D9
• Update Figure 35. Typical application diagram
• Removed Part Identification section
5 7/2013 • Added part numbers to the ordering information for the MMPF0100A
• Added corrections and notes to the document to accomodate the new part numbers, where identified
by MMPF0100A
• VIN threshold (coin cell powered to VIN powered) Max. changed to 3.1
6 8/2013 • Removed LICELL connection to VIN on PF0100A
• Removed 4.7 μF LICELL bypass capacitor as coin cell replacement
7 12/2013 • Updated typical and max Off Current
• Add bypass capacitor in VDDIO
• Added industrial part numbers PMPF0100xxANES
• Added parts F3 and F4
• Added Table 3, Ambient temperature range and updated specification headers accordingly.
• Increased max standby and sleep currents on Extended Industrial parts.
• Update output accuracy on SW1A/B, SW1C, SW2, SW3A/B and SW4.
• Corrected the default value on DEVICEID register, bit4 (unused) from 0 to 1.
• Corrected default register values on Table 118.
• Added VDDIO capacitor to Miscellaneous in the BOM
8 4/2014 • Corrected VDDOTP maximum rating
• Corrected SWBSTFB maximum rating
• Corrected inductor Isat for SW1ABC single phase mode from 4.5 A to 6.0 A
• Added note to clarify SWBST default operation in Auto mode
• Corrected default value of bits in SILICONREVID register in Table 136
• Changed VSNVS current limit for PF0100A
• Noted that voltage settings 0.6V and below are not supported
• VSNVS Turn On Delay (td1) spec corrected from 15 ms to 5.0 ms
• Updated per GPCN 16298
6/2014 • Corrected GPCN number in the revision history table (16220 changed to 16298)

9 7/2014 • Updated VTL1, VTH1, and VSNVSCROSS threshold specifications

• Added F6 part
• Changes documented in GPCN 16369
• Added new part numbers MMPF0100F9ANES and MMPF0100FAANES to Table 1
10 7/2015
• Updated Table 10
11 8/2015 • Removed MMPF0100F3EP and MMPF0100F4EP from Orderable Parts table

PF0100

NXP Semiconductors 135

REVISION HISTORY

Revision Date Description of changes

• Updated Table 53
• Updated Table 62
• Updated Table 77
• Updated Table 86
• Fixed typo in Table 138
• Updated Table 139
• Added Table 140
12 9/2015
• Corrected the default register value for SW1ABMODE in Table 46
• Corrected the default register value for SW1CMODE in Table 51
• Corrected the default register value for SW2MODE in Table 60
• Corrected the default register value for SW3AMODE in Table 70
• Corrected the default register value for SW3BMODE in Table 75
• Corrected the default register value for SW4MODE in Table 84
• Updated Figure 35
• Removed MMPF0100NPEP, MMPF0100F0EP, MMPF0100F1EP, and MMPF0100F2EP from
Orderable Part Variations. No longer manufactured.
13 12/2015
• Updated Table 10
• Reformatted to newer template form and style
14 3/2016 • Updated SW2 current capability from 2000 mA to 2500 mA for F9/FA versions

15 5/2016 • Changed Table 10 row - Default I2C Address from 0x80 to 0x08 for F9 and FA
• Added NP version to OTP's with SW2 current capability of 2500 mA
16 9/2016 • Added MMPF0100FBANES part number to Table 1
• Added FB OTP option to Table 10
• Added MMPF0100FCAEP, MMPF0100FDAEP, and MMPF0100FCANES part numbers to Table 1
17 1/2017
• Added OTP configurations for FC and FD to Table 10
• Updated 98ASA00405D drawing as per PCN 201906034F01
18 7/2019
• Changed document status from Advance Information to Technical Data
19 4/2022 • Added 98ASA00405D optional bottom view page for E-type package as per CIN 202204010I
• Table 139: replaced Freescale by NXP
20 5/2022
• Table 140: replaced Freescale by NXP

PF0100

136 NXP Semiconductors

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Document Number: MMPF0100

Rev. 20
5/2022