R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

SEMESTER – I

S. No. Course Course Name Category Hours per week Credits

codes L T P
1. CMOS Analog IC Design PC 3 0 0 3
2. CMOS Digital IC Design PC 3 0 0 3
Program Elective – I
3. Microchip Fabrication Techniques
Scripting Languages for VLSI PE 3 0 0 3
CAD for VLSI
Program Elective – II PE 3 0 0 3
Device Modelling
4. FPGA Architectures and Applications
ASIC Design
5. CMOS Analog IC Design Lab PC 0 0 4 2
6. CMOS Digital IC Design Lab PC 0 0 4 2
7. Research Methodology and IPR MC 2 0 0 2
8. RTL Synthesis, Simulation and Verification SE 0 1 2 2
Audit Course – I
9. AC 2 0 0 0

Total 20

1
 R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

SEMESTER – II

S. No. Course Course Name Category Hours per week Credits

codes L T P
1. CMOS Mixed Signal IC Design PC 3 0 0 3
2. Physical Design Automation PC 3 0 0 3
Program Elective – III PE 3 0 0 3
3. SoC Testing and Verification
Semiconductor Memory Design and Testing
Advanced VLSI interconnects
Program Elective – IV PE 3 0 0 3
4. Low Power VLSI Design
Algorithms for VLSI Design
VLSI Signal Processing
5. CMOS Mixed Signal IC Design Lab PC 0 0 4 2
6. Physical Design Automation Lab PC 0 0 4 2
7. Quantum Technologies and Applications MC 2 0 0 2
8. Comprehensive Viva Voce PC 0 0 0 2
Audit Course – II AC 2 0 0 0

9.

Total 20

2
 R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

SEMSTER - III

S. No. Course Course Name Category Hours per week Credits

codes L T P
1. Program Elective – V PE 3 0 0 3
Bi-CMOS Technology and Applications
Optimization Techniques and Applications in VLSI
Design
SoC Architecture
2. Open Elective – I OE 3 0 0 3
IoT and its Applications
3. Dissertation Phase – I PR 0 0 20 10
4. Industry Internship 0 0 0 2
5. Co-curricular Activities 0 0 0 1
Total 19

SEMESTER - IV

S. No. Course Course Name Category Hours per week Credits

codes L T P
1. Dissertation Phase – II PR 0 0 32 16
Total 16

3
 R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

Course Code CMOS ANALOG IC DESIGN L T P C

3 0 0 3
Semester I

Course Objectives:
 This course focuses on theory, analysis and design of analog integrated circuits in both
Bipolar and Metal-Oxide-Silicon (MOS) technologies.
 Basic design concepts, issues and tradeoffs involved in analog IC design are explored.
 Intuitive understanding and real-life applications are emphasized throughout the course.
 To learn about Design of CMOS Op Amps, Compensation of Op Amps, Design of Two-
Stage Op Amps, Power Supply Rejection Ratio of Two-Stage Op Amps, Cascade Op Amps,
Measurement Techniques of OP Amp.
 To know about Characterization of Comparator, Two-Stage, Open-Loop Comparators,
Improving the Performance of Open-Loop Comparators, Discrete-Time Comparators etc.
Course Outcomes (CO): Student will be able to
 Design MOSFET based analog integrated circuits.
 Analyze analog circuits at least to the first order.
 Appreciate the trade-offs involved in analog integrated circuit design.
 Understand and appreciate the importance of noise and distortion in analog circuits.
 Analyze complex engineering problems critically in the domain of analog IC design for
conducting research.
 Solve engineering problems for feasible and optimal solutions in the core area
UNIT - I Lecture Hrs:
Basic MOS Device Physics: General Considerations, MOS I/V Characteristics, Second Order
effects, MOS Device models and MOS Capacitor. Short Channel Effects and Device Models. Single
Stage Amplifiers – Basic Concepts, Common Source Stage, Source Follower, Common Gate Stage,
Cascode Stage.
UNIT - II Lecture Hrs:
Differential Amplifiers: Single Ended and Differential Operation, Basic Differential Pair, Common
Mode Response, Differential Pair wit MOS loads, Gilbert Cell. Passive and Active Current Mirrors
– Basic Current Mirrors, Cascode Current Mirrors, Active Current Mirrors. Current Steering Circuit.
UNIT - III Lecture Hrs:
Frequency Response of Amplifiers: General Considerations, Common Source Stage, Source
Followers, Common Gate Stage, Cascode Stage, Differential Pair. Noise – Types of Noise,
Representation of Noise in circuits, Noise in single stage amplifiers, Noise in Differential Pairs.
UNIT - IV Lecture Hrs:
Feedback Amplifiers: General Considerations, Feedback Topologies, Effect of Loading.
Operational Amplifiers – General Considerations, One Stage Op Amps, Two Stage Op Amps, Gain
Boosting, Common – Mode Feedback, Input Range limitations, Slew Rate, Power Supply Rejection,
Noise in Op Amps, Stability and Frequency Compensation.
UNIT - V Lecture Hrs:
Operational Amplifiers: One Stage Op-Amp, Two Stage Op-Amp, Gain Boosting, Common Mode
Feed-Back, Input Range Limitations, Slew Rate, PSRR. Compensation of Two Stage Op-Amp,
Slewing in Two Stage Op-Amp, Compensation Techniques. Design Procedure for 2-Stage Op-Amp.
Textbooks:
1. B.Razavi, “Design of Analog CMOS Integrated Circuits”, 2nd Edition, McGraw Hill Edition 2016.
2. Paul.R.Gray & Robert G. Meyer, “Analysis and Design of Analog Integrated Circuits”, Wiley,
5thEdition, 2009.
Reference Books:
4
 R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

1.T.C.Carusone, D.A.Johns&K.Martin, “Analog Integrated Circuit Design”, 2ndEdition, Wiley, 2012.

2. P.E.Allen&D.R.Holberg, “CMOS Analog Circuit Design”, 3 rd Edition, Oxford University Press,
2011.
3. R.Jacob Baker, “CMOS Circuit Design, Layout, and Simulation”, 3rdEdition, Wiley, 2010.
4. Adel S. Sedra, Kenneth C. Smith, Arun, “Microelectronic Circuits”, 6 thEdition, Oxford University
Press.

5
 R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

Course Code CMOS DIGITAL IC DESIGN L T P C

3 0 0 3
Semester I

Course Objectives:
 To understand the fundamental properties of digital Integrated circuits using basic MOSFET
equations and to develop skills for various logic circuits using CMOS related design styles.
 The course also involves analysis of performance metrics.
 To teach fundamentals of CMOS Digital integrated circuit design such as importance of
Pseudo logic, Combinational MOS logic circuits and Sequential MOS logic circuits.
 To teach the fundamentals of Dynamic logic circuits and basic semiconductor memories
which are the basics for the design of high performance digital integrated circuits.
Course Outcomes (CO): Student will be able to
 Demonstrate advanced knowledge in Static and dynamic characteristics of CMOS,
 Estimate Delay and Power of Adders circuits.
 Classify different semiconductor memories.
 Analyze, design and implement combinational and sequential MOS logic circuits.
 Analyze complex engineering problems critically in the domain of digital IC design for
conducting research.
 Solve engineering problems for feasible and optimal solutions in the core area of digital ICs
UNIT - I Lecture Hrs:
MOS Design Pseudo NMOS Logic: Inverter, Inverter threshold voltage, Output high voltage,
Output Low voltage, Gain at gate threshold voltage, Transient response, Rise time, Fall time, Pseudo
NMOS logic gates, Transistor equivalency, CMOS Inverter logic.
UNIT - II Lecture Hrs:
Combinational MOS Logic Circuits: MOS logic circuits with NMOS loads, Primitive CMOS logic
gates–NOR & NAND gate, Complex Logic circuits design–Realizing Boolean expressions using
NMOS gates and CMOS gates, AOI and OIA gates, CMOS full adder, CMOS transmission gates,
Designing with Transmission gates.
UNIT - III Lecture Hrs:
Sequential MOS Logic Circuits: Behavior of bistable elements, SR Latch, Clocked latch and flip
flop circuits, CMOS D latch and edge triggered flip-flop
UNIT - IV Lecture Hrs:
Dynamic Logic Circuits: Basic principle, Voltage Bootstrapping, Synchronous dynamic pass
transistor circuits, Dynamic CMOS transmission gate logic, High performance Dynamic CMOS
circuits.
UNIT - V Lecture Hrs:
Semiconductor Memories: Types, RAM array organization, DRAM – Types, Operation, Leakage
currents in DRAM cell and refresh operation, SRAM operation Leakage currents in SRAM cells,
Flash Memory-NOR flash and NAND flash.
Textbooks:
1. Neil Weste, David Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”, 4 th
Edition, Pearson, 2010
2. Digital Integrated Circuit Design – Ken Martin, Oxford University Press, 2011.
3. CMOS Digital Integrated Circuits Analysis and Design – Sung-Mo Kang, Yusuf Leblebici,
TMH, 3rd Edition, 2011.
Reference Books:
1. Introduction to VLSI Systems: A Logic, Circuit and System Perspective – Ming-BO Lin, CRC
Press, 2011

6
 R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

2. Digital Integrated Circuits – A Design Perspective, Jan M.Rabaey, Anantha Chandrakasan,

Borivoje Nikolic, 2ndEdition, PHI.

7
 R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

Course Code MICROCHIP FABRICATION TECHNIQUES L T P C

Program Elective – I 3 0 0 3
Semester I

Course Objectives:
 Comprehend impact of semiconductor industry on the design of development of integrated
circuits.
 Acquaint with clean room technology
 Understand oxidation methods, aspects of photolithography, diffusion, ion implantation
techniques.
 Specify NMOS and CMOS design rules corresponding to 180nm, 90nm and
45nm technologies
 Understand packaging principles
Course Outcomes (CO): Student will be able to
 Understand various stages of fabrication
 Understand Various packaging techniques and Design rules.
 Classify various thin films and its characteristics.
UNIT - I Lecture Hrs:
Introduction to Processing: Overview of semiconductor industry, Stages of Manufacturing, Process
and product trends, Crystal growth, Basic wafer fabrication operations, process yields,
Semiconductor material preparation, Yield measurement, Contamination sources, Clean room
construction.
UNIT - II Lecture Hrs:
Photolithography: Oxidation and Photolithography, Ten step patterning process, Photoresists,
physical properties of photoresists, Storage and control of photoresists, photo masking process, Hard
bake, develop inspect, Dry etching Wet etching, resist stripping.
UNIT - III Lecture Hrs:
Diffusion & Ion Implantation: Doping and depositions: Diffusion process steps, deposition, Drive-
in oxidation, Ion implantation-1, Ion implantation-2.
UNIT - IV Lecture Hrs:
Film Depositions and Growth: Metallization, CVD basics, CVD process steps, Low pressure CVD
systems, Plasma enhanced CVD systems, Vapour phase epitaxy, molecular beam epitaxy.
UNIT - V Lecture Hrs:
Yield: Design rules and Scaling, BICMOS ICs: Choice of transistor types, PNP transistors,
Resistors, capacitors.
Packaging: Chip characteristics, package functions, package operations.
Textbooks:
1. Peter Van Zant, Microchip fabrication, McGraw Hill, 1997.
2. Plummer, J.D., Deal, M.D. and Griffin, P.B., “Silicon VLSI Technology: Fundamentals, Practice
and Modeling”, 3rd Ed., Prentice-Hall, 2000.
Reference Books
1.C.Y. Chang and S.M. Sze, ULSI technology, McGraw Hill, 2000
2. S.K. Gandhi, VLSI Fabrication principles, John Wiley and Sons, NY, 1994
3. S.M. Sze, VLSI technology, McGraw-Hill Book company, NY, 1988

8
 R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

Course Code SCRIPTING LANGUAGES FOR VLSI L T P C

Program Elective – I 3 0 0 3
Semester I

Course Objectives:
 Learn programming with scripting languages
 Understand how to create and run scripts using PERL/TCL/PYTHON in CAD Tools
 Gain knowledge about PERL/PYTHON/ TCL in developing system and web applications
 Develop skill to design a real time project using PERL/PYTHON
Course Outcomes (CO): Student will be able to
 Gain fluency in programming with scripting languages
 Create and run scripts using PERL/TCL/PYTHON in CAD Tools
 Demonstrate the use of PERL/PYTHON/ TCL in developing system and web applications
 Develop a real time project using PERL/PYTHON
UNIT - I Lecture Hrs:
Introduction to Scripts and Scripting: Basics of Linux, Origin of Scripting languages, scripting
today, Characteristics and uses of scripting languages.

UNIT - II Lecture Hrs:

PERL: Introduction to PERL, Names and values, Variables and assignment, Scalar expressions,
Control structures, Built-in functions, Collections of Data, Working with arrays, Lists and hashes,
Simple input and output, Strings, Patterns and regular expressions, Subroutines, Scripts with
arguments.
UNIT - III Lecture Hrs:
Advanced PERL: Finer points of Looping, Subroutines, Using Pack and Unpack, Working with
files, Type globs, Eval, References, Data structures, Packages, Libraries and modules, Objects and
modules in action, Tied variables, interfacing to the operating systems, Security issues.
UNIT - IV Lecture Hrs:
TCL: The TCL phenomena, Philosophy, Structure, Syntax, Parser, Variables and data in TCL,
Control flow, Data structures, Simple input/output, Procedures, Working with Strings, Patterns, Files
and Pipes, Example code.
UNIT - V Lecture Hrs:
Advanced TCL: The eval, source, exec and up-level commands, Libraries and packages,
Namespaces, Trapping errors, Event-driven programs, Making applications 'Internet-aware', 'Nuts-
and-bolts' internet programming, Security issues, TCL and TK integration.
PYTHON: Introduction to PYTHON language, PYTHON-syntax, statements, functions, Built-in
functions and Methods, Modules in PYTHON, Exception Handling.
Textbooks:
1.The World of Scripting Languages- David Barron, Wiley Student Edition.
2.PYTHON Web Programming, Steve Holden and David Beazley, New Riders Publications.

Reference Books:
1. TCL/TK: A Developer's Guide- ClifFlynt, Morgan Kaufmann Series.
2. Core PYTHON Programming, Chun, Pearson Education.
3. Learning Perl, Randal L. Schwartz, O’ Reilly publications 6th edition.
4. Linux: The Complete Reference”, Richard Peterson McGraw Hill Publications, 6th Edition.

9
 R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

Course Code CAD FOR VLSI L T P C

Program Elective – I 3 0 0 3
Semester I

Course Objectives:
 To understand the various phases of CAD for digital electronic systems, from digital logic
simulation to physical design, including test and verification.
 To demonstrate knowledge and understanding of fundamental concepts in CAD and to
establish capability for CAD tool development and enhancement.
 To practice the application of fundamentals of VLSI technologies
 To optimize the implemented design for area, timing and power by applying suitable
constraints.
Course Outcomes (CO): Student will be able to
 Establish comprehensive understanding of the various phases of CAD for digital electronic
systems, from digital logic simulation to physical design, including test and verification.
 Demonstrate knowledge and understanding of fundamental concepts in CAD and to establish
capability for CAD tool development and enhancement.
 Practice the application of fundamentals of VLSI technologies
 Optimize the implemented design for area, timing and power by applying suitable constraints.
UNIT - I Lecture Hrs:
Introduction: VLSI Design Cycle, New Trends in VLSI Design Cycle, Physical Design Cycle, New
Trends in Physical Design Cycle, Design Styles, System Packaging Styles.
UNIT - II Lecture Hrs:
Partitioning: Partitioning, Pin Assignment and Placement: Partitioning – Problem formulation,
Classification of Partitioning algorithms, Kernighan-Lin Algorithm, Simulated Annealing.
UNIT - III Lecture Hrs:
Floor Planning: Floor Planning – Problem formulation, Classification of floor planning algorithms,
constraint based floor planning, Rectangular Dualization, Pin Assignment – Problem formulation,
Classification of pin assignment algorithms, General and channel Pin assignments.
UNIT - IV Lecture Hrs:
Placement and Routing: Placement–Problem formulation, Classification of placement algorithms,
Partitioning based placement algorithms.
Global Routing and Detailed Routing: Global Routing – Problem formulation, Classification of
global routing algorithms, Maze routing algorithms, Detailed Routing – Problem formulation,
Classification of routing algorithms, Single layer routing algorithms.
UNIT - V Lecture Hrs:
Physical Design Automation of FPGAs and MCMs: FPGA Technologies, Physical Design cycle
for FPGAs, Partitioning, Routing – Routing Algorithm for the Non-Segmented model, Routing
Algorithms for the Segmented Model; Introduction to MCM Technologies, MCM Physical Design
Cycle.
Textbooks:
1. Algorithms for VLSI Physical Design Automation by Naveed Shervani,3 rdEdition, 2005,
Springer International Edition.
2. CMOS Digital Integrated Circuits Analysis and Design – Sung-Mo Kang, Yusuf Leblebici,
TMH, 3rd Ed., 2011.

Reference Books:
1. VLSI Physical Design Automation-Theory and Practice by Sadiq M Sait, Habib Youssef, World
10
 R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

Scientific.
2. Algorithms for VLSI Design Automation, S. H. Gerez, 1999, Wiley student Edition, John Wiley
and Sons (Asia) Pvt. Ltd.
3. VLSI Physical Design Automation by Sung Kyu Lim, Springer International Edition

11
 R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

Course Code DEVICE MODELLING L T P C

Program Elective – II 3 0 0 3
Semester I

Course Objectives:
 To understand the physics of 2-terminal MOS operation and its characteristics
 To understand the physics of 4-terminal MOSFET operation and its characteristics.
 To analyze the SOI MOSFET electrical characteristics.
Course Outcomes (CO): Student will be able to
 Understand the physics of 2-terminal MOS operation and its characteristics
 Understand the physics of 4-terminal MOSFET operation and its characteristics.
 Analyze the SOI MOSFET electrical characteristics.
UNIT - I Lecture Hrs:
2-terminal MOS device: threshold voltage modelling (ideal case as well as considering the effects of
of, Φms and Dit.).
UNIT - II Lecture Hrs:
C-V characteristics (ideal case as well as taking into account the effects of Qf, Φms and Dit); MOS
capacitor as a diagnostic tool (measurement of non-uniform doping profile, estimation of Qf, Φms
and Dit)
UNIT - III Lecture Hrs:
4-terminal MOSFET: threshold voltage (considering the substrate bias); above threshold I-V
modelling (SPICE level 1,2,3 and 4).
UNIT - IV Lecture Hrs:
Sub threshold current model; scaling; effect of threshold tailoring implant (analytical modelling of
threshold voltage using box approximation); buried channel MOSFET. Short channel, DIBL and
narrow width effects; small signal analysis of MOSFETs (Meyer’s model)
UNIT - V Lecture Hrs:
SOI MOSFET: Basic structure; threshold voltage modelling Advanced topics: hot carriers in
channel; EEPROMs; CCDs; high-K gate dielectrics.
Textbooks:
1. S. M. Sze, Physics of Semiconductor Devices, (2e), Wiley Eastern, 1981.
2. M. Lundstrom, Fundamentals of Nano transistors, World Scientific Publishing Co Pte Ltd
2017.
Reference Books
1. Y. P. Tsividis, Operation and Modelling of the MOS Transistor, McGraw-Hill, 1987.
2. E. Takeda, Hot-carrier Effects in MOS Transistors, Academic Press, 1995.
3. J. P. Colinge, “FinFETs and Other Multi-Gate Transistors,” Springer. 2009

12
 R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

Course Code FPGA ARCHITECTURES AND APPLICATIONS L T P C

Program Elective – II 3 0 0 3
Semester I

Course Objectives:
 To acquire knowledge about various architectures and device technologies of PLD’s.
 To comprehend FPGA Architectures.
 To analyze System level Design and their application for Combinational and Sequential
Circuits.
 To familiarize with Anti-Fuse Programmed FPGAs.
 To apply knowledge of this subject for various design applications.
Course Outcomes (CO): Student will be able to
 Acquire knowledge about various architectures and device technologies of PLD’s.
 Comprehend FPGA Architectures.
 Analyze System level Design and their application for Combinational and Sequential
Circuits.
 Familiarize with Anti-Fuse Programmed FPGAs.
 Apply knowledge of this subject for various design applications.
UNIT - I Lecture Hrs:
Introduction to Programmable Logic Devices: Introduction, Simple Programmable Logic Devices
– Read Only Memories, Programmable Logic Arrays, Programmable Array Logic, Programmable
Logic Devices/Generic Array Logic; Complex Programmable Logic Devices–Architecture of Xilinx
Cool Runner XCR3064XL CPLD, CPLD Implementation of a Parallel Adder with Accumulation.
UNIT - II Field Programmable Gate Arrays Lecture Hrs:
Field Programmable Gate Arrays: Organization of FPGAs, FPGA Programming Technologies,
Programmable Logic Block Architectures, Programmable Interconnects, and Programmable I/O
blocks in FPGAs, Dedicated Specialized Components of FPGAs, and Applications of FPGAs.
UNIT - III Lecture Hrs:
SRAM Programmable FPGAs: Introduction, Programming Technology, Device Architecture, the
Xilinx XC2000, XC3000 and XC4000 Architectures.
UNIT - IV Lecture Hrs:
Anti-Fuse Programmed FPGAs: Introduction, Programming Technology, Device Architecture,
The Actel ACT1, ACT2 and ACT3 Architectures.
UNIT - V Lecture Hrs:
Design Applications: General Design Issues, Counter Examples, A Fast Video Controller, A
Position Tracker for a Robot Manipulator, A Fast DMA Controller, Designing Counters with ACT
devices, Designing Adders and Accumulators with the ACT Architecture
Textbooks:
1. Field Programmable Gate Array Technology - Stephen M. Trimberger, Springer International
Edition.
2. Digital Systems Design - Charles H. Roth Jr, Lizy Kurian John, Cengage Learning.
Reference Books:
1. Field Programmable Gate Arrays-John V. Oldfield, Richard C. Dorf, Wiley India.
2. Digital Design Using Field Programmable Gate Arrays - Pak K. Chan/Samiha Mourad, Pearson
Low Price Edition.
3. Digital Systems Design with FPGAs and CPLDs-Ian Grout, Elsevier, Newnes.
4. FPGA based System Design-Wayne Wolf, Prentice Hall Modern Semiconductor Design Series.

13
 R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

Course Code ASIC DESIGN L T P C

Program Elective – II 3 0 0 3
Semester I

Course Objectives:
 To understand different types of ASICs and their libraries.
 To understand about programmable ASICs, I/O modules and their interconnects.
 To familiarize different methods of software ASIC design their simulation, testing and
construction of ASICs.
Course Outcomes (CO): Student will be able to
 Understand different types of ASICs and their libraries.
 Understand about programmable ASICs, I/O modules and their interconnects.
 Familiarize different methods of software ASIC design their simulation, testing and
construction of ASICs.
UNIT - I Lecture Hrs:
Introduction to ASICs: Types of ASICs, Design Flow, Case Study, Economics of ASICs, ASIC
Cell Libraries, Transistors as resistors, Transistor Parasitic Capacitance, Logical Effort, Library Cell
Design, Library Architecture, Gate-Array Design, Standard Cell Design, Data Path Cell Design.
UNIT - II Lecture Hrs:
Programmable ASICs and Programmable ASIC Logic Cells: The Anti fuse, Static Ram, EPROM
and EEPROM Technology, Practical Issues, Specifications, PREDP Benchmarks, FPGA Economics,
Actel ACT, Xilinx LCA, Altera Flex, Altera Max.
UNIT - III Lecture Hrs:
I/O Cells and Interconnects & Programmable ASIC Design Software: DC Output, AC Output,
DC input, AC input, Clock input, Power input, Xilinx I/O block, Other I/O Cells, Actel ACT, Xilinx
LCA, Xilinx EPLD, Altera Max 5000 and 7000, Altera Max 9000, Altera FLEX, Design Systems,
Logic Synthesis, The Half gate ASIC.
UNIT - IV Lecture Hrs:
Low Level Design Entry and Logic Synthesis: Schematic Entry, Low level Design Languages,
PLA Tools, EDIF, A logic synthesis example, A Comparator/MUX, Inside a Logic Synthesizer,
Synthesis of Viterbi Decoder, Verilog and Logic synthesis, VHDL and Logic Synthesis, Finite State
Machine Synthesis, Memory Synthesis, The Engine Controller, Performance Driven Synthesis,
Optimization of the viterbi decoder.
UNIT - V Lecture Hrs:
Simulation, Test and ASIC Construction: Types of Simulation, The Comparator/MUX Example,
Logic Systems, How Logic Simulation Works, Cell Models, Delay Models, Static Timing Analysis,
Formal Verification, Switch Level Simulation, Transistor Level Simulation, The importance of test,
Boundary Scan Test, Faults, Faults Simulation, Automatic Test Pattern Generator, Scan Test, Built in
Self-Test, A simple test Example, Physical Design, CAD Tools, System Partitioning, Estimating
ASIC Size, Power Dissipation, FPGA Partitioning, Partitioning Methods
Textbooks:
1. Michael John Sebastian Smith, “Application Specific Integrated Circuits”, Pearson Education,
2003.
2. L.J. Herbst, “Integrated Circuit Engineering”, Oxford Science Publications, 1996.
Reference Books:
1. Himanshu Bhatnagar, “Advanced ASIC Chip Synthesis using Synopsis Design Compiler”, 2nd
Edition, Kluwer Academic, 2001.

14
 R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

Course Code CMOS ANALOG IC DESIGN LAB L T P C

0 0 4 2
Semester I

Course Objectives:
 To explain the VLSI Design Methodologies using VLSI design tool.
 To grasp the significance of various CMOS analog circuits in full-custom IC Design flow
 To explain the Physical Verification in Layout Design
 To fully appreciate the design and analyze of analog and mixed signal simulation
 To grasp the Significance of Pre-Layout Simulation and Post-Layout Simulation
Course Outcomes (CO):
 Explain the VLSI Design Methodologies using VLSI design tool.
 Grasp the significance of various CMOS analog circuits in full-custom IC Design flow
 Explain the Physical Verification in Layout Design
 Fully appreciate the design and analyze of analog and mixed signal simulation
 Grasp the Significance of Pre-Layout Simulation and Post-Layout Simulation
List of Experiments:
 The students are required to design and implement using CMOS Technology.
 The students are required to implement LAYOUTS of any SIX Experiments using CMOS
130nm Technology and Compare the results with Pre-Layout Simulation.

1. MOS Device Characterization and parametric analysis

2. Common Source Amplifier
3. Common Source Amplifier with source degeneration
4. Cascode amplifier
5. Simple current mirror
6. Cascode current mirror.
7. Wilson current mirror.
8. Differential Amplifier
9. Two stage Operational Amplifier
10. Sample and Hold Circuit
11. Direct-conversion ADC
12. R-2R Ladder Type DAC

Lab Requirements:
Software:
Mentor Graphics Tool/ Cadence/ Synopsys/Industry Equivalent Standard Software
Hardware:
Personal Computer with necessary peripherals, configuration and operating System.

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 R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

Course Code CMOS DIGITAL IC DESIGN LAB L T P C

0 0 4 2
Semester I

Course Objectives:
 To explain the VLSI Design Methodologies using any VLSI design tool.
 To grasp the significance of various design logic Circuits in full-custom IC Design.
 To explain the Physical Verification in Layout Extraction.
 To fully appreciate the design and analyze of CMOS Digital Circuits.
 To grasp the Significance of Pre-Layout Simulation and Post-Layout Simulation.
Course Outcomes (CO):
 Explain the VLSI Design Methodologies using any VLSI design tool.
 Grasp the significance of various design logic Circuits in full-custom IC Design.
 Explain the Physical Verification in Layout Extraction.
 Fully appreciate the design and analyze of CMOS Digital Circuits.
Grasp the Significance of Pre-Layout Simulation and Post-Layout Simulation.
List of Experiments:

The students are required to design and implement the Circuit and Layout of any Twelve
Experiments using CMOS Technology.

1. Inverter Characteristics.
2. NAND and NOR Gate
3. XOR and XNOR Gate
4. 2:1 Multiplexer
5. Full Adder
6. RS-Latch
7. Clock Divider
8. JK-Flip Flop
9. Synchronous Counter
10. Asynchronous Counter
11.Static RAM Cell
12. Dynamic Logic Circuits
13. Linear Feedback Shift Register

Lab Requirements:
Software:
Mentor Graphics Tool/ Cadence/ Synopsys/Industry Equivalent Standard Software
Hardware:
Personal Computer with necessary peripherals, configuration and operating System.

16
 R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

Course Code RTL SYNTHESIS, SIMULATION AND L T P C

VERIFICATION 0 1 2 2

Semester I

Course objectives: This course aims to

 The simulation of combinational and sequential circuits.
 FSM based designs.
 Implementation of DFT and FFTs.
 Verify layout of basic digital circuits.

Course outcomes: After completion of this course, students will be able to

 Demonstrate the process steps required for simulation /synthesis.
 Design and simulate various combinational and sequential circuits using HDL.
 Develop an RTL code for various real time applications.
 Synthesize / Simulate an RTL code for several digital designs
 Build and verify various digital circuits.
Module 1 – Introduction to RTL Design
 RTL design flow: Specification → RTL coding → Synthesis → Simulation → Verification.
 HDL coding styles for synthesis (SystemVerilog/VHDL basics).
 Lab:
1. Write synthesizable Verilog/SystemVerilog code for:
a) Half Adder, Full Adder
b) 4-bit Ripple Carry Adder
c) 4-bit Synchronous Counter (Up/Down)
2. FSM Design: Sequence Detector (e.g., detect “1011”).

Module 2 – RTL Synthesis

 Synthesis concepts: mapping RTL to gate-level netlist.
 Constraints: clock, area, power.
 Lab:
1. Synthesize combinational and sequential circuits (Adder, Counter, FSM) using
EDA tool
2. Generate gate-level netlist and analyze area, delay, power reports.
3. Apply constraints (clock, timing) and observe impact on synthesis results.

Module 3 – Simulation
 Functional vs. Timing simulation.
 Testbench creation, waveforms, debugging.
 Lab: Run simulations
1. Develop testbenches for:
a) 4-bit ALU (add, sub, AND, OR).
b) Universal Shift Register.
2. Perform functional simulation using EDA tools
3. Perform post-synthesis (timing) simulation and compare results with
functional simulation.
Module 4 – Verification
 Verification basics: functional verification, assertion-based verification.
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 R25 Regulations

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

(Established by Govt. of A.P., ACT No.30 of 2008)
ANANTHAPURAMU – 515 002 (A.P) INDIA

M.Tech. in VLSI/VLSI SYSTEM DESIGN

COMMON COURSE STRUCTURE & SYLLABI

 Introduction to UVM/OVM concepts.
 Lab: Writing simple verification testbenches.
1. Write self-checking testbenches for combinational and sequential circuits.
2. Use assertion-based verification (SystemVerilog Assertions – SVA) for protocol checks
(e.g., handshaking signals).
3. Coverage-driven verification experiment: Create random test cases for FIFO/Memory.

Module 5 – Case Study & Mini Project

 Design, synthesize, and verify a digital subsystem (e.g., ALU, UART, FIFO).
 End-to-end RTL → Synthesis → Simulation → Verification flow.
 Lab: Design, synthesize, simulate, and verify a digital subsystem such as:

1. UART Transmitter/Receiver
2. Simple CPU Core Module (Instruction Decoder + ALU + Register File)
3. FIFO Buffer with full/empty flags

Textbooks / References
1. Samir Palnitkar – Verilog HDL: A Guide to Digital Design and Synthesis.
2. Michael Ciletti – Advanced Digital Design with the Verilog HDL.
3. Chris Spear & Greg Tumbush – SystemVerilog for Verification.
4. David Rich – Design and Verification with SystemVerilog.

Suggested reading:
1. Samir Palnitkar, “Verilog HDL, a guide to digital design and synthesis”, Prentice Hall 2003.
1. Doug Amos, Austin Lesea, Rene Richter, “FPGA based prototyping methodology manual”,
Xilinx, 2011.
2. Bob Zeidman, “Designing with FPGAs & CPLDs”, CMP Books, 2002.

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