unit 5

Santhu ff
October 2025

1 Introduction
TMS320 Family of DSPs (Architecture of TMS320C5x)
Introduction
• The TMS320 family of Digital Signal Processors (DSPs) is developed by
Texas Instruments (TI).
• These processors are optimized for real-time signal processing applications
such as audio, video, telecommunications, and control systems.
• The TMS320 family includes several generations:
– TMS320C1x – First generation (fixed-point)
– TMS320C2x/C5x – Second generation (enhanced fixed-point)
– TMS320C3x/C4x – Floating-point processors
– TMS320C6x – Very high-performance VLIW DSPs

Architecture of TMS320C5x Processor

• The TMS320C5x is a 16-bit fixed-point DSP belonging to the second
generation of TI DSPs.
• It uses a modified Harvard architecture with separate program and data
memory spaces.

Block Diagram of TMS320C5x Architecture

Main Functional Units

1. Central Arithmetic Logic Unit (ALU):
• Performs arithmetic and logical operations.
• Works with 16-bit data and supports fast multiply–accumulate (MAC)
operations.

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 2. Multiplier and Accumulator (MAC) Unit:
• Performs one multiply–accumulate operation in a single cycle.
• Essential for DSP algorithms such as convolution, correlation, and
filtering.

3. Shifter Unit:
• Performs logical and arithmetic shifts.
• Useful for scaling and normalization in DSP computations.
4. Accumulator Registers (A, B):

• Two 32-bit accumulators used to store intermediate results.

5. Auxiliary Registers (AR0–AR7):
• Used for indirect addressing and pointer manipulation.

6. Program and Data Memory:

• Separate 64K word program and data spaces.
• Supports fast data fetching and instruction execution.
7. Address Generation Unit (AGU):

• Generates effective addresses for memory operations.

• Supports circular and bit-reversed addressing.
8. On-chip Peripherals:
• Includes serial port, timer, and interrupt controller.

Key Features
• 16-bit fixed-point architecture.
• Modified Harvard architecture.

• Single-cycle multiply–accumulate (MAC) operation.

• Circular and bit-reversed addressing modes.
• On-chip RAM and ROM.

• Support for serial I/O and interrupts.

• Pipelined instruction execution.

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Applications
• Digital filters and FFT algorithms.
• Speech and audio signal processing.

• Image compression and enhancement.

• Modem and telecommunication systems.

article booktabs [a4paper,margin=1in]geometry

Comparison between Fixed Point and Floating

Point DSP Processor Data Paths

Feature Fixed Point DSP Processor Floating Point DSP Proces-

sor
Data Representation Numbers are represented as inte- Numbers are represented with a
gers with a fixed binary point. mantissa and exponent (scientific
notation).
Dynamic Range Limited dynamic range due to Wide dynamic range because of
fixed binary point. exponent field.
Precision Higher precision for small num- Precision is maintained over a
bers but limited overall range. wide range of values.
Hardware Complexity Simpler hardware, lower power More complex hardware with
consumption and cost. floating-point unit (FPU).
Speed Faster arithmetic operations due Slightly slower due to normaliza-
to simpler data path. tion and exponent handling.
Memory Requirement Requires less memory per data Requires more memory (e.g., 32-
sample (e.g., 16-bit or 32-bit bit or 64-bit floating).
fixed).
Programming Effort Requires scaling and careful Easier to program as scaling is
handling to prevent over- handled automatically.
flow/underflow.
Cost and Power Low cost and low power suitable High cost and power con-
for embedded systems. sumption suitable for high-
performance systems.
Applications Audio processing, motor control, Scientific computation, radar,
speech coding, etc. image processing, etc.

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Features of DSP Processors
Digital Signal Processors (DSPs) are specialized microprocessors designed specif-
ically for high-speed numeric processing applications such as audio, speech, im-
age, and video processing. They possess unique architectural features that en-
able efficient implementation of signal processing algorithms.

Key Features of DSP Processors

1. Harvard Architecture: DSPs use Harvard architecture where program
and data memories are separate. This allows simultaneous access to in-
structions and data, increasing processing speed.
2. Multiple Bus Architecture: DSPs typically include multiple buses for
parallel data transfers, enabling simultaneous fetching of operands and
instructions.
3. Hardware Multiplier and Accumulator (MAC Unit): DSPs have
a dedicated Multiply and Accumulate (MAC) unit that performs multi-
plication and accumulation in a single cycle. This is crucial for operations
like convolution and filtering.
4. Pipelining: DSPs use pipelining to overlap different instruction phases,
which improves instruction throughput and processing speed.
5. Special Addressing Modes: DSPs provide specialized addressing modes
such as circular addressing, bit-reversed addressing, and auto-increment/decrement
for efficient data handling.
6. Zero-Overhead Looping: DSPs support zero-overhead loops where
loop control does not consume extra clock cycles, enhancing execution
efficiency for repetitive operations.
7. On-Chip Memory: DSPs include high-speed on-chip RAM and program
memory for fast data access and reduced latency.
8. DMA (Direct Memory Access): Many DSPs support DMA to transfer
data between memory and peripherals without CPU intervention, freeing
the processor for computation.
9. Parallelism: DSPs can execute multiple operations in parallel through
techniques such as instruction-level parallelism and parallel data paths.
10. Specialized Instruction Set: DSPs have instructions optimized for sig-
nal processing, including multiply-accumulate, saturation arithmetic, and
bit manipulation operations.
11. Low Power Consumption: Modern DSPs are designed for embedded
and portable applications with power-saving modes and efficient circuit
design.

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 12. Real-Time Processing Capability: DSPs can process input signals in
real time with deterministic execution timing, making them suitable for
time-critical applications.

Conclusion
The combination of high-speed arithmetic units, efficient memory organization,
and specialized control features make DSP processors ideal for real-time signal
processing tasks.

Pipelining in DSP Processors

Introduction
Pipelining is a technique used in Digital Signal Processors (DSPs) to improve
the instruction throughput. It allows the overlapping of different stages of in-
struction execution, so that multiple instructions are processed simultaneously
in different phases.

Concept of Pipelining
In a non-pipelined processor, each instruction must complete all stages (fetch,
decode, execute, etc.) before the next instruction begins. In contrast, a pipelined
DSP divides the instruction execution into several stages, where each stage per-
forms a part of the operation.
Thus, while one instruction is being executed, another can be decoded, and
a third can be fetched. This parallelism increases the overall processing speed
and efficiency.

Typical Pipeline Stages in a DSP

A simple DSP pipeline can be divided into the following stages:

1. Instruction Fetch (IF): The instruction is fetched from program mem-

ory.
2. Instruction Decode (ID): The fetched instruction is decoded to deter-
mine the operation and operands.

3. Operand Fetch (OF): The required operands (data) are fetched from
data memory or registers.
4. Execution (EX): The operation (e.g., addition, multiplication) is per-
formed in the Arithmetic Logic Unit (ALU) or MAC unit.

5. Write Back (WB): The result of the operation is written back to the
register or memory.

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Advantages of Pipelining
• Increases instruction throughput.
• Improves processor speed without increasing clock frequency.

• Efficient utilization of processor hardware resources.

• Reduces the average execution time per instruction.

Pipeline Example
If the pipeline has 5 stages, then after the initial fill-up time, one instruction is
completed in every clock cycle.

ExecutionT ime(pipelined) = N umberof instructions + (N umberof stages − 1)

Pipeline Diagram

Clock Cycle Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5

1 IF
2 ID IF
3 OF ID IF
4 EX OF ID IF
5 WB EX OF ID IF
6 WB EX OF ID

Conclusion
Pipelining significantly enhances the computational efficiency of DSP processors.
It allows continuous data flow and real-time signal processing by overlapping in-
struction execution stages. [a4paper,12pt]article article booktabs [a4paper,margin=1in]geometry

Comparison between Butterworth and

Chebyshev Filters

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S.No Butterworth Filter Chebyshev Filter
1 Has a maximally flat magnitude re- Has ripples in the passband (Type I) or
sponse in the passband (no ripples). stopband (Type II).
2 Provides smooth and monotonic fre- Provides faster roll-off due to ripple
quency response. characteristics.
3 Slower transition from passband to Sharper transition between passband
stopband. and stopband.
4 No ripple in either passband or stop- Ripple present either in passband or
band. stopband depending on filter type.
5 Magnitude response decreases slowly Magnitude response decreases rapidly
compared to Chebyshev. compared to Butterworth.
6 Filter order required for given specifica- Lower filter order is required for the
tions is higher. same specifications.
7 Phase response is more linear than Phase response is less linear due to rip-
Chebyshev. ples.
8 Easier to design and implement. Slightly complex design due to ripple
parameter.
9 Suitable for applications requiring Suitable for applications requiring
smooth frequency response. sharp cutoff characteristics.
10 Transfer function poles lie on a circle in Transfer function poles lie on an ellipse
the left-half s-plane. in the left-half s-plane.

Table 1: Comparison between Butterworth and Chebyshev Filters