GATE Computer Science & IT

ADVANCED
DIGITAL LOGIC

Practice Questions Booklet

ANALYSIS OF DIGITAL LOGIC IN GATE PAPER

 Years Marks
2015 5
2016 6
2017 3
2018 4
2019 4
2020 4
2021(Set-1) 6
2021(Set-2) 7
2022
DIGITAL LOGIC GATE SYLLABUS
 Boolean Algebra and Minimization: Logic Operations, Laws of Boolean Algebra,
Sum of Product and Product of Sum, Karnaugh Map etc.
 Logic Gates: OR, AND, NOT, NOR, NAND, Ex-OR, Ex-NOR, Universal Gate etc.
 Arithmetic Circuits: Half-Adder, Full-Adder, Half-Subtractor, Full-Subtractor, Serial
Adder, Parallel Adder etc.
 Combinational Circuits: Multiplexer, Demultiplexer, Decoder, Encoder, Priority
Encoder etc.
 Sequential Circuits: SR Flip-Flops, JK Flip-Flops, D Flip-Flops, T Flip-Flops, Level
Triggered, Edge Triggered, Counters, Asynchronous Ripple or Serial Counter,
Synchronous UP/DOWN Counter.

DIGITAL LOGIC GATE REFERENCE BOOKS

 Digital Circuits and Design by S Salivahanan
 Fundamentals of Digital Circuits by A. An

Short Notes
 Simplification and K-map
Q1. Which of the following is the K-Map produces exactly the same outputs as the
most simplified version of the following K-Map?

(a) (b)

(c) (d)

Answer: (d)
Solution:
Given K - Map

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 Given k – map produces output as Y = AB + A C
The same output is produced by option (d).
Option (d) is correct.

Q2. Given the following Boolean function:

F(A,B,C,D)=Σm(0,2,8,11) + d(3,10,15)
What is the complement function F'?
(a) ΠM(1, 4, 5, 6,7 , 9, 12, 13, 14)
(b) ΠM(1, 4, 5, 6, 7, 9, 12, 13, 14) .d(3, 10,1 5)
(c) ΠM(0, 2, 8, 11) .d(3, 10, 15)
(d) none of the above.

Answer: (c)
Solution:

F = m (0, 2, 8, 11) + d (3, 10, 15)

F = m (1, 4, 5, 6, 7, 9, 12, 13, 14) + d (3, 10, 15)
F = m (0, 2, 8, 11). D(3, 10, 15)

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  Correct is ©.
Q3. Consider the K-map for a Boolean function F(A, B, C, D) as shown below,
where X represents don’t care value.

Let X is the number of prime implicants and Y be the number of essential

prime implicants in the K-map, then the value of X + Y is______

Answer: (6)
Solution:

No. of prime implicants (X) = 6

No. of essential prime implicants (Y) = 0
 All four ones are part of more than one prime implicants.
 Correct is 6.
Q4. Consider the following K-map of a function W(A, B, C, D):

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 What is the simplest SOP form for W' (the complement of W)?
(a)A.B'.C + A'.B.D' + A.C'.D' + B'.C.D
(b)A.B.C' + A.B'.D' + A'.C.D' + B.C'.D
(c)A.B'.C + A'.B.D' + A.C'.D + B'.C.D'
(d)A.B.C + A'.B.D' + A.C'.D' + B.C.D'
Answer: (a)
Solution:

WSOP = SOP of Zeroes in above K – Map

= BCD + ABC + ABD + A CD
By re – arranging the terms
= A BC + AB𝐷 + ACD + BCD
 Correct option is (a)
Q5. Consider the following K-map:

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 You need to change two cells in the K-map above to don’t cares such that:
1) The new minimal S.O.P. and P.O.S. are equal functions
2) The sum of the number of literals from the S.O.P. and P.O.S. is minimal.
Which of the following minterm’s you will select as a don’t care?
(a) Σd(3, 10)
(b) Σd(2, 7)
(c) Σd(2, 9)
(d) Σd(8, 13)

Answer: (d)
Solution:
Check Option (a)  (3, 10)
F=

F = ABD + A BD + BCD
SOP form

F=

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 F= BD + AC + B D
F = BD + AC + BD
F = (BD) (AC) (𝐵𝐷 ) [By Demorgan’s law]
F = (B + D) (A + C) (B + D) [POS form]
F = (BA + B C + DA + DC) (B + D)
F = ABD + BCD + ABD + B C D
Clearly SOP form and POS form of option (a) does not match, hence new minimal SOP
and POS are not equal functions.
 Option (a) is not correct.
Similarly you can check for option (b) and option (c). [ Both b and c are incorrect ]
Now check option (d)  (8, 13)
F=

SOP form F = BD + BD

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 F = BD + B D
F = BD + BD
F = (BD) (BD)
F = (B + D) (B + D) [POS form]
F = BB + BD + BD + DD

F = BD + BD

Here in option (d) the new minimal SOP and POS are equal to the functions.
 Option (d) is Correct.

Q6. Consider the symbolic K-map shown below, where F and G are Boolean
variables, and F' and G' represent their respective Boolean complements.

Clearly, the above K-map gives rise to different Boolean functions of x1, x2, x3
and x4 for different combinations of Boolean values of F and G. In other
words, the K-map represents a Boolean function of x1, x2, x3, x4, F and G.
Let us call this function H(x1, x2, x3, x4, F, G). Suppose F and G are
functions of {x1, . . . x4}. Specifically, suppose F = (x1 + x4) and G =
(x1⊕x2⊕x4). How many sum terms of the minimal POS form of the Boolean
function ϕ represented by the symbolic K-map given above? _______________

Answer: 4

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 Solution:
F = x1 + x4
G = x1  x2 x4

∅ = H = x1 x2 x4 + x1x2x4 + x2 x3x4 + x1 x2x3 x4

H= x1 x2 x4 + x1 x2 x4 + x2 x3 x4 + x1 x2 x3 x4
H = (x1 x2 x4 ) (x1 x2 x4 ) (x2 x3 x4 ) (x1 x2 x3 x4 )
H = (x1 + x2 + x4) (x1 + x2 + x4) (x2 + x3 + x4 ) (x1 + x2 + x3 + x4)
POS from (minimal)
No. of sum terms = 4

Q7. Consider the following K-maps where blank cells are don’t care:

What is F⊕G?
(a) Σ(2,6,8,11,13,14) + d(3,5,7,9,12,15)
(b) Σ(2,6,8,13) + d(3,5,7,9,11,14,12,15)
(c) Σ(2,6,8) + d(3,5,7,9,12,15)
(d) Σ(0,1,4) + d(3,5,7,9,11,14,12,15)
Answer: (a)
Solution:

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 F = m (0, 2, 6, 8, 10, 13) + d (3, 5, 11, 12, 14)

G = m (0, 10, 11, 14 ) + d (5, 7, 9, 15)

F  G = Min term that is present exactly once
= m (2, 6, 8, 13, 11, 14) +D (3, 5, 7, 9, 15, 12)
= m (2, 6, 8, 11, 13, 14) + d (3, 5, 7, 9, 12, 15)
 Option (a) is correct.
Q8. Consider the following Boolean function in Maxterm form:
𝑓(𝐴,𝐵,𝐶,𝐷) = Π(0,1,3,4,9,11).d(6,7,10,12,13)
How many minimized SOP for (𝐴,B,C,D) are there? _______

Answer: 1
Solution:
f (A, B, C, D) =  (0, 9, 3, 4, 9,11) D (6, 7, 10, 12, 13)

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 F = CD + BD + A D
 Only 1 minimized SOP
 Correct answer is 1.
Q9. Which of the following choice below that best describes the functionF (A, B, C,
D, E) = m(0, 2, 7, 8, 10, 12, 14, 15, 16, 18, 19, 23, 24, 26, 27, 31)?
(a) ABE + ACE+ACDE+ADE (b) ADE+C'E'+CDE+A'BE'
(c) ACDE+ABE+ADE+CD (d) ABCE+CDE+CD+ADE

Answer: (b)
Solution:
K – Map for 5 – variables

F = A (CE + BE + CDE) + A (DE + CE)

F = ACE + A B E + ACDE + ADE + ACB
F = CE A + A + A B E + DE (A + A C)
F = CE + A B E + ADE + CDE

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  Option (b) is correct.

Q10. The function J(a, b, c) has three inputs a, b, c and one output. Output is true
when two or more inputs are true; otherwise, output is false. That is,
J(1,1,0)=J(1,0,1)=J(0,1,1)=J(1,1,1)=1. otherwise, J=0.
Which of the following is/are true?
(a) Minimal SOP for J(a,b,c) = ab + bc + ac
(b) xJ(a,b,c) + x’y + yJ(a,b,c) = xJ(a,b,c) + x’y
(c) J(a,b,c) is functionally complete
(d) None of the above

Answer: (a) and (b)

Solution:
(a) J(a, b, c) = abc' + ab'c + a 'bc + abc = ab + be + ac
(b) Proof:
xJ(a, b, c) + x'y + yJ(a,b,c)
= xJ(a, b, c) + x'y + (x + x’) yJ (a, b, c)
= x(1 + y)J(a, b, c) + x'y(1+ J(a, b, c))
= xJ(a, b, c) + x 'y
(c) No. Because no complement appears in the minimum sum-of-products
expression of the majority logic J (a, b, c) "NOT" cannot be realized. Thus,
the majority logic J (a, b, c) is not functionally complete.
Q11. [MSQ]
Given the following Boolean expression of F(A,B,C):
F(A, B, C) = A' + B + C'
Which of the following statements is/are true about the above expression?
(a) It is an SOP expression
(b) It is a POS expression
(c) It is a sum-of-minterm’s expression
(d) It is a product-of-maxterm’s expression

Answer: (a), (b), (d)

Solution:

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Q12. Given the Boolean expression below:
AB’ (C + D' + E)'F + (C' + F')' + DF
Which of the following is equivalent to the above expression?
(a) F
(b) DF
(c) (C'+ D')F
(d) (C + D)F
Answer: (d)
Solution:
AB C + D + E F + (C + F) + DE
AB (C D E) F + CF + DF
(ABC D E + C + D)F
((A BCE + 1) D + C) F
(D + C) F
 Option (d) is correct.

Q13. Consider the following Boolean expression:

w(z + y) + zx'w + zx'w' + yz;
Assume that w + x' + y = 1andyw = 0. Which of the following is the most
simplified form of above expression?
(a) wz + wy + x'z + yz
(b)wz + x'z +yz
(c) z
(d) wz + wy + zx'w + zx'w' + yz
Answer: (c)
Solution:

Q14. Given a Boolean function f(A, B, C) = m(1,3,6)+ d(), how many don't care
terms need to be l's to make f(A,B,C)= AC?_________
Answer: 1
Solution:

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 A  C = AC + AC
So by taking m4 = 1 in k – map of ‘f’ we get f (A, B, C) = A  C
 Only 1 don’t care term need to be 1.
 Answer is 1.
Q15. Given that AB  0 and A  B  1 , the Boolean function 𝐴 + 𝐶 𝐴 + 𝐵 is equivalent
to
(a) AC (b) BC (c) AB (d) none of these

Answer: (b)
Solution:
( A  C )( A  B )  A A  AB  AC  BC  AB  AC  BC
 0  AC  BC  C ( A  B ) 1  C ( A  B )( A  B )
 C ( AA  AB  AB  BB)  C ( AB  AB  B )  C (( A  A) B  B )
 C ( B  B )  BC

Q16. [MSQ]
Select the Boolean function(s) equivalent to x + yz, where x, y, and z are
Boolean variables, and + denotes logical OR operation.
(a) x + z + xy
(b) (x + y) (x + z)
(c) x + xy + yz
(d) x + xz + xy

Answer: (b) and (c)

Solution:
f = x + yz
(a) x + z + xy
x + xy + z
x (1 + y) + z
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 x+z
Not equivalent to x + yz.
 Option (a) is incorrect.
(b) (x + y) (x +z)
x + xz + xy + yz
x (1 + z + y) + yz
x + yz
Equivalent to f,  Option (b) is correct.
© x + xy + yz
x (1 + y) + yz
x + yz
Equivalent to f,  Option © is Correct.
(d) x + xz + xy
x ( 1 + z + y)
Not equivalent to f,  Option (d) is incorrect.

So, Option (b, c) are Correct.

Q17. A staircase light is controlled by two switches; one is at the top of the stairs
and other at the bottom of stairs. Realization of this function using NAND
logic results in which of the following circuits? (Assume S1 and S2; are the
switches)

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 Answer: (a, d)
Solution:
Stair case light will be on, when atleast one of the switch will be on. i.e.
f = S1 + S2
(a)

S1 S1 S2 = S1 + S1S2 = S1 + S2
S1 S2 S2 = S1S2 + S2 = S1 + S2

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 S1 + S2 (S1 + S2 ) = S1 + S2 + S1 + S2
= S1. S2 + S1 . S2
= S 1 S2
 Option (a) is correct.

(b)

F = S1.S2 . S1 .S2 = 0
 Option (b) is incorrect.
(C)

F = S1 S2 = S1 + S2
 Option © is incorrect.
(d)

F = S1 + S2 (S1 + S2 )
= S1 + S2 + S1 + S2
F = S1.S2 + S1 .S2 = S1 S2
 Option (d) is correct.
Q18. Consider the following Circuit

the function f represented

(a) (x0 + x1) (x2 + x3) (x4 + x5)....(xn-1+ xn)
(b) x0 + x1 +x2 +x3 + . . . + xn
(c) x0x2x4. . .xn + x1x2. . .xn + xn-1xn
(d) x0x1 + x2x3 + . . . + xn-1xn

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 Answer: (c)
Solution:
Take n = 4

f1 = x0 + x1
f2 = f1.x2 = (x0 + x1) x2 = x0x2 + x1x2
f3 = f2 + x3 = x0x2 + x1x2 + x3) x4
f4 = x0x2x4 + x1x2x4 + x3x4
f4 matches with option © by putting n = 4 in option ©
 Option © is correct.
Q19. If the functions w, x, y and z are as follows.
w = R + PQ + RS
x = PQRS + PQRS + P QRS
y = RS + PR + PQ + PQ
z = R + S + PQ + PQR + P QS
then
(a) w = z, x= y
(b) w = z, x = z
(c) w = y
(d) w = y = z

Answer: (b)
Solution:
w = R + PQ + RS

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 x = PQRS + PQRS + PQRS

y = RS + R + PQ + PQ
y = RS + (PR) (P Q) (PQ)
y = RS + (P + R) (P + Q) (P + Q)
y = RS + (P + R) (PQ + QP + Q)
y = RS + (P + R) Q
y = RS + PQ + RQ

Z = R + S + PQ + PQR + P QS
Z = R + S + (PQ ) (PQR) (P QS )
Z = R + S + (P + Q) (P + Q + R) (P + Q + S)
Z = R + S + (P + Q) (PQ + PS + PQ + Q + QS + PR + QR + RS)
Z = R + S + (P + Q) (Q + PS + PR + RS)
Z = R + S + (P + Q) (Q + PS + PR) {By Consensus theorem}
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 Z = R + S + PQ + PR + P QS + PQ R
Z = R + S + PQ
Z = R + S + PQ

You can observe from K –Map of w, x, y, z that w = z and x = z

 Option (b) is true.

Q20. The dual form of expression

AB + AC + BC = AB + AC is
(a) (A + B) (A + C) (B + C) = (A + B) (A + C)
(b) (A + B) (A + C) (B + C) = (A + B) (A + C)
(c) (A + B) (A + C) (B + C) = (A + B) (A + C)
(d) AB + AC + BC = AB + AC

Answer: (a)
Solution:
AB + AC + BC = AB + AC
It’s dual form is :
(A + B) (A + C) (B + C) = (A + B) (A + C)
{No change in variable and priority of variable remains constant}
Option (a) is Correct.
Q21. Boolean expression for shaded portion is

(a) ABC + ABC

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 (b) AB + BC + CA
(c) ABC + ABC + ABC
(d) ABC + ABC + ABC

Answer: (c)
Solution:

Boolean expression for shaded portion is ABC + ABC + ABC

 Option© is correct.
Q22. A function of Boolean variables X, Y and Z is expressed in terms of the min-
terms as
F(X, Y, Z) = (1, 2, 5, 6, 7)
Which one of the product of sums given below is equal to the function F(X, Y,
Z)?
(a) (X + Y + Z). (X + Y+ Z). (X + Y + Z)
(b) (X + Y + Z). (X + Y + Z). (X + Y + Z)
(c) (X + Y + Z). (X + Y + Z). (X + Y + Z). (X + Y +Z). (X + Y + Z)
(d) (X + Y +Z). (X + Y + Z) (X + Y +Z). (X + Y +Z). (X + Y + Z)
Answer: (b)
Solution:

F =  (0, 3, 4)

000 011 100

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 F = (X + Y + Z) (X + Y + Z) (X + Y + Z)
 Option (b) is correct.
Q23. Following is the k — map of a Boolean function of five variables P, Q, R, S and
X. The minimum sum of product (SOP) expression for the function is:

(a) PQ S X + P Q S X + Q RS X + QR S X
(b) Q S X + Q S X
(c) Q S X + Q SX
(d) Q S + Q S

Answer: (b)
Solution:

F = X (SQ) + X (SQ)
 F = QSX + QSX
 Option (b) is correct.
Q24. In a car security system, we usually want to connect the siren in such a way
that the then will activate when it is triggered by one or more sensors. In
addition, there will be a master switch to turn the system on or off.

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  Let us assume that there is a car door switch D, a vibration detector switch
V, and a master switch M.
 Assume that when the door is opened, D = 1, otherwise D = 0.
 Similarly, when the, car is being shaken, V = 1, otherwise, V = 0.
 We want the siren S to turn on (i.e., set S = 1) when either the door is open
or the car is shaken.
 The siren should turn on only when the system is turned on. However,
when we turn off the system, we do not want the siren to turn on
regardless of the state of the door switch or the vibration switch.
Given the above description of a car security system, which of the following is
the Boolean Function F(M, D, V) as a sum of minterm’s for car security
system?
(a) Σm(2, 5, 6)
(b) Σm(4, 5, 7)
(c) ΣM(5, 6, 7)
(d) ΣM(4, 5, 6)

Answer: (c)
Solution:

Q25. A vending machine that dispenses drinks has four buttons: C (coffee), T (tea),
M (milk), S (sugar). Create the logic for the signal that will dispense a stirring
stick, based on the following rules:
1. This machine is meant to dispense beverages only: coffee, tea, milk, coffee

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 with milk and tea with milk.
2. If no buttons are pressed, don't dispense a stick.
3. If any drink is selected on its own, don't dispense a stick.
4. If coffee or teas are dispensed with either milk or sugar, then dispense a
stirring stick.
5. The user will never select sugar on its own.
6. The user will never select milk and sugar together on their own, and will
never select coffee and tea together (yuck).
What is the Boolean expression of the output stick for this vending machine
in terms of inputs C, T, M and S?
(a) S + TM + CM
(b) TS + SC + TM
(c) C'TS + C'TM + CT'S + CT'M
(d) CSM + TSM + C'T'

Answer: (a)
Solution:
Number C T M S STICK
0 0 0 0 0 0
1 0 0 0 1 X
2 0 0 1 0 0
3 0 0 1 1 X
4 0 1 0 0 0
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 1
8 0 0 0 0 0
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 X
13 1 1 0 1 X
14 1 1 1 0 X
15 1 1 1 1 X

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 Stick = S + TM + CM
 Option (a) is correct.
Q26. Which of the following function are complete?
(a) f(x,y) = x' + y
(b) f(x,y,z) = xy' + yz
(c) f(x,y) = xy' (x'+y) x'y y'
(d) None of the above

Answer: (d)
Solution:
(a)
f (x, y) = x + y
x y x x+y
0 0 1 1
0 1 1 1
1 0 0 0
1 1 0 1
Check for 5 properties
1. 0 preserve  false
2. 1 preserve  true
As 1 preserve property is satisfied.
 Option (a) is not functionally complete.
(b) f (x, y, z) = xy + yz
x y z y xy yz xy + yz
0 0 0 1 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 1 1
1 0 0 1 1 0 1
1 0 1 1 1 0 1
1 1 0 0 0 0 0
1 1 1 0 0 1 1

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 1. 0 preserve  true
As 0 preserve property is satisfied.
 Option (b) is not functionally complete.
© f (x, y) = xy (x + y) xy y
x y x y xy x+y xy f (x, y)
0 0 1 1 0 1 0 0
0 1 1 0 0 1 1 0
1 0 0 1 1 0 0 0
1 1 0 0 0 1 0 1

1. 0 – preserve
As 0 preserve property is satisfied.
 Option © is not functionally complete.
As Option (a, b, c) all are not functionally complete.
Option (d) is correct.
Q27. If X = 1 in the logic equation [X + Z{Y + (Z + XY)}] {X + Z (X + Y)} = 1, then
(a) Y = Z
(b) Y = Z’
(c) Z = 0
(d) Z = 1

Answer: (c)
Solution:
[X + Z {Y + (Z + XY)}] {X + Z (X + Y)]
[1 + Z {Y + (Z + XY)}] {X + Z (X + Y)}
X + Z (X + Y) = 1
1 + Z (1 + Y) = 1
0+Z=1
Z=0
 Option © is correct.
Q28. Minimize the following Boolean function
F = ABC’D’ + ABC’D + AB’C’D + ABCD + AB’CD +ABCD’ + AB’CD’
(a) AB + AC + AD
(b) BC + BD + AD +AC
(c) CD + AB + AC
(d) AB + BC

Answer: (a)
Q29. How many minimum number of NAND gate are required to implement

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 Boolean funcation F = (x' + y')(w' + x)(xz')? Assume that all variables are
available in both true and complement form.________________
Answer: 3
Solution:

F = AB + AD +AC
 Option (a) is correct.

Data for the next three questions, the logic circuit below has three inputs, X, Y
and Z, and two outputs, F and G.

Q30. Which of the following is the minterm list form of a Boolean function F(X, Y,
Z)?
(a) XYZ (3, 5, 6, 7) (b) XYZ (1, 2, 4, 7)
(c) XYZ (0, 3, 5, 6) (d) XYZ (0, 1, 2, 4)

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 Answer: (a) and (d)
Solution

F = (XY)(XZ) (YZ)
F = XY + XZ + YZ
F = XY + XZ + YZ

F = XYZ (3, 5, 6, 7)
and F = xyz (0, 1, 2, 4)
 Option (a, d) are correct.
Q31. Which of the following is the minterm list form of a Boolean function G(X, Y,
Z)?
(a) XYZ (3, 5, 6, 7) (b) XYZ (1, 2, 4, 7)
(c) XYZ (0, 3, 5, 6) (d) XYZ (0, 1, 2, 4)

Answer: (b) and (c)

Solution:

G = (X ⊙Y) ⊙Z
G = (XY + XY) ⊙ Z
G = (XY + XY)Z + (XY + XY) (Z)
G = XYZ + XY Z + X Y + X Y (Z)
G = XYZ + XY Z + X Y Z + X YZ

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 G = XYZ (1, 2, 4, 7) = XYZ (0, 3, 5, 6)
 Option (b, c) are correct.
Q32. An operator # is defined by A#B = A' + B. This operation is
(a) Commutative
(b) Associative
(c) Both Commutative and Associative
(d) Neither Commutative nor Associative

Answer: (d)
Solution:

Q33. How many minterm’s does function f(A, B, C, D) = A⨁B⨁C⨁D include?

___________

Answer: 8
Solution:

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Q34. What is the minimum number of logic gates required if we convert the circuit
in Figure to a circuit with NAND gates ONLY? _____________Assume that
complements literals are not available.

Answer: 7
Solution:

 7 NAND Gates are required.

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 Combination Circuit
Q35. An 8-to-1 multiplexer is used to implement a logical function Y as shown in
the figure. The output Y = F(A, B, C, D) is given by:
(a) m(2, 6, 10, 11)
(b) m(3, 7, 12. 13)
(c) m(0, 2, 4, 5, 6, 8, 9, 10, 11, 14, 15)
(d) m(0, 1, 3, 7, 9, 10, 12, 13, 14, 15)

Solution:
Y = ABC D + AB C D + AB C (0) + A B C (0) + ABC (0) + A BC (0) + ABC (0) +
ABC (1) + ABC (0)
Y = AB C D + A BC D + ABC (D + D)
Y = AB CD + A BCD + AB C D + AB CD
0011 0111 1101 1100
3 7 13 12
Y = m (3, 7, 12, 13)
 Option (b) is Correct.

Q36. Consider the following multiplexer where I0, I1, I2 and I3 are four data input
lines selected by two address line combinations A1A0 = 00, 01, 10, and 11,
respectively, and F is the output of the multiplexer. EN is the enable input,
find the function F(x, y, z) implemented by the below circuit.
(a) m(6)
(b) m(3, 7)
(c) m(0, 2, 4, 5, 6)
(d) None of the above

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 Solution:

F = EN (A1 A0 I0+ A1 A0 I1 + A1A0 I2 + A1A0I3)

F = z (yz x + yzx + yz y + y z y)
F = z (xy (z + z) + 0 + yz)
F = z (xy + yz)
F = xyz + yzz
F = xyz
F = M (6)
Option (a) is Correct.
Q37. The following multiple switching functions are to be implemented using a
single decoder and OR gates:
f1 =m (2, 4, 10, 11, 12, 13, 14)
f2 = m (1, 3, 8, 10, 11)
f3 = m (2, 4, 5, 6, 7)
Which of the following is the minimum configuration of decoder and OR gates
are needed?
(a) 3-to-8-line decoder and 3 OR gates
(b) 3-to-8-line decoder and 4 OR gates
(c) 4-to-16-line decoder and 3 OR gates
(d) 4-to-16-line decoder and 4 OR gates

Solution:
f1 = m (2, 4, 10, 11, 12, 13, 14)
f2 = m (1, 3, 8, 10, 11)
f3 = m (2, 4, 5, 6, 7)

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 4 to 16 line decoder and 3 OR gates are required.
Q38. A 3-to-8 decoder is shown in the following figure

All the output lines of the chip will be high except pin 8, when all the inputs
1, 2, and 3
(A) are high; and G, G2 are low
(B) are high; and G is low G2 is high
(C) are high: and G, G2 are high
(D) are high: and G is high; G2 is low

Answer: (c)
Solution:

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 Outputs are active low, so to make Pin 8 low, all the inputs will be high and
chip will be enabled, that means
G2 = 1 and G = 1
 G2 = 0 (low)
and G = 1 (high)
 All the output lines of the chip will be high except Pin8, when all the inputs
1, 2 and 3 are high and G is high and G2 is low.
Q39. The circuit shown in figure is same as

(a) two input NAND gate with a and c inputs

(b) two input NOR gate with a and c inputs
(c) two input XOR gates with a and b inputs
(d) two input XNOR gate with b and c as inputs.

Answer: (d)
Solution:

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 y = bc a + b c (a) + bc a + bc (a)
y = abc + a b c + a b c + a bc

y = ab + a b = a  b
 Circuit is same as two input XOR gates with a and b inputs.
 Option © is correct.
Q40. If a 4-to-1 MUX (shown in the figure) realizes a three-variable function
𝑓 (𝑥, 𝑦, 𝑧) = 𝑥𝑦 + 𝑥𝑧, then which of the following is correct?

(a) I0 = x, I1 = 0, I2 = x, I3 = x
(b) I0 = 0, I1 = 1, I2 = y, I3 = x
(c) I0 = x, I1 = 1, I2 = 0, I3 = x
(d) I0 = x, I1 = 0, I2 = x, I3 = z

Answer: (a)

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 Solution:

Check option (a)

F = yz x + y z 0 + y z x + yz (x)
F = xyz + xy z + xyz

F = xy + xz
 Option (a) is correct.
Q41. For an MUX to function as a full adder, what should be the input provided to
the I0, I1, and I2, I3 if the A and B are the select lines?

(a) I0 = I1 = Cin; I2 = I3 = Cin

(b) I0 = I1 = Cin ; I2 = I3 = Cin
(c) I0 = I3 = Cin; I1 = I2 = Cin
(d) I0 = I3 = Cin ; I1 = I2 = Cin

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 Answer: (c)
Solution:
We know that in Full Adder
Sum (S) = A  B  C = AB C + A B C + A BC + ABC
Carry (Cout) = AB + BC + CA
K – Map of sum (S) of full adder is:

Our Approach:-
Check all options one by one and if any options K – Map matches with K –
Map of sum than only that option will be correct.
(a)

F = AB C + A BC + A BC + AB C

K – Map of option (a) doesn’t match with K – Map of sum.

 Option (a) is incorrect.
(b)

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 F = ABC + A B C + A B C + ABC

K – Map of option (b) doesn’t match with sum.

 Option (b) is incorrect.
(c)

F = AB C + A B C + A BC + ABC

K – Map of Option © matches with K – map of sum.

 Option © is correct.
Q42. The following multiplexer circuit is equal to

(a) Implementation of sum equation of full adder

(b) Implementation of carry equation of full adder

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 (c) Implementation of borrow equation of full subtract
(d) None of the above

Answer: (a)
Solution:

y = bc a + b c a + bca + bca
y = abc + ab c + a bc + abc

 K map of sum equation of full adder and y are same.

 Option (a) is Correct.
Note:- Remember the K – Map of sum equation of full adder, it will be very
helpful to quickly solve this type of problems.
Q43. If we have a comparator and if E represents the condition for equality, that is,
(An Bn), if An and Bn are to be compared, then the expression
A3B3 + E3A2B2 + E3E2A1B1 +E3E2E1A.Brepresents which of the condition for a 4-
bit number?
(a) A > B
(b) B > A
(c) A = B
(d) none of these

Answer: (d)
Solution:
En = An Bn

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 Do this question by option elimination,
(a) Find those values of A and B which makes option (a) false.
E. g.
A = 15 and B = 14
A  A3 A2 A1 A0
1 1 1 1
B  B3 B2 B1 B0
1 1 1 0
Expression = A3B3 + E3A2B2 + E3E2A1B1 + E3E2E1A0B0
= 1.0 + (11).1.0 + 0 + 0 = 0 (NOT 1)
 Option (a) is Incorrect.
(b) A = 0 and B = 15
A  A3 A2 A1 A0
0 0 0 0
B  B3 B2 B1 B0
1 1 1 1
Expression = A3B3 + E3A2B2 + E3E2A1B1 + E3E2E1A0B0
= 1.0 + (0  1).0.0 + 1. (1  0).0.0 + 1.1.1.0.0
=0+0+0+0
= 0 (not 1)
 Option (b) is incorrect.
(c) A = 15 and B = 15
A  A3 A2 A1 A0
1 1 1 1
B  B3 B2 B1 B0
1 1 1 1
Expression:- A3B3 + E3A2B2 + E3E2A1B1 + E3E2E1A0B0
= 1.0 + 0 + 0 +0
= 0 (not 1)
 Option © is incorrect.
Hence Option (d) none of these is correct option.
Q44. Consider a Boolean gate (D) where the output Y is related to the inputs A and
B as, Y = A +B, where + denotes logical OR operation. The Boolean inputs '0'
and '1' are also available separately. Using instances of only D gates and
inputs '0' and '1', _________ (select the correct option(s)).
(a) NAND logic can be implemented
(b) OR logic cannot be implemented
(c) NOR logic can be implemented
(d) AND logic cannot be implemented

Answer: (a, c)
Solution:

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 F (A, B) = A+ B
As 0 and 1 are available.
F(0, B)= A+B = 0 + B
= B (NOT)
F(A+B) = A+ B = A + B
F (A +B) = A + B (OR)
With the combination of OR and NOT, NOR gate can be implemented.
Since NOR gate is universal logic gate, so all the functions can be
implemented. So, correct option is (a, c).
Q45. Which circuit diagram exactly matches the Boolean algebra expression𝑌 =
𝐶(𝐴 + 𝐵)(𝐵𝐶 )?
(a) (b)

(c) (d)

Answer: (b)
Solution:
Y = C (A + B) (B C)
(a)

Y = AB (B + C) C
Not matches with Option (a)
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 (b)

Y = (A + B) B C . C
OR
Y = C (A + B) C (matches)
 Option (b) is Correct.
Q46. We have the combinational circuit shown below with part of its logic hidden. It
takes in one 1-bit input: A, and produces one 1-bit output: Out. The
relationship between A and Out is shown in the accompanying truth table.

What is the functionality of the hidden logic in the circuit? You can denote the
two inputs to the hidden logic as In1 and In2.
(a) AND (b) NOR (c) NAND (d) OR

Answer: (a) and (b)

Solution:
(a)

Out = A.A = 0
 Option (a) is correct.
(b)

Out = A + A = 1 = 0

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  Option (b) is correct.
(c)

Out = A. A = 0 = 1
 Option © is incorrect.
(d)

Out = A + A = 1
 Option (d) is incorrect.
Q47. Consider the following decoder with the logic gates:

Which of the following function G(A, B, C) implemented by the above circuit?

(a) Σm(1, 2, 5, 6)
(b) Σm(0, 3, 4, 7)
(c) ΠM(0, 1, 2, 3)
(d) ΠM(4, 5, 6, 7)

Answer: (a)
Solution:

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 G = X1.X2
X1 = (ABC)⊙ (A BC)
X1 = (ABC. A BC) + A + B + C (A + B + C) [ A ⊙ B = AB + AB]
X1 = 0 + A + (B + C) (B + C)
X1 = A + BC + BC
X2 = (ABC)⊙ (ABC)
X2 = (ABC) (ABC) + (A + B + C) (A + B + C)
X2 = 0 + A + B + C (B + C)
X2 = A + BC + BC
G = X1.X2
G = (A + BC + BC) (A + BC + BC)
G = A.A + BC + BC
G = BC + BC

G = m (1, 2, 5, 6) = m (0, 3, 4, 7)
 Option (a) is correct.
Q48. Which of the following is the correct truth table for the circuit shown below?

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 (a) (b) (c) (d)

Answer: (b)
Solution:

f = x (g) + x (g)
f = x (yz + y z) + x (yz + yz)
f = xy z + x y z + xyz + xyz

Truth table of f is :-
x y z f
0 0 0 0 0
1 0 0 1 1
2 0 1 0 1
3 0 1 1 0
4 1 0 0 1
5 1 0 1 0
6 1 1 0 0
7 1 1 1 1

 Option (b) is correct.

Q49. Which circuit below implements the function f(x, y, z) = xy + xz + yz?

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 (a)

(b)

(c)

(d) None of the above

Answer: (a), (b) and (c)

Solution:
(a)

f = z (xy) + z (x + y)
f = xyz + xz + yz
f = x (y z + z) yz
f = x (y + z) + yz
f = xy + yz +xz
 Option (a) is correct.
(b)

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 f = x(yz) + x ( y + z)
f = x yz + xy + xz
f = (xz + x) y + xz
f = (z + x) y + xz
f = xy + yz + xz
 Option (b) is correct.
©

f = y (xz) + y (x + z)
f = xyz + xy + yz
f = x (yz + y) + yz
f = xy + xz + yz
 Option © is correct.
Data for the next three questions, the circuit below uses a 2-bit magnitude
comparator, a 4:1 multiplexer and a 1:4 demultiplexer. Inputs are A, B, C, D and
outputs are P, Q, R, S.

Q50. Which of the following is the simplified SOP expressions for P?

(a) Σm(10, 15)

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 (b) Σm(4, 12, 13, 14)
(c) Σm(2, 3, 6, 7, 11)
(d) Σm(4, 5, 6, 7)

Answer: (a)
Solution:

A B C D MUX output P
0 0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1 0
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0 1
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1 1

If we think logically (to solve this question quickly)

than P will be high only when both S1 and S0 are low and output of MUX is
high, Imean,

for P to be 1,
S1 = 0 and S0 = 0 and MUX output = 1
Now for S1 = 0 and S0 = 0 that means X is neither less than Y and X is neither
greater than Y it means X = Y.
For X = Y
X1X0 = Y1Y0
A B =CD
4 possible case ABCD = 0000 0101 1010 1111
Conclusion: In truth table whenever AB = CD
Than P = A
{Because S1 and S0 of both MUX and DEMUX are set zero}
 P is high at ABCD = 1010 and 1111
 SOP expression for is m (10, 15)
Q51. Which of the following is the simplified SOP expressions for Q?
(a) Σm(10, 15)

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 (b) Σm(4, 12, 13, 14)
(c) Σm(2, 3, 6, 7, 11)
(d) Σm(4, 5, 6, 7)

Answer: (c)
Solution:
For Simplified SOP expression for Q, S1 = 0 and S0 = 1 in DEMUX and S1 is
connected with X> Y Pin of comparator and so is connected with X < Y Pin of
Comparator that means,
S1 = of MUX = value of X < Y = So of DEMUX = 1
S0 = of MUX = value of X > Y = S1 of DEMUX = 0

 Q of DEMUX = C of MUX only when X < Y

A B C D Q
0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

X < Y or AB < CD in 6 possible cases {0001, 0010, 0011, 0110, 0111,

1011} but C is only at min term 2, 3, 6, 7, 11
 SOP expression for Q = m (2, 3, 6, 7, 11)
 Option © is correct.
Q52. Which of the following is the simplified SOP expressions for R?
(a) Σm(10, 15)

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 (b) Σm(4, 12, 13, 14)
(c) Σm(2, 3, 6, 7, 11)
(d) Σm(4, 5, 6, 7)
Answer: (b)
Solution:

 R of DEMUX = B of MUX only when X >Y

A B C D R
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0 1
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1
 From truth table, R is high at min term 4, 12, 13, 14
 R = m (4, 12, 13, 14)
 Option (b) is correct.
Data for the next four questions, multiplication the unsigned product of 2-bit
numbers A1A0 and B1B0 is a 4-bit result Y3Y2Y1Y0 for example,

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112.112 = 310.310 = 910 = 10012
Identify the efficient Boolean formulas for the product bits Y 3, Y2, Y1 and Y0 as a
function of the bits of the multiplier A1A0 and the multiplicand B1B0?
Q53. Boolean formulas for Y3
(a) A0B0
(b) A1'A0B1 + A1A0'B0 + A1B1'B0 + A0B1B0'
(c) A1A0'B1 + A1B1B0'
(d) A1A0B1B0

Answer: (d)
Solution:

Q54. Boolean formulas for Y2

(a) A0B0
(b) A1'A0B1 + A1A0'B0 + A1B1'B0 + A0B1B0'
(c) A1A0'B1 + A1B1B0'
(d) A1A0B1B0

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 Answer: (c)
Solution:

Q55. Boolean formulas for Y1

(a) A0B0
(b) A1'A0B1 + A1A0'B0 + A1B1'B0 + A0B1B0'
(c) A1A0'B1 + A1B1B0'
(d) A1A0B1B0

Answer: (b)
Solution:

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Q56. Boolean formulas for Y0
(a) A0B0
(b) A1'A0B1 + A1A0'B0 + A1B1'B0 + A0B1B0'
(c) A1A0'B1 + A1B1B0'
(d) A1A0B1B0

Answer: (a)
Solution:

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Data for the next two questions, with the addition of few logic gates, an n-bit ripple
carry adder can be used to compare the magnitude of two n-bit unsigned numbers.
Consider the n-bit ripple carry adder with logic gates:

You may assume both A and B are unsigned numbers.

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Q57. For vectors A = a3a2a1a0 and B = b3b2b1b0, the output X of the circuit is
(a) A = B
(b) A > B
(c) A < B
(d) A >= B

Answer: (a)
Solution
Let sum output of FA1, FA2, FAA IS x1, x2, xn respectively.
 X = x1 + x2 + ⋯ + xn
For X to be high (x = 1)
x1 + x2 + … . + xn = 1
x1 + x2 + . . . xn = 0
It means x1 = 0 and x2 = 0 . . . and xn = 0
Now observe the FA1

Sum = A  B  C
Carry = AB + BC + CA

Sum = 1 A0B0 = x1 = 0
A0B0  1 = 0 {As XOR is associative}
A0B0 = 0 {As 1  A = A}
A 0  B0 = 0
A 0  B0 = 0
It means A0B0 = 00 or 11
 A0 = B0
Similarly in generalized way we can say that
A0 = B0
A1 = B1
.
.
.
An = Bn
A=B
Hence Option (a) is correct.
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Q58. For vectors A = a3a2a1a0 and B = b3b2b1b0, the output Yof the circuit is
(a) A = B
(b) A > B
(c) A < B
(d) A >= B

Answer: (d)
Q59. Given F (a, b, c, d) = Σm (0, 1, 3, 4, 8, 9, 10, 11, 12, 14), which of the following
is/areVALID expression for F?
(a)F (a, b, c, d) = (b' + d') (a + c' + d)
(b) F (a, b, c, d) = c'd' + ad' + b'd
(c) F (a, b, c, d) = Π(2, 5, 6, 7, 13, 15)
(d) F (a, b, c, d) = (bd + a'cd')'

Answer: (a), (b), (c) and (d)

Solution:

F = cd + b d + a d
 Option (b) is correct.
F = bd + a cd
F = F = bd + a c d
 Option (d) is correct.
F = bd + a cd
F = (bd) (acd)
F = (b + d) (a + c + d)
 Option (a) is correct.
From K – Map,
F = m (0, 1, 3, 4, 8, 9, 10, 11, 12, 14)
F = m (2, 5, 6, 7, 13, 15)
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  Option © is correct.
Hence Option (a, b, c, d) all are correct.
Q60. The output F of the digital circuit shown can be written in the form(s)

(a) A. B (b) A+ B
(c) A + B (d) A . B

Answer: (a) and (b)

Solution:

Q61. The Boolean function realized by the logic circuit shown is

(a) F= m(0,1,3,5,9,10,14)
(b) F= m(2,3,5,7,8,12,13)

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 (c) F= m(1,2,4,5,11,14,15)
(d) F= m(2,3,5,7,8,9,12)

Answer: (d)
Solution

F = AB C + A BD + A BC + AB CD
F = AB C + A BD + A BC + AB CD

F = m (2, 3, 5, 7, 8, 9, 12)
Q62. The propagation delays of the XOR gate, AND gate and multiplexer (MUX) in
the circuit shown in the figure are 4 ns, 2 ns and 1 ns, respectively.

If all the inputs P, Q, R, S and T are applied simultaneously and held

constant, the maximum propagation delay of the circuit is

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 (a) 8 ns (b) 5 ns
(c) 6 ns (d) 7 ns

Answer: (a)
Q63. For the given combinational network with three inputs A, B, and C, three
intermediate outputs P, Q, and R, and two final outputs X = PQ =  (0, 2, 4)
and Y = PR = (1, 2, 4, 6) as shown in the figure.

Find the smallest function P (containing minimum number of minterms that

can produce the output x and y).
(a) (2, 4)
(b) (0, 1, 2, 4, 6)
(c) (3, 5, 7)
(d) (1, 2, 6)

Answer: (b)

P  Q = {0, 2, 4}
It implies P must contain 0, 2, 4
 P = (0, 2, 4} [minimum set of P] - - - - - -(1)
P  R = {1, 2, 4, 6}

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 It implies P must contain 1, 2, 4, 6
 P = {1, 2, 4, 6} [minimum set of P]
From equation (1) and equation (2)
Small function P = (0, 2, 4}  {1, 2, 4, 6}
 P {0, 1, 2, 4, 6}
Q64. Consider a two-level logic implementation of the look-ahead carry generator.
Assume that all Pi and Gi are available for the carry generator circuit and that
the AND gates and OR gates can have any number of inputs. The number of
AND gates and OR gates needed to implement the look-ahead carry generator
for a 3-bit adder are:
(a) 4 and 10
(b) 6 and 3
(c) 10 and 4
(d) 6and5

Answer: (b)
Solution:

Q65. A 1-bit Full Adder circuit takes 70 ns to produce the sum and 50 ns to
produce the carry. If a 6-bit parallel adder is to be designed with the Full
Adder block, what will be the minimum propagation delay for getting the
results? How many 6-bit additions per second can be expected from this
design?
(a) 230ns, 3.275  106
(b) 320ns, 3.125  106

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 (c) 35Ons, 3.125  106
(d) 370ns, 3.275  106

Answer: (b)

Q66. Consider the incomplete circuit implementing the function y(a, b, c)= Σm
(1,2,4,7):

Which of following is the missing Label1 & Label2 respectively so that the
circuit shown above correctly implements y(a, b, c)?
(a) 1, a' (b) a, a' (c) a', a (d) 1, 1

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 Answer: (b)
Solution:

Suppose l1 and l2 are inputs to label- 1 and label - 2 respectively

y1 = bl1 + b l1
y2 = b l2 + b l2
y = cy1 + cy2
y = c (bl1 + b l1 ) + c (bl2 + bl2 )
y = bcl1 + b cl1 + bc l2 + bcl2 - - - - - (1)
y = m(1, 2, 4, 7) = ab c + a b c + a bc + abc- - - - (2)
001 010 100 111
on Comparing equation (1) and (2)
l1 = a and l2 = a
 Option (b) is correct.
Q67. What does this circuit represent?

(a) The sum of a full adder

(b) The carry-out of a full adder
(c) The C output of a carry-look-ahead adder (C = AB + C(A⊕B))
(d) None of the above

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 Answer: (d)

Y = AB 0 + A B C + AB C + AB (C)
Y = ABC + AB C + ABC
(a) Sum = A BC
= 001, 010, 100, 111
= AB C + A BC + ABC + ABC
 Option (a) is incorrect.
(b) Cout = AB + BC + CA
 Option (b) is incorrect.
© C = AB + C (A  B)
= AB + C (AB + AB)
= AB + ABC + AB C
 Option © is incorrect.
 Option (d) is correct.
Q68. For the Boolean function f (a, b, c) = ΣM (1, 6, 7) the missing inputs X and Y
respectively to the multiplexers. Assume EN= 1.

(a) 1, a' (b) a, a' (c) a', a (d) 1, 1

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 Answer: (c)
f (a, b, c) = m (1, 6, 7) = ab c + abc + abc

Y1 = ac + ax
f = bY1 + BY
f = b (a c + ax) + b y = ab c + abc + abc
f = ab c + ab x + bY = ab c + abc + abc
Compare,
= a`b c + abX + bY = ab c + abc + abc
= ab c + ab X + bY = ab c + ab ( c + c = 1)
Now check option by option:
(a) 1, a
abc + ab + ba = ab c + ab

K – Map does not match,

 Option (a) is incorrect.
(b) a, a
= ab c + a b a + ba = ab c + ab
= ab c + ab + a b = ab c + ab

K – Map does not match

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  Option (b) is incorrect.
© a, a
= ab c + aba + ba
= ab c + 0 + ba = ab c + ab
= ab c + ab = ab c + ab
LHS = RHS
 Option © is correct.
Data for the next two questions, consider the circuit shown below:

The circuit shown above takes as input an 8-bit number A [7:0] and a control input
Z. It generates an 8-bit output G [7:0].
Q69. What is functionality of the circuit when Z = 0?
(a) Logical right shift by 2 bits
(b) Logical left shift by 2 bits.
(c) Arithmetic right shift by 2 bits.
(d) Arithmetic left shift by 2 bits.

Answer: (c)
Solution:
When z = 0
Input no.  A7 A6 A5 A4 A3 A2 A1 A0
Output no.  A7A7A7 A6 A5 A4 A3 A2
You can observe 2 conclusion from output:
Conclusion 1: Right shift by 2 bit ( A1 and A0 is lost)
Conclusion 2: Arithmetic shift [ output retains the topmost bit]
Option © is correct.
Note: The difference b/w logical shift and Arithmetic shift is understood by an
example shown below:
Consider the Binary number in 2’s complement is 11100101

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 After applying logical right shift by 2 bits  00 111001
After applying Arithmetic right shift by 2 bits  11 111001
Q70. What is functionality of the circuit when Z = 1?
(a) Unsigned division by 3
(b) Unsigned division by 8
(c) Unsigned multiplication by 3
(d) Unsigned multiplication by 8

Answer: (b)
Solution:
Input no.  A7 A6 A5 A4 A3 A2 A1 A0
Output no.  0 0 0 A7 A6 A5 A4 A3
Logical Right shift by 3 bits
 Unsigned division by 23
 Option (b) is correct.
Q71. Function implemented by the following circuit is

(a) Half adder

(b) Full adder
(c) Half substractor
(d) Full substractor

Answer: (b)

Solution

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 f1 = (A0 + B0 + A0 B0 C0 )
= (A0 + B0 ) (A0 B0 C0 )
= (A0 + B0) (A0B0 + C0)
= A0B0 + A0C0 + A0B0 + B0C0
f1 = A0B0 + B0C0 + C0A0 = Carry of full adder
f2 = (A0 B0 ) (A0 + B0)  C0
= (A0 + B0 ) (A0 + B0)  C0
= (A0 B0 + A0B0 )  C0
f2 = A0B0C0 Sum of full adder.

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 Sequential Circuit
Q72. Consider the following flip-flop constructed using a D flip-flop:

Tthe next-state equation for the above flip flop is

(a) Q(t + 1) = Q(t) ⊚ X
(b) Q(t + 1) = Q(t)'⊕ X
(c) Q(t + 1) = Q(t) ⊕ X
(d) Q(t + 1) = Q(t)' ⊚ X

Answer: (c, d)
Solution

Qt+1 = D
D = X  Qt
 Qt+1 = d = XQt = XQt + XQt = Qt ⊙ X
 Options (c, d) are correct.
Q73. A new flip-flop, called AB flip-flop, is created as shown below.

What does the flip flop do?

(a) Set command A = 0B = 0
(b) Reset command A = 0B =1
(c) Hold command A = 1 B = 0

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 (d) Toggle command A = 1 B = 1

Answer: (d)
Solution:
J=A+B
K = AB
Qt+1 = JQt + TCQt
A B J K Qt+1
0 0 0 0 Qt Hold state
0 1 1 0 1 set state
1 0 1 0 1 set state
1 1 1 1 =Qt Toggle state

Toggle command A = 1 R = 1
 Option (d) is correct.

Q74. An incomplete schematic of a down-counter is shown below. This design uses

T flip-flops as the internal storage.

Which one of the following gate must be in the box to complete schematic of a
down-counter?
(a) NOR
(b) NAND
(c) XOR
(d)X-NOR

Answer: (a)

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 Solution:

Assume output of box is X (So T2 = X)

In ff0
T0 = 1
𝑄0+ = T0 Q0 = 1  Q0 = Q0
𝑄0+ = Q0
In ff1
T1 = Q 0
𝑄0+ = T1 Q1 =Q0  Q1 =Q0 . Q1 +Q0 . Q1
= Q0. Q1 +Q0 .Q1
= Q0⊙Q1
+
𝑄1 = Q0⊙ Q1
In ff2,
T2 = X
𝑄2+ = T2 Q2
= X  Q2
𝑄2+ = X  Q2
Check option (a) (NOR)

T2 = X = Q 1 + Q 0
LSB 
Q0 Q1 Q2
0 0 0
1 1 1
0 1 1
1 0 1
0 0 1
1 1 0
0 1 0
1 0 0
0 0 0
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 1 1 1

MSB 
Q2 Q1 Q0
0 0 0 0
1 1 1 7
1 1 0 6
1 0 1 5
1 0 0 4
0 1 1 3
0 1 0 2
0 0 1 1
0 0 0 0

As output are 7, 6, 5, 4, 3, 2, 1, 0
 Given counter is mod – 8 down counter
 Option (a) is Correct.
Data for the next two question, the following sequential circuit consists of two
different flip-flops and five gates. The input and output signals are X and Y,
respectively. Each state is encoded as Q1Q0, with the JK flip-flop being Q1 and the SR
flip-flop being Q0 of the state representation.

Q75. A group of employees is implementing this circuit. A careless employee ignored

the difference between the two flip-flops, and thus mistakenly replaced the SR
flip-flop with a JK flip-flop in his implementation. Which of the following
statement is TRUE regarding this change?
(a) The modified circuit will not work correctly, as the next state logic in the
circuit will generate the (1, 1) input combination.
(b) The modified circuit will not work correctly, as the next state logic in the

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 circuit will not generate the (0, 1) input combination.
(c) The modified circuit will not work correctly, when X = 0 & Q0 =1, both
inputs of the JK flip-flop will be 1.
(d) The modified circuit will work correctly, as the next state logic in the circuit
will never generate the (1, 1) input combination.

Answer: (d)
Solution: The modified circuit will still work, because the next state logic in
this circuit will never generate the (1, 1) input combination which is the invalid
input for an SR flip-flop. For all other input combinations, the JK flip-flop has
the same functionality as the SR flip-flop. Therefore, the replacement does not
change the behavior of the circuit.
Q76. Interestingly, another employee made the opposite mistake. He replaced the
JK flip-flop with an SR flip-flop in his implementation. Which of the following
statement is TRUE regarding this change?
(a) The modified circuit will not work correctly, as the next state logic in the
circuit will generate the (1, 1) input combination.
(b) The modified circuit will not work correctly, as the next state logic in the
circuit will not generate the (0, 1) input combination.
(c) The modified circuit will not work correctly, when X = 0 & Q0 =1, both
inputs of the JK flip-flop will be 1.
(d) The modified circuit will work correctly, as the next state logic in the circuit
will never generate the (1, 1) input combination.

Answer: (c)
Solution: The modified circuit will not work. When X = 0 & Q0 =1, both inputs
of the JK flip-flop will be 1. This is an invalid input combination if it is
replaced by an SR flip-flop, and will change the behavior of the circuit.
Q77. A sequential circuit has one flip-flop Q, two inputs X and Y, and one output S.
The circuit consists of a D flip-flop with S as its output and logic implementing
the function D  X  Y  S with D as the input to the D flip-flop.

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 Which one of the following is the state diagram of the above circuit? Assume
that formate XY/S on the arc repersent Input/Output.
(a)

(b)

(c)

(d)

Answer: (d)
Q+ = S + = D = X  Y  S
X Y S S+ = XYS

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 0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

now draw excitation table from above truth table:

S S+ X Y S
0 0 0 0 0 OR 110
0 1 0 1 0 OR 100
1 0 1 0 1 OR 011
1 1 1 1 1 OR 001

State Diagram below:

 Option (d) is correct.

Q78. Find the values of p. q. r and s in the state diagram for the given sequential
logic circuit:

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 Assume that on arc, values in the form X/Q and in circle value represents Y
(a) p = 0/1, q = 1/0, r = 1/1, s =0/0
(b) p = 1/0, q = 0/1, r = 1/1, s =0/0
(c) p = 0/0, q = 1/0, r = 0/1, s =1/1
(d) p = 1/1, q = 0/0, r = 0/1, s =1/0

Excitation table of J/K flip flop:-

Q Q+ J K J=K
0 0 0 X 0
0 1 1 X 1
1 0 X 1 1
1 1 X 0 0

Case 1: Q = 0 and Q+ = 0
J=K=0

1X=0
X=1

Y=1⊙1=1
p = X/Y = 1/1
Case 2:
Q = 0 and Q+ = 1
J=K=1

1X=1
X=0

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 Y=1⊙0
Y=0
q = 0/0
Case 3:
Q = 1 and Q+ = 0

0X=1
X=1

Y=0⊙1
Y=0
S = 1/0
Case 4:
Q = 1 and Q+ = 1

0X=0
X=0

Y=0⊙0
Y=1
r = 0/1
Q79. The following synchronous sequential circuit is designed with a J-K flip-flop
and a T flip-flop with JA = (A+ B'), KA = (A'+B), and TB = A. If the initial state
(AB) is 00, then find the sequence of states visited by the circuit?

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 (a) 00, 01, 10, 11
(b) 00, 10, 11, 00
(c) 00, 11, 10, 00
(d) 00, 01, 11, 10

Answer: (b)
Solution:
In J –K flip flop,
Q+ = JQ + KQ
A+ = JAA + K A A
A+ = (A + B) A + (A + B)A
A+ = AB + (A. B)A
A+ = A B + A B
A+ = (A + A)B
 A+ = B
In T – flip flop
Q+ = T  Q
B + = T B B
B+ = A  B
A B
0 0
1 0
1 1
0 0

00, 10, 11, 00

 Option (b) is correct.
Q80. Which of the following statements is/are FALSE?
(a) Characteristic Equation of a flip-flop is a minimized representation of the
next state by considering present input only.
(b) A don't care in Excitation Table indicates that the specific transition will
take place irrespective of the variable under consideration being 0 or 1.
(c) Characteristic Table shows in tabular from what as input is required to

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 move the flip-flop from one particular state to other.
(d) The State Analysis Table lists all the inputs of the flip-slop at a given state
and finds out next state using flip-flop Truth Table and also notes the final
output.

Answer: (a) and (c)

Q81. The number of used states of the counter shown in the following figure is____:

Answer: 6
Solution

𝑄0+ = J0Q0 + K 0 Q0
𝑄0+ = 1.Q0 + 0. Q0
𝑄0+= Q0

𝑄1+= J1Q1 + K1 Q1
= (Q0Q2 ) Q1 +Q0 . Q1
= Q0 Q 1 Q 2 + Q 0 Q1

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 𝑄2+= J2Q2 + K 2 Q2
𝑄2+= Q0Q1Q2 + Q0 Q2
𝑄0+= Q0 - - - - - (1)
𝑄1+= Q0Q1 . Q2 + Q0 Q1 - - - - -(2)
𝑄2+= Q0Q1Q2 + Q0 Q2 - - - - - - -(3)
State Q0 Q1 Q2
1 0 0 0
2 1 0 0
3 0 1 0
4 1 1 0
5 0 0 1
6 1 0 1

 No. of used of the counter = 6

Q82. Consider the following figure:

Suppose you are asked to make a decoding circuit such that the output Y=1
when the counter is at state 1, 2, 4 and 7. Using a single gate, which of the
following can be used to implement the given logic operation?
(a) AND
(b) OR
(c) XNOR
(d) XOR
Answer: (c)
Solution
A+ = A
B+ = B {B will change its output only when A changes its output from 1 to 0
because B is negative edge triggered flipflop with input clock A}
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 C+ = C (C will change its output only when B changes its output from 1 to 0)
MSB
A B C
0 0 0
1 0 0
0 1 0
1 1 0
0 0 1
1 0 1
0 1 1
1 1 1
0 0 0

MSB
A B C
0 0 00
0 0 1 1
0 1 02
0 1 13
1 0 04
1 0 1 5
1 1 06
1 1 17
0 0 0 6

Check option by option:-

(a) AND

When C = 1, B = 1, A = 1 (state 7) Y should be 1 but,

Y = 1.1.1 = 0
 Option (a) is false.
(b) OR

When C = 0, B = 0, A = 1, (8 state 1) Y should be 1, but

Y = 1+0+0 = 1 = 0
 Option (b) is false.
© XNOR

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 Y = C ⊙ B ⊙ A = CBA
When C = 0, B = 0, A= 0 (State 0) Y should be 1, buy Y = 0  0 0 = 0
Option © is false.
(d) XOR

Y = CBA = C⊙B⊙A
When C = 0, B = 0, A = 1, Y should be 1,
but Y = 0 ⊙ 0 ⊙ 1 = 0
 Option (d) is false.

Q83. The initial state of the counter is CBA=000 (A-LSB).

The number of clock pulse at which the counter again goes back to its initial
state. and the order of state of the counter for each clock pulse is
a) At 8th clock pulse, 000,001,110,111,100,101,010,011
b) At 7th clock pulse, 000,001,110,111,100,101,010
c) At 8th clock pulse 000, 101, 011, 110, 010, 111, 001
d) At 7th clock pulse, 000,101,011,110,010,111,001

Answer: (a)
Solution:

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 JA = 1, KA = 1
A+ = JAA + K A A
A+ = 1A + 1A = A
A+ =A

JB = A, KB = A
B+ = JBB + K B B
B+ = AB + A B
B+ = AB

JC = AB, KC = AB
C+ = JCC + K C C
C+ = ABC + ABC
C+ = ABC
MSB
A B C
0 0 0
1 0 0
0 1 1
1 1 1
0 0 1
1 0 1
0 1 0
1 1 0
0 0 0

MSB
C B A
0 0 0

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 1 0 0 1
21 1 0
31 1 1
41 0 0
51 0 1
60 1 0
70 1 1
80 0 0

After 8th clock plus, counter again goes back to its initial state 000.
Order of state is 000, 001, 110, 111, 100, 101, 010, 011
 Option (a) is correct.
Data for the next two questions, consider the F flip-flop with an external input F.
The state diagram of his flip-flop is shown below.

Q84. If the F flip-flop is implemented using a T flip-flop and one logic gate, then the
logic gate is
(a) EX-OR (b) OR
(c) NOT (d) EX-NOR

Answer: (c)
Solution:
Implementing F Flipflop using T flipflop
Truth table of F:
Excitation Table of T:
F Q Q+ T
0 0 0 1 1
1 0 1 0 1
2 1 0 0 0
3 1 1 1 0

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 F Flip flop is implemented using a T flip flop and one NOT gate.
 Option © is correct.
Q85. If the F flip-flop is implemented using a D flip-flop and one logic gate, then the
logic gate is
(a) EX-OR (b) OR
(c) NOT (d) EX-NOR

Answer: (d)
Solution: .
Implementing F flip flop using D flipflop
Truth table of Flip flop :
Excitation table f D flip flop
F Q Q+ D
0 0 0 1 1
1 0 1 0 0
2 1 0 0 0
3 1 1 1 1

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 D = FQ + FQ = F ⊙ Q

The F flip flop is implemented using a D flip flop and one XNOR gate.
 Option (d) is correct.
Q86. Consider the sequential circuit below, which uses four D flip-flops. The 𝐶𝐿𝑅
input is an asynchronous input that is used to clear the value of a flip-flop.
Note that Q' of the right-most flip-flop is connected to the D input of the left-
most flip-flop.

The circuit is initialized to ABCD = 0000 by clearing all flip-flops to zero (i.e.,
the Q output for every flip-flop is cleared to zero). This sequential circuit cycles
through a number of states. The first state (call it state 0) is 0000, the second
state (call it state 1) is 1000. How many states are there altogether? __________

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 Answer: 8
Solution:
A+ = D
B+ = A
C+ = B
D+ = C
A B C D
0 0 0 0  State 0
1 0 0 0  State 1
1 1 0 0  State 2
1 1 1 1  State 3
1 1 1 1  State 4
0 1 1 1  State 5
0 0 1 1  State 6
0 0 0 0  State 7
0 0 0 0

 Total state = 8 (state 0 to state 7)

Q87. Which of the following is the correct truth table for the gated SR latch circuit
shown?

(a) (b)

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 (c) (d)

Q88. A committee of logic designers could not agree on whether to use NAND gates
or NOR gates to build a set-reset latch. The compromise design is shown
below.

Which of the following is(are) the correct statement(s) regarding the

compromise design?
(a) This circuit is a set latch; it can never be reset.
(b) When X is 0, the output of the NAND gate is low, which forces the output of
the NOR gate high.
(c) When Y is 1, the output of the NOR gate is low, which forces the output of
the NAND gate high.
(d) When X is 1 and Y is 0, the circuit retains its previous state.

Q89. The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing
flip-flops, with each flip-flop having a propagation delay of 20 ns, is ______.
(Round off to one decimal place).

Q90. The digital circuit shown

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 (a) is a divide-by-5 counter
(b) is a divide-by-7 counter
(c) is a divide-by-8 counter
(d) does not function as a counter due to disjoint cycles of states

Q91. Assuming that flip-flops are in reset condition initially, the count sequence
observed at QA in the circuit shown is

(a) 0010111…
(b) 0001011…
(c) 0101111…
(d) 0110100…

Q92. If we need to design a synchronous counter that goes through the states
00  01  11  10  00 using D flip-flop, what should be the input to the
flip-flops?

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 (a) D0 = Q0, D1 = Q1
(b) D0 = Q1 , D1 = Q0
(c) D0 = Q1 Q0, D1 = Q1 Q0
(d) D0 = Q0 , D1 = Q1

Answer: (b)
Solution
Q1 Q0 D1 D0
0 0 0 0 1
1 0 1 1 1
3 1 1 1 0
2 1 0 0 0
0 0

D1 = Q0

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 D0 = Q1
 Option (b) is correct.

Q93. The excitation table for a flip-flop whose output conditions are,
if AB = 00, no change of state occurs,
AB = 01, ff becomes 1 with next clock pulse,
AB = 10, ff becomes 0 with next clock pulse,
AB = 11, ff changes its state
(a) Qn Qn+1 A B (b) Qn Qn+1 A B
0 0 0 x 0 0 1 x
0 1 1 x 0 1 0 x
1 0 x 1 1 0 x 0
1 1 x 0 1 1 x 1

(c) Qn Qn+1 A B (d) Qn Qn+1 A B

0 0 x 0 0 0 x 0
0 1 x 1 0 1 1 x
1 0 1 x 1 0 x 1
1 1 0 x 1 1 0 x

Answer: (c)
Solution
Truth table:
A B Qn Qn+1
0 0 0 0
0 0 1 1
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 0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0

Excitation table:
Qn Qn+1 A B
0 0 0 0
1  X0
0
0 1 0 1
1  X1
1
1 0 1 0
1  1 X
1
0 1 0 0
0  0X
1

 Option © is correct.

Q94. Consider the following sequential circuit:

Assume that the flip-flops are all positive edge triggered, and their values are
all high before the first positive clock edge. Which of the following is the correct
Wave form for the output Y?

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 Answer: (c)
Solution
𝑄0+ = D0 = Q0 Q1 = Y
𝑄1+ = D1 = Q0
𝑄2+ = D2 = Q1
Y = Q0  Q1
Q0 Q1 Q2
1 1 1
0 1 1
1 0 1
1 1 0
0 1 1
1 0 1

 Option © is correct.

Q95. Consider the following circuit:

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 If S0=0, S1=1when the clk is received, then A0(t+1) and A1(t+1)will be
(a) A0(t+1) = L, A1(t+1) = A0
(b) A0(t+1) = A1, A1(t+1) = R
(c) A0(t+1)= I0, A1(t+1) = I1
(d) A0(t+1) = A0, Al(t+1) = A1
Answer: (a)
Solution

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 A1 (t + 1) = D1 =A0
A0 (t + 1) = D0 = L
 Option (a) is correct.
Q96. The circuit shown consists of J-K flip-flops, each with an active low
asynchronous reset ( 𝑅𝑑 input). The counter corresponding to this circuit is

(a) a modulo – 8 up counter

(b) a modulo – 5 up counter
(c) a modulo – 6 up counter
(d) a modulo – 7 up counter

Answer: (d)
Solution
𝑄0+= Q0
𝑄1+ = Q1 when Q0 1 to 0 { -ve edge triggered flip flop }
𝑄2 = Q2 when Q1 1 to 0
+

Rd = Q2. Q1. Q0
 Rd = Q2. Q1.Q0
It means output of Flip flop get reset (000) when Q2 = Q1 = Q0 = 1
Q0 Q1 Q2
0 0 0
1 0 0
0 1 0
1 1 0
0 0 1
1 0 1

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 0 1 1
1 1 1

Q0. Q1.Q2 = 111 will disappear because Rd is asynchronous

 Only possible states are 7
MSB Q2 Q1 Q0
0 0 00
0 0 11
0 1 02
0 1 13
1 0 04
1 0 15
1 1 06
0 0 0

 Given circuit is mod – 7 up counter.

 Option (d) is correct.
Q97. A mod-n counter using a synchronous binary up-counter with asynchronous
clear input is shown in the figure. The value of n is _______.

Answer: 10
Solution
Clear = QC QA
Clear = QC. QA
QA QB QC QD
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0

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 1 0 0 1
1 0 1 0
Clear get high and clear input is
asynchronous therefore 1010 does not
appear.
Hence Total 10 states are possible (0000 to 1001)
 Mod – 10 counter.
So n = 10 ans.
Q98. Five JK flip - flops are cascaded to form circuit shown in figure. Clock pulses
at a frequency of 1 MHz are applied as shown. The frequency (in kHz) of the
waveform at Q4 is ______. (Rounded off to two decimal places)

Answer: 31.25
Solution

𝑓 1000𝑘ℎ𝑧
 Frequency of waveform at Q4 = = = 31.25 kHz answer.
32 32

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