ECE 410: VLSI Design Course Lecture Notes
(Uyemura textbook) Professor Andrew Mason Michigan State University
ECE 410, Prof. A. Mason
Lecture Notes Page 2.1
CMOS Circuit Basics
CMOS = complementary MOS
uses 2 types of MOSFETs to create logic functions
nMOS pMOS
source drain drain gate gate source
nMOS
pMOS
CMOS Power Supply
typically single power supply VDD, with Ground reference
typically uses single power supply VDD varies from 5V to 1V
VDD VDD
+ CMOS logic circuit
CMOS logic circuit
Logic Levels
all voltages between 0V and VDD Logic 1 = VDD Logic 0 = ground = 0V
V
VDD logic 1 voltages undefined logic 0 voltages
Lecture Notes Page 2.2
ECE 410, Prof. A. Mason
Transistor Switching Characteristics
nMOS switching behavior
on = closed, when Vin > Vtn
drain Vout
nMOS
Vin
gate
Vtn = nMOS threshold voltage Vin is referenced to ground, Vin = Vgs
off = open, when Vin < Vtn
+ Vgs -
nMOS Vgs > Vtn = on
source
pMOS switching behavior
+ Vsg on = closed, when Vin < VDD - |Vtp| Vin |Vtp| = pMOS threshold voltage magnitude gate
Vin is referenced to ground, Vin = VDD-Vsg
source
pMOS
pMOS Vsg > |Vtp| = on Vsg = VDD - Vin
off = open, when Vin > VDD - |Vtp| Rule to Remember: source is at lowest potential for nMOS highest potential for pMOS
ECE 410, Prof. A. Mason
drain
Lecture Notes Page 2.3
Transistor Digital Behavior
nMOS
Vin Vout (drain) 1 Vs=0 device is ON 0 ? device is OFF
Vin
drain gate
Vout
nMOS
pMOS
Vin Vout (drain) 1 ? device is OFF 0 Vs=VDD=1 device is ON
+ Vgs -
nMOS Vgs > Vtn = on
source
+ Vsg Vin
pMOS
source
gate drain
pMOS Vsg > |Vtp| = on Vsg = VDD - Vin
Vin
VDD VDD-|Vtp| on
pMOS off on
Vout
Vtn
off nMOS
Notice: When Vin = low, nMOS is off, pMOS is on When Vin = high, nMOS is on, pMOS is off Only one transistor is on for each digital voltage
ECE 410, Prof. A. Mason
Lecture Notes Page 2.4
MOSFET Pass Characteristics
Pass characteristics: passing of voltage from drain (or source) to source (or drain) when device is ON (via gate voltage) Each type of transistor is better than the other at passing (to output) one digital voltage
nMOS passes a good low (0) but not a good high (1) pMOS passes a good high (1) but not a good low (0)
nMOS
ON when gate is high
VDD 0V
VDD
?
Vy = 0 V
0V
VDD
+ Vgs=Vtn ?Vy = VDD-Vtn
Passes a good low
Max high is VDD-Vtn
0V
pMOS
ON when gate is low
VDD
?
Vy = VDD
0V
Vsg=|Vtp| ?+
Vy = |Vtp|
Passes a good high
Min low is |Vtp|
Rule to Remember source is at lowest potential for nMOS and at highest potential for pMOS
ECE 410, Prof. A. Mason Lecture Notes Page 2.5
MOSFET Terminal Voltages
How do you find one terminal voltage if the other 2 are known?
nMOS case 1) if Vg > Vi + Vtn, then Vo = Vi
Vo Vg Vi
(Vg-Vi > Vtn) (Vg-Vi < Vtn)
here Vi is the source so the nMOS will pass Vi to Vo
case 2) if Vg < Vi + Vtn, then Vo = Vg-Vtn For nMOS, max(Vo) = Vg-Vtn
here Vo is the source so the nMOS output is limited
Vi Vg
pMOS case 1) if Vg < Vi - |Vtp|, then Vo = Vi
(Vi-Vg > |Vtp|)
here Vi is the source so the pMOS will pass Vi to Vo
case 2) if Vg > Vi - |Vtp|, then Vo = Vg+|Vtp| (Vi-Vg < |Vtp|)
Vo
here Vo is the source so the pMOS output is limited
For pMOS, min(Vo) = Vg+|Vtp|
IMPORTANT: Rules only apply if the devices is ON (e.g., Vg > Vtn for nMOS)
ECE 410, Prof. A. Mason Lecture Notes Page 2.6
MOSFET Terminal Voltages: Examples
nMOS rules max(Vo) = Vg-Vtn
case 1) if Vg > Vi + Vtn, then Vo = Vi case 2) if Vg < Vi + Vtn, then Vo = Vg-Vtn (Vg-Vi > Vtn) (Vg-Vi < Vtn) 1.5 Vo
Vg 2 Vi 2 source Vi 2
acts as the source
nMOS examples (Vtn=0.5V)
1: Vg=5V, Vi=2V
Vg=5 > Vi +Vtn = 2.5 Vo = 2V
Vo 2 Vg 5
2: Vg=2V, Vi=2V
Vg=2 < Vi+Vtn = 2.5 Vo = 1.5V
pMOS rules
min(Vo) = Vg+|Vtp|
case 1) if Vg < Vi - |Vtp|, then Vo = Vi (Vi-Vg > |Vtp|) case 2) if Vg > Vi - |Vtp|, then Vo = Vg+|Vtp| (Vi-Vg < |Vtp|)
pMOS examples (Vtp=-0.5V)
1: Vg=2V, Vi=5V
Vg=2 < Vi-|Vtp|=4.5 Vo = 5V
Vi 5 source Vg 2 Vo 5 Vg 2
Vi 2
acts as the source
2: Vg=2V, Vi=2V
Vg=2 > Vi-|Vtp|=1.5 Vo = 2.5V
2.5 Vo
ECE 410, Prof. A. Mason
Lecture Notes Page 2.7
Switch-Level Boolean Logic
Logic gate are created by using sets of controlled switches Characteristics of an assert-high switch nMOS acts like an assert-high switch
y = x A, i.e. y = x if A = 1
AND, or multiply function
Series switches AND function
Parallel switches OR function
a AND b
ECE 410, Prof. A. Mason
a OR b
Lecture Notes Page 2.8
Switch-Level Boolean Logic
Characteristics of an assert-low switch pMOS acts like an assert-low switch
y=x
y=?
y = x A, i.e. y = x if A = 0
error in figure 2.5
Series assert-low switches ?
a b
NOT (a OR b)
NOT function, combining asserthigh and assert-low switches
NOR Remember This?? a b = a + b,
DeMorgan relations
a=1 SW1 closed, SW2 open y=0 = a
a+b=ab
a=0 SW1 open, SW2 closed y=1 = a
Lecture Notes Page 2.9
ECE 410, Prof. A. Mason
CMOS Push-Pull Logic
CMOS Push-Pull Networks
pMOS nMOS
on when input is low pushes output high on when input is high pulls output low
inputs
assert-low pMOS logic output assert-high nMOS logic
Operation: for a given logic function
one logic network (p or n) produces the logic function and pushes or pulls the output the other network acts as a load to complete the circuit, but is turned off by the logic inputs since only one network it active, there is no static current (between VDD and ground)
zero static power dissipation
ECE 410, Prof. A. Mason
Lecture Notes Page 2.10
Creating Logic Gates in CMOS
All standard Boolean logic functions (INV, NAND, OR, etc.) can be produced in CMOS push-pull circuits. Rules for constructing logic gates using CMOS
use a complementary nMOS/pMOS pair for each input connect the output to VDD through pMOS txs connect the output to ground through nMOS txs insure the output is always either high or low inputs
assert-low pMOS logic output assert-high nMOS logic
CMOS produces inverting logic
CMOS gates are based on the inverter outputs are always inverted logic functions
e.g., NOR, NAND rather than OR, AND
Logic Properties
DeMorgans Rules (a b) = a + b (a + b) = a b
Useful Logic Properties 1+x=1 0+x=x 1x=x 0x=0 x + x = 1 x x = 0 aa=a a+a=a ab + ac = a (b+c) ECE 410, Prof. A. Mason
Properties which can be proven (a+b)(a+c) = a+bc a + a'b = a + b
Lecture Notes Page 2.11
Review: Basic Transistor Operation
CMOS Circuit Basics
assert-low pMOS logic output assert-high nMOS logic
+ Vsg Vin
source gate drain
drain
pMOS Vsg > |Vtp| = on Vsg = VDD - Vin
Vg= Vin Vout 0 1 on = closed 1 ? off = open Vg= Vin Vout 0 ? off = open 1 0 on = closed
Vin
VDD VDD-|Vtp|
pMOS
inputs
off on on
Vin
gate
+ Vgs -
nMOS Vgs > Vtn = on
source
Vtn
off
nMOS
source is at lowest potential (nMOS) and highest potential (pMOS)
VDD VDD VDD Vy = 0 V
CMOS Pass Characteristics
nMOS
0V
+ Vgs=Vtn Vy = VDD-Vtn
nMOS
0 in 0 out VDD in VDD-Vtn out strong 0, weak 1 VDD in VDD out 0 in |Vtp| out strong 1, weak 0 Lecture Notes Page 2.12
0V
0V 0V Vy = VDD
pMOS
VDD
Vsg=|Vtp| +
Vy = |Vtp|
pMOS
ECE 410, Prof. A. Mason
Review: Switch-Level Boolean Logic
assert-high switch
y = x A, i.e. y = x if A = 1 series = AND
a AND b
parallel = OR
a OR b
assert-low switch
y = x A, i.e. y = x if A = 0 series = NOR parallel = NAND
ECE 410, Prof. A. Mason
=x a b
NOT (a OR b)
Lecture Notes Page 2.13
CMOS Inverter
Inverter Function
toggle binary logic of a signal Inverter Symbol
x y
Inverter Switch Operation Inverter Truth Table x y
=x
=VDD Vin=VDD
0 1
1 0
CMOS Inverter Schematic
input low output high nMOS off/open pMOS on/closed pMOS on output high (1) input high output low nMOS on/closed pMOS off/open nMOS on output low (0)
ECE 410, Prof. A. Mason
+ Vsg Vin
pMOS
Vout = Vin
nMOS
+ Vgs -
Lecture Notes Page 2.14
nMOS Logic Gates
We will look at nMOS logic first, more simple than CMOS nMOS Logic (no pMOS transistors)
assume a resistive load to VDD nMOS switches pull output low based on inputs
VDD VDD
(a) nMOS is off output is high (1) (b) nMOS is on output is low (0) nMOS NAND
nMOS Inverter
=VDD VDD
nMOS NOR
c = a+b parallel switches = OR function nMOS pulls low (NOTs the output)
c = ab series switches = AND function nMOS pulls low (NOTs the output)
Lecture Notes Page 2.15
ECE 410, Prof. A. Mason
CMOS NOR Gate
NOR Symbol
x y x+y
NOR Truth Table
x y x+y
Karnaugh map
true terms x 0 1 y 0 1 0 1 0 0
0 0 1 1
0 1 0 1
1 0 0 0
false terms
g(x,y) = x y 1 + x 0 + y 0
construct Sum of Products equation with all terms each term represents a MOSFET path to the output 1 terms are connected to VDD via pMOS 0 terms are connected to ground via nMOS
ECE 410, Prof. A. Mason Lecture Notes Page 2.16
CMOS NOR Gate
CMOS NOR Schematic
x y g(x,y) = x + y x
g(x,y) = x y 1 + x 0 + y 0
output is LOW if x OR y is true parallel nMOS output is HIGH when x AND y are false series pMOS
Notice: series-parallel arrangement
when nMOS in series, pMOS in parallel, and visa versa true for all static CMOS logic gates allows us to construct more complex logic functions
ECE 410, Prof. A. Mason
Lecture Notes Page 2.17
CMOS NAND Gate
NAND Symbol
x y xy
0 0 1 1 0 1 0 1 1 1 1 0
Truth Table
x y xy
K-map
x 0 1 y 0 1 1 1 1 0
CMOS Schematic
g(x,y) = (y1) + (x1) + (x y 0)
x
g(x,y) = x y y x
output is LOW if x AND y are true series nMOS output is HIGH when x OR y is false parallel pMOS
ECE 410, Prof. A. Mason
Lecture Notes Page 2.18
3-Input Gates
NOR3
x y z x+y+z
x y z g(x,y) = x+y+z x y
Alternate Schematic
what function?
NAND3
x y
g(x,y) = x y z z y x
x y z xyz
note shared gate inputs
is input order important? in series, parallel, both?
this schematic resembles how the circuit will look in physical layout
ECE 410, Prof. A. Mason Lecture Notes Page 2.19
Complex Combinational Logic
General logic functions
for example f = a (b + c), f = (d e) + a (b + c)
How do we construct the CMOS gate?
use DeMorgan principles to modify expression
construct nMOS and pMOS networks ab=a+b a+b=ab
use Structured Logic (covered only briefly in ECE410)
AOI (AND OR INV) OAI (OR AND INV)
ECE 410, Prof. A. Mason Lecture Notes Page 2.20
Using DeMorgan
DeMorgan Relations
NAND-OR rule ab=a+b
x
pMOS and bubble pushing
Parallel-connected pMOS
y
bubble pushing illustration
x y x y
equivalent to
x y x+y
g(x,y) = x + y = x y
x y
x+y
bubbles = inversions
assert-low OR creates NAND function
NOR-AND rule
x y x+y x
equivalent to
Series-connected pMOS
a+b=ab
x y g(x,y) = x y = x + y x y x y
x y
to implement pMOS this way, must push all bubbles to the inputs and remove all NAND/NOR output bubbles ECE 410, Prof. A. Mason
assert-low AND creates NOR function
Lecture Notes Page 2.21
Review: CMOS NAND/NOR Gates
NOR Schematic NAND Schematic
x
x y g(x,y) = x + y
y
g(x,y) = x y x
output is LOW if x OR y is true parallel nMOS output is HIGH when x AND y are false series pMOS
output is LOW if x AND y are true series nMOS output is HIGH when x OR y is false parallel pMOS
ECE 410, Prof. A. Mason
Lecture Notes Page 2.22
Rules for Constructing CMOS Gates
The Mathematical Method Given a logic function
F = f(a, b, c)
Reduce (using DeMorgan) to eliminate inverted operations
inverted variables are OK, but not operations (NAND, NOR)
Form pMOS network by complementing the inputs
Fp = f(a, b, c)
Form the nMOS network by complementing the output
Fn = f(a, b, c) = F
Construct Fn and Fp using AND/OR series/parallel MOSFET structures
series = AND, parallel = OR
EXAMPLE:
F = ab Fp = a b = a+b; Fn = ab = ab; OR/parallel AND/series
ECE 410, Prof. A. Mason
y x
g(x,y) = x y
Lecture Notes Page 2.23
CMOS Combinational Logic Example
Construct a CMOS logic gate to implement the function:
F = a (b + c)
b c a F
14 transistors (cascaded gates)
pMOS
Apply DeMorgan expansions
F = a + (b + c) F=a+(bc)
nMOS
Invert output for nMOS
Fn = a (b + c)
Invert inputs for pMOS
Fp = a + (b c)
6 transistors (CMOS)
a b c
Apply DeMorgan
none needed
Resulting Schematic
a b c F=a(b+c)
b a c
Resulting Schematic
F=a(b+c) a b c
F=a(b+c)
ECE 410, Prof. A. Mason
Lecture Notes Page 2.24
Structured Logic
Recall CMOS is inherently Inverting logic Can used structured circuits to implement general logic functions AOI: implements logic function in the order
AND, OR, NOT (Invert) Example: F = a b + c d
operation order: i) a AND b, c AND d, ii) (ab) OR (cd), iii) NOT
Inverted Sum-of-Products (SOP) form
OAI: implements logic function in the order
OR, AND, NOT (Invert) Example: G = (x+y) (z+w)
operation order: i) x OR y, z OR w, ii) (x+y) AND (z+w), iii) NOT
Use a structured CMOS array to realize such functions
ECE 410, Prof. A. Mason Lecture Notes Page 2.25
Inverted Product-of-Sums (POS) form
AOI/OAI nMOS Circuits
nMOS AOI structure
series txs in parallel X=ab+cd
nMOS OAI structure
series of parallel txs
Y = a+e b+f
eX
b X
error in textbook Figure 2.45
ECE 410, Prof. A. Mason Lecture Notes Page 2.26
AOI/OAI pMOS Circuits
pMOS AOI structure
series of parallel txs opposite of nMOS
(series/parallel)
pMOS OAI structure
series txs in parallel opposite of nMOS
(series/parallel)
Complete CMOS AOI/OAI circuits
ECE 410, Prof. A. Mason
Lecture Notes Page 2.27
Implementing Logic in CMOS
Reducing Logic Functions
fewest operations fewest txs minimized function to eliminate txs Example: x y + x z + x v = x (y + z + v)
5 operations: 3 AND, 2 OR # txs = ___? 3 operations: 1 AND, 2 OR # txs = ___?
Suggested approach to implement a CMOS logic function create nMOS network
invert output reduce function, use DeMorgan to eliminate NANDs/NORs implement using series for AND and parallel for OR complement each operation in nMOS network
i.e. make parallel into series and visa versa
ECE 410, Prof. A. Mason Lecture Notes Page 2.28
create pMOS network
CMOS Logic Example
Construct the function below in CMOS
F = a + b (c + d); remember AND operations occur before OR
nMOS
Group 1: c & d in parallel Group 2: b in series with G1 Group 3: a parallel to G2 follow same order in pMOS dont compliment inputs
pMOS
Group 1: c & d in series Group 2: b parallel to G1 Group 3: a in series with G2
Circuit has an OAOI organization (AOI with extra OR)
ECE 410, Prof. A. Mason Lecture Notes Page 2.29
Another Combinational Logic Example
Construct a CMOS logic gate which implements the function:
F = a (b + c)
pMOS
Apply DeMorgan expansions
none needed
nMOS
Invert output for nMOS
Fn = a (b + c)
Invert inputs for pMOS
Fp = a (b + c)
Apply DeMorgan
Fn = a + (b+c ) Fn = a + (b c)
Resulting Schematic ?
Resulting Schematic ?
ECE 410, Prof. A. Mason
Lecture Notes Page 2.30
Yet Another Combinational Logic Example
Implement the function below by constructing the nMOS network and complementing operations for the pMOS: F = a b (a + c)
nMOS
Invert Output Eliminate NANDs and NORs Reduce Function
Fn = a (b + c) Fn = a b + ( a c) Fn = a b (a + c) = a b + (a + c)
b c F=a b (a+c)
Resulting Schematic ? Complement operations for pMOS
Fp = a + (b c)
ECE 410, Prof. A. Mason
Lecture Notes Page 2.31
XOR and XNOR
Exclusive-OR (XOR)
ab=ab+ab not AOI form (no I)
Exclusive-NOR
ab=ab+ab inverse of XOR
XOR/XNOR in AOI form
XOR: a b = a b + a b, formed by complementing XNOR above XNOR: a b = a b + a b, formed by complementing XOR
thus, interchanging a and a (or b and b) converts from XOR to XNOR
ECE 410, Prof. A. Mason Lecture Notes Page 2.32
XOR and XNOR AOI Schematic
b a a b a
note: errors in textbook figure
XOR: a b = a b + a b XNOR: a b = a b + a b
ECE 410, Prof. A. Mason
uses exact same structure as generic AOI
Lecture Notes Page 2.33
CMOS Transmission Gates
Function
recall: pMOS passes a good 1 and nMOS passes a good 0
gated switch, capable of passing both 1 and 0
Formed by a parallel nMOS and pMOS tx
schematic
symbol
Controlled by gate select signals, s and s
if s = 1, y = x, switch is closed, txs are on if s = 0, y = unknown (high impedance),
switch open, txs off
ECE 410, Prof. A. Mason Lecture Notes Page 2.34
y = x s, for s=1
Transmission Gate Logic Functions
TG circuits used extensively in CMOS
good switch, can pass full range of voltage
(VDD-ground)
2-to-1 MUX using TGs
F = Po s + P1 s
ECE 410, Prof. A. Mason
Lecture Notes Page 2.35
More TG Functions
TG XOR and XNOR Gates
= a b, b = 1
ab=ab+ab
= a b, b = 1
ab=ab+ab
= a b, b = 1
= a b, b = 1
Using TGs instead of static CMOS
TG OR gate
= a, a = 1
f=a+ab
= a b, a = 1
f=a+b
ECE 410, Prof. A. Mason
Lecture Notes Page 2.36
