UNIVERSITY OF DAR ES SALAAM

COLLEGE OF INFORMATION AND COMMUNICATION TECHNOLOGIES

TE 442: DIGITAL ELECTRONICS FOR ENGINEERS III

LABORATORY REPORT

PARTICIPANTS:

SURNAME SANGA PETER KAMALI

FIRST NAME REG. NO. DAVID EMMANUEL PASCHAL

COURSE

2008-04-02076 TE 2008-04-03311 TE 2008-04-01354 TE

COURSE LECTURER: Dr. D. D. HAULE DATE: 5th June, 2012

TABLE OF CONTENTS

LAB QUESTION: DESIGN OF COMPARATORS (ARITHMETIC).........................................2 B1: DESIGN OF ONE BIT NETWORK COMPARE CIRCUIT .................................................3 1.1: THEORY AND PRINCIPLES .............................................................................................3 1.2: TRUTH TABLE ..................................................................................................................3 1.3: EQUATION .........................................................................................................................3 1.4: CIRCUIT .............................................................................................................................4 1.5: WAVEFORMS ....................................................................................................................5 B2: DETERMINATION OF THE WORST CASE DELAY PATH .............................................6 2.1: DATA ..................................................................................................................................6 2.2: SOLUTION .........................................................................................................................6 B3: DESIGN OF A CARRY-LOOK-AHEAD CIRCUIT ............................................................7 3.1: CIRCUIT .............................................................................................................................7 B4: COMBINING THE LOOK-AHEAD UNITS........................................................................8 4.1: CIRCUIT .............................................................................................................................8

LAB QUESTION: DESIGN OF COMPARATORS (ARITHMETIC) B0: Consider an n-bit comparator unit which accepts two (2) binary n-tuples A[n], B[n]; compares them as binary integers, and produces a 2-bit result Z[2] as follows: A is equal to B Z0, Z1 = 00; A is larger than B Z0, Z1 = 10; B is larger than A Z0, Z1 = 01. Example: If A = 01010111 and B = 00111110 would result in Z[2] = 10. Design a one bit network compare circuit, using CMOS NAND gates, which propagates from the most significant end to the least significant end. The network should be cascadable to an arbitrary length. Hint: You can use two "carry" variables with the same code as Z0, Z1 above. The high end boundary condition would be Cin[2]=00. Suppose that an inverter has a delay of one (1) delta; and that a NAND gate has a rise time of 1 delta and a fall time of (Fan-In + 2)/4 delta, where Fan-In is the number of NAND inputs. Let n=16 in B1 above. Determine the worst case delay path for the 16-bit compare unit and the delay value. Design a "carry" lookahead circuit for this compare unit. Sketch the design for a lookahead of 4 stages. Hint: You can use a first level "propagate" function of EQ = a`b` + ab, with two generate" functions: BG = a`b and AG = ab`. Combine 5 of the lookahead units from B3 with your design in B1. Using the same timing assumptions as in B2, determine the worst case delay path for the 16-bit compare unit with lookahead, and the delay value.

B1:

B2:

B3:

B4:

B1: DESIGN OF ONE BIT NETWORK COMPARE CIRCUIT 1.1: THEORY AND PRINCIPLES Comparing two binary words for equality is a commonly used operation in computer systems and device interfaces. A circuit that compares two binary words and indicates whether they are equal is called a comparator. Here we are required to design such kind of a comparator which compares the value of two 1-bit numbers and gives the output Z[2] to 00 when the first number A is equal to the second number B, Z[2] to 01 when the first number A is less than the second number B, and Z[2] to 10 when the first number A is larger than the second number B. The method is to extend the 1-bit comparator to an n-bit comparator by combining the logic relation between the 1-bit comparator outputs. We have used Circuit maker to draw the layout of the CMOS circuit, then extracted the spice file in Circuit maker and run under PSPICE to get the simulation result to verify if it works. 1.2: TRUTH TABLE To design a 1-bit comparator with two input nd two output as shown on Table 1 A 0 0 1 1 B 0 1 0 1 Z0 0 0 1 0 Z1 0 1 0 0

Table 1: Truth table for 1 bit compare circuit 1.3: EQUATION Hence, Z0 = AB and Z1 = AB

1.4: CIRCUIT Logic circuit using NAND gates:

U1A

U1B

U2B

U1C

Z1
U2A U1D

Z0

Logic circuit using CMOS gates:

Z0 A

Z1 B

1.5: WAVEFORMS

B2: DETERMINATION OF THE WORST CASE DELAY PATH 2.1: DATA Consider the following data for the 16-bit compare unit and the delay value. Inverter delay = 1 delta NAND gate has: -Rise time, tr = 1 delta -Fall time, tf = ((Fan-in + 2)/4) delta where Fan-in = number of NAND inputs 2.2: SOLUTION Using the formula t f = ((Fan-in + 2)/4) delays of the two categories of the NAND gates were obtained as follows: Those with Fan-in = 2 tf = ((2+2)/4) = 1 delta And thus, Delay = ((t r+tf)/2) = ((1+1)/2) = 1 delta Those with Fan-in = 3 tf = ((3+2)/4) = 1.25 delta And thus, Delay = ((t r+tf)/2) = ((1.25+1)/2) = 1.125 delta Worst case = 1+1.125+1 = 3.125 delta (For a single unit) Thus for a 16-compare unit = 50 delta

B3: DESIGN OF A CARRY-LOOK-AHEAD CIRCUIT 3.1: CIRCUIT Consider the following circuit:
A B

Gout Eout Lout

1-bit comparator

Gin

Lin

Where Gin = Greater input (carry) Lin = Low input (carry) Gout = Greater output Eout = Equal output Lout = Low output The variable Eout is 1 if A = B and Gin = 0 and Lin = 0. The variable Gout is 1 if A > B or if A = B and Gin = 1. The variable Lout is 1 if A < B or if A = B and Lin = 1.

B4: COMBINING THE LOOK-AHEAD UNITS 4.1: CIRCUIT Consider the circuit below for combined look-ahead units from B3 above

x3

y3

x2

y2

x1

y1

x0

y0

gt eq lt

G4 1-bit comp L4

G3 1-bit comp L3

G2 1-bit comp L2

G1 1-bit comp L1

G0 L0

Gin=0 Lin=0

Below is an example of the cascaded circuit:

The following are the waveforms from the 4-bit comparator network (cascading the 4 1-bit comapartors)