SP601 Hardware User Guide

UG518 (v1.6) July 18, 2011

 Copyright 20092011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DISCLAIMER The information disclosed to you hereunder (the Materials) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps.

Revision History
The following table shows the revision history for this document.
Date 07/15/09 08/19/09 Version 1.0 1.1 Initial Xilinx release. Added Appendix B, VITA 57.1 FMC LPC Connector Pinout. Updated Figure 1-17. Updated Table 1-4, Table 1-19, and Table 1-22. Added introductory paragraph to Appendix C, SP601 Master UCF. Miscellaneous typographical edits and new user guide template. Revision

05/17/10

1.2

Updated Figure 1-1, Figure 1-2, Figure 1-14, Figure 1-18, Table 1-9, Table 1-1, Table 1-11, and Table 1-16. Added Figure 1-7, Figure 1-8, and Table 1-13. Updated 9. VITA 57.1 FMC-LPC Connector, page 25, Appendix B, VITA 57.1 FMC LPC Connector Pinout, and Appendix C, SP601 Master UCF. Reversed order of 15. Configuration Options and 16. Power Management. Updated 1. Spartan-6 XC6SLX16-2CSG324 FPGA and 2. 128 MB DDR2 Component Memory. Added Table 1-26. Added UG394, Spartan-6 FPGA Power Management User Guide to Appendix D, References. Added Power System Test Points, including Table 1-25. Added note and revised header description to indicate the I/Os support LVCMOS25 signaling on page 34. Revised oscillator manufacturer information from Epson to SiTime on page page 23 and page 51. Corrected wording from PPM frequency jitter to PPM frequency stability in section Oscillator (Differential), page 23. Added Table 1-15, page 27.

06/16/10

1.3

09/24/10 02/16/11

1.4 1.5

07/18/11

1.6

SP601 Hardware User Guide

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UG518 (v1.6) July 18, 2011

Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chapter 1: SP601 Evaluation Board

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Related Xilinx Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1. Spartan-6 XC6SLX16-2CSG324 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. 128 MB DDR2 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. SPI x4 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4. Linear Flash BPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. 10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. USB-to-UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7. IIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Kb NV Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Socket (Single-Ended, 2.5V or 3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMA Connectors (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9. VITA 57.1 FMC-LPC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10. Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11. FPGA Awake LED and Suspend Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12. FPGA INIT and DONE LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13. User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14. FPGA_PROG_B Pushbutton Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15. Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Adapter and 5V Input Power Jack/Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Onboard Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power System Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 12 12 15 17 19 21 22 22 23 23 24 24 25 28 29 30 31 35 36 36 37 37 37 38

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Appendix A: Default Jumper and Switch Settings Appendix B: VITA 57.1 FMC LPC Connector Pinout Appendix C: SP601 Master UCF Appendix D: References

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Preface

About This Guide

This manual accompanies the Spartan-6 FPGA SP601 Evaluation Board and contains information about the SP601 hardware and software tools.

Guide Contents
This manual contains the following chapters: Chapter 1, SP601 Evaluation Board, provides an overview of the SP601 evaluation board and details the components and features of the SP601 board. Appendix A, Default Jumper and Switch Settings. Appendix B, VITA 57.1 FMC LPC Connector Pinout. Appendix C, SP601 Master UCF. Appendix D, References.

Additional Documentation
The following documents are available for download at http://www.xilinx.com/products/spartan6. Spartan-6 Family Overview This overview outlines the features and product selection of the Spartan-6 family. Spartan-6 FPGA Data Sheet: DC and Switching Characteristics This data sheet contains the DC and switching characteristic specifications for the Spartan-6 family. Spartan-6 FPGA Packaging and Pinout Specifications This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications. Spartan-6 FPGA Configuration User Guide This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques. Spartan-6 FPGA SelectIO Resources User Guide This guide describes the SelectIO resources available in all Spartan-6 devices. Spartan-6 FPGA Clocking Resources User Guide

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Preface: About This Guide

This guide describes the clocking resources available in all Spartan-6 devices, including the DCMs and PLLs. Spartan-6 FPGA Block RAM Resources User Guide This guide describes the Spartan-6 device block RAM capabilities. Spartan-6 FPGA DSP48A1 Slice User Guide This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs and provides configuration examples. Spartan-6 FPGA Memory Controller User Guide This guide describes the Spartan-6 FPGA memory controller block, a dedicated embedded multi-port memory controller that greatly simplifies interfacing Spartan-6 FPGAs to the most popular memory standards. Spartan-6 FPGA PCB Designers Guide This guide provides information on PCB design for Spartan-6 devices, with a focus on strategies for making design decisions at the PCB and interface level.

Additional Support Resources

To search the database of silicon and software questions and answers or to create a technical support case in WebCase, see the Xilinx website at: http://www.xilinx.com/support.

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Chapter 1

SP601 Evaluation Board

Overview
The SP601 board enables hardware and software developers to create or evaluate designs targeting the Spartan-6 XC6SLX16-2CSG324 FPGA. The SP601 provides board features for evaluating the Spartan-6 family that are common to most entry-level development environments. Some commonly used features include a DDR2 memory controller, a parallel linear flash, a tri-mode Ethernet PHY, general-purpose I/O (GPIO), and a UART. Additional functionality can be added through the VITA 57.1.1 expansion connector. Features, page 8 provides a general listing of the board features with details provided in Detailed Description, page 10.

Additional Information
Additional information and support material is located at: http://www.xilinx.com/sp601

This information includes: Current version of this user guide in PDF format Example design files for demonstration of Spartan-6 FPGA features and technology Demonstration hardware and software configuration files for the SP601 linear and SPI memory devices Reference Design Files Schematics in PDF format and DxDesigner schematic format Bill of materials (BOM) Printed-circuit board (PCB) layout in Allegro PCB format Gerber files for the PCB (Many free or shareware Gerber file viewers are available on the internet for viewing and printing these files.) Additional documentation, errata, frequently asked questions, and the latest news

For information about the Spartan-6 family of FPGA devices, including product highlights, data sheets, user guides, and application notes, see the Spartan-6 FPGA website at http://www.xilinx.com/support/documentation/spartan-6.htm.

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Chapter 1: SP601 Evaluation Board

Features
The SP601 board provides the following features (see Figure 1-2 and Table 1-1): 1. Spartan-6 XC6SLX16-2CSG324 FPGA 2. 128 MB DDR2 Component Memory 3. SPI x4 Flash 4. Linear Flash BPI 5. 10/100/1000 Tri-Speed Ethernet PHY 7. IIC Bus 8Kb NV memory External access 2-pin header VITA 57.1 FMC-LPC connector Oscillator (Differential) Oscillator Socket (Single-Ended, 2.5V or 3.3V)

8. Clock Generation

SMA Connectors (Differential) 9. VITA 57.1 FMC-LPC Connector 10. Status LEDs FPGA_AWAKE INIT DONE User LEDs User DIP switch User pushbuttons GPIO male pin header

13. User I/O

14. FPGA_PROG_B Pushbutton Switch 15. Configuration Options 3. SPI x4 Flash (both onboard and off-board) 4. Linear Flash BPI JTAG Configuration AC Adapter and 5V Input Power Jack/Switch Onboard Power Supplies

16. Power Management

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Block Diagram
Figure 1-1 shows a high-level block diagram of the SP601 and its peripherals.
X-Ref Target - Figure 1-1

LEDs DIP Switch GPIO Header

Part of FMC LPC Expansion Connector

10/100/1000 Ethernet GMII

USB JTAG Connector

DED Bank 0 2.5 V

DDR2
Bank 3 1.8V

Spartan-6
XC6SLX16
U1

Parallel Flash
Bank 1 2.5V

Differential Clock Clock Socket SMA Clock

Pushbuttons
Bank 2 2.5V

Part of FMC LPC Expansion Connector

IIC EEPROM and Header

MODE DIP Switch

SPI x4 or External Config

USB UART

UG518_01_090909

Figure 1-1:

SP601 Features and Banking

Related Xilinx Documents

Prior to using the SP601 Evaluation Board, users should be familiar with Xilinx resources. See the following locations for additional documentation on Xilinx tools and solutions: ISE: www.xilinx.com/ise Answer Browser: www.xilinx.com/support Intellectual Property: www.xilinx.com/ipcenter

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Chapter 1: SP601 Evaluation Board

Detailed Description
Figure 1-2 shows a board photo with numbered features corresponding to Table 1-1 and the section headings in this document.
X-Ref Target - Figure 1-2

14 15

13

9 2 7 11 4 8 5 6 10 13
UG518_02_091009

16

3 12

Figure 1-2:

SP601 Board Photo

The numbered features in Figure 1-2 correlate to the features and notes listed in Table 1-1. Table 1-1:
Number 1 2 3 4

SP601 Features
Feature Notes XC6SLX16-2CSG324 Elpida EDE1116ACBG 1 Gb DDR2 SDRAM SPI select and External Headers StrataFlash 8-bit (J3 device), 3 pins shared w/ SPI x4 5 8 8 Schematic Page

Spartan-6 FPGA DDR2 Component SPI x4 Flash and Headers Linear Flash BPI

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Detailed Description

Table 1-1:
Number 5 6 7 8 9 10 11 12

SP601 Features (Contd)

Feature Notes GMII Marvell Alaska PHY Uses CP2103 Serial-to-USB connection Goes to Header and VITA 57.1 FMC Differential, Single-Ended, Differential LVDS signals, clocks, PRSNT Ethernet PHY Status FPGA Awake LED, Suspend Header FPGA INIT, DONE User I/O (active-High) User I/O (active-High) User I/O, CPU_RESET (active-High) 6 pins x 2 male header with 8 I/Os (active-High) FPGA_PROG_B Cypress USB to JTAG download cable logic Power Management Schematic Page 7 10 10 9 6 7 8 9 9 9 9 10 9 14, 15 11,12,13

10/100/1000 Ethernet PHY RS232 UART (USB Bridge) IIC Clock, socket, SMA VITA 57.1 FMC-LPC connector LEDs LED, Header LEDs LED DIP Switch

13

Pushbutton 12-pin (8 I/O) Header

14 15 16

Pushbutton USB JTAG Onboard Power

1. Spartan-6 XC6SLX16-2CSG324 FPGA

A Xilinx Spartan-6 XC6SLX16-2CSG324 FPGA is installed on the SP601 Evaluation Board.

References
See the Spartan-6 FPGA Data Sheet. [Ref 1]

Configuration
The SP601 supports configuration in the following modes: Master SPI x4 Master SPI x4 with off-board device BPI JTAG (using the included USB-A to Mini-B cable)

For details on configuring the FPGA, see 15. Configuration Options. The Mode DIP switch SW2 is set to M[1:0] = 01 Master SPI default.

References
See the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]

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Chapter 1: SP601 Evaluation Board

I/O Voltage Rails

There are four available banks on the LX16-CSG324 device. Banks 0, 1, and 2 are connected for 2.5V I/O. Bank 3 is used for the 1.8V DDR2 component memory interface of Spartan-6 FPGAs hard memory controller. The voltage applied to the FPGA I/O banks used by the SP601 board is summarized in Table 1-2. Table 1-2: I/O Voltage Rail of FPGA Banks
I/O Voltage Rail 2.5V 2.5V 2.5V 1.8V

FPGA Bank 0 1 2 3

References
See the Spartan-6 FPGA documentation for more information at http://www.xilinx.com/support/documentation/spartan-6.htm.

2. 128 MB DDR2 Component Memory

There are 128 MB of DDR2 memory available on the SP601 board. A 1-Gb Elpida EDE1116ACBG (84-ball) DDR2 memory component is accessible through Bank 3 of the LX16 device. The Spartan-6 FPGA hard memory controller is used for data transfer across the DDR2 memory interfaces 16-bit data path using SSTL18 signaling. The SP601 board supports the standard VCCINT setting of 1.20V 5%. This setting provides the standard memory controller block (MCB) performance of 625 Mb/s for DDR2 memory in a -2 speed grade device. Signal integrity is maintained through DDR2 resistor terminations and memory on-die terminations (ODT), as shown in Table 1-3 and Table 1-4. Table 1-3: Termination Resistor Requirements
Board Termination 49.9 to VTT 49.9 to VTT 49.9 to VTT 49.9 to VTT 49.9 to VTT 100 to GND 4.7K to GND 4.7K to GND ODT ODT ODT On-Die Termination

Signal Name DDR2_A[14:0] DDR2_BA[2:0] DDR2_RAS_N DDR2_CAS_N DDR2_WE_N DDR2_CS_N DDR2_CKE DDR2_ODT DDR2_DQ[15:0] DDR2_UDQS[P,N], DDR2_LDQS[P,N] DDR2_UDM, DDR2_LDM

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Detailed Description

Table 1-3:

Termination Resistor Requirements (Contd)

Board Termination 100 differential at memory component On-Die Termination

Signal Name DDR2_CK[P,N]

Notes:

1. Nominal value of VTT for DDR2 interface is 0.9V.

Table 1-4:

FPGA On-Chip (OCT) Termination External Resistor Requirements

FPGA U1 Pin ZIO RZQ FPGA Pin Number L6 C2 Board Connection for OCT No Connect 100 to GROUND

Table 1-5 shows the connections and pin numbers for the DDR2 Component Memory. Table 1-5:
FPGA U1 Pin J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6

DDR2 Component Memory Connections

Memory U2 Schematic Net Name Pin Number DDR2_A0 DDR2_A1 DDR2_A2 DDR2_A3 DDR2_A4 DDR2_A5 DDR2_A6 DDR2_A7 DDR2_A8 DDR2_A9 DDR2_A10 DDR2_A11 DDR2_A12 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12

L2 L1 K2 K1 H2 H1 J3

DDR2_DQ0 DDR2_DQ1 DDR2_DQ2 DDR2_DQ3 DDR2_DQ4 DDR2_DQ5 DDR2_DQ6

G8 G2 H7 H3 H1 H9 F1

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6

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Chapter 1: SP601 Evaluation Board

Table 1-5:
FPGA U1 Pin J1 M3 M1 N2 N1 T2 T1 U2 U1

DDR2 Component Memory Connections (Contd)

Memory U2 Schematic Net Name Pin Number DDR2_DQ7 DDR2_DQ8 DDR2_DQ9 DDR2_DQ10 DDR2_DQ11 DDR2_DQ12 DDR2_DQ13 DDR2_DQ14 DDR2_DQ15 F9 C8 C2 D7 D3 D1 D9 B1 B9 Pin Name DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

F2 F1 E1

DDR2_BA0 DDR2_BA1 DDR2_BA2

L2 L3 L1

BA0 BA1 BA2

E3 L5 K5 K6 G3 G1 H7 L4 L3 P2 P1 K3 K4

DDR2_WE_B DDR2_RAS_B DDR2_CAS_B DDR2_ODT DDR2_CLK_P DDR2_CLK_N DDR2_CKE DDR2_LDQS_P DDR2_LDQS_N DDR2_UDQS_P DDR2_UDQS_N DDR2_LDM DDR2_UDM

K3 K7 L7 K9 J8 K8 K2 F7 E8 B7 A8 F3 B3

WE RAS CAS ODT CK CK CKE LDQS LDQS UDQS UDQS LDM UDM

References
See the Elpida DDR2 SDRAM Specifications for more information. [Ref 11] Also, see the Spartan-6 FPGA Memory Controller User Guide. [Ref 3]

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Detailed Description

3. SPI x4 Flash
The Xilinx Spartan-6 FPGA hosts a SPI interface which is accessible to the Xilinx iMPACT configuration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are 3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flash through a 2.5V bank. The XC6SLX16-2CSG324 is a master device when accessing an external SPI flash memory device. The SP601 SPI interface has two parallel connected configuration options (see Figure 1-4): an SPI X4 (Winbond W25Q64VSFIG) 64-Mb flash memory device and a flash programming header (J12). J12 supports a user-defined SPI mezzanine board. The SPI configuration source is selected via SPI select jumper J15. For details on configuring the FPGA, see 15. Configuration Options.
X-Ref Target - Figure 1-3

SPI Prog J12

1 2 3

FPGA_PROG_B FPGA_D2_MISO3 FPGA_D1_MISO2 SPI_CS_B FPGA_MOSI_CSI_B_MISO0 FPGA_D0_DIN_MISO_MISO1 FPGA_CCLK GND VCC3V3

TMS TDI

4 5 6 7 8 9

Silkscreen

TDO TCK GND 3V3

HDR_1X9
UG518_04_040910

Figure 1-3:

J12 SPI Flash Programming Header

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Chapter 1: SP601 Evaluation Board

X-Ref Target - Figure 1-4

U1 FPGA SPI INTERFACE

U17 DIN,DOUT,CCLK

J12

SPI X4 FLASH MEMORY

SPIX4_CS_B WINBOND W25Q64VSFIG ON = SPI X4 U17 OFF = SPI EXT. J12 2 1

SPI_CS_B

J15 SPI SELECT JUMPER

SPI PROGRAM HEADER

UG518_07_070809

Figure 1-4: SPI Flash Interface Topology Table 1-6:

FPGA U1 Pin V2 V14 T14 V3 T13 R13 R15

SPI x4 Memory Connections

SPI MEM U17 Schematic Net Name Pin # FPGA_PROG_B FPGA_D2_MISO3 FPGA_D1_MISO2_R SPI_CS_B FPGA_MOSI_CSI_B_MISO0 FPGA_D0_DIN_MISO_MISO1 FPGA_CCLK 15 8 16 DIN IO1_DOUT CLK 1 9 IO3_HOLD_B IO2_WP_B Pin Name SPI HDR J12 Pin Pin Name Number 1 2 3 4 5 6 7 8 9 TMS TDI TDO TCK GND VCC3V3

J15.2

SPIX4_CS_B

CS_B

References
See the Winbond Serial Flash Memory Data Sheet for more information. [Ref 12] See the XPS Serial Peripheral Interface Data Sheet for more information. [Ref 4]

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Detailed Description

4. Linear Flash BPI

An 8-bit (16 MB) Numonyx linear flash memory (TE28F128J3D-75) (J3D type) is used to provide non-volatile bitstream, code, and data storage. The J3D devices operate at 3.0V; the Spartan-6 FPGA I/Os are 3.3V tolerant and provide electrically compatible logic levels to directly access the linear flash BPI through a 2.5V bank. For details on configuring the FPGA, see 15. Configuration Options.
X-Ref Target - Figure 1-5

U1

U10

FPGA BPI FLASH INTERFACE

ADDR, DATA, CTRL

NUMONYX TYPE J3vD T28F128J3D-75

UG518_09_070809

Figure 1-5: Table 1-7:

Linear Flash BPI Interface

BPI Memory Connections

BPI Memory U10 Schematic Net Name Pin Number Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 FLASH_A0 FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 32 28 27 26 25 24 23 22 20 19 18 17 13 12 11 10 8

FPGA U1 Pin K18 K17 J18 J16 G18 G16 H16 H15 H14 H13 F18 F17 K13 K12 E18 E16 G13

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Table 1-7:

BPI Memory Connections (Contd)

BPI Memory U10 Schematic Net Name Pin Number Pin Name A17 A18 A19 A20 A21 A22 A23 A24 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WE_B OE_B CE0 RP_B FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_A22 FLASH_A23 FLASH_A24 FPGA_D0_DIN_MISO_MISO1 FPGA_D1_MISO2 FPGA_D2_MISO3 FLASH_D3 FLASH_D4 FLASH_D5 FLASH_D6 FLASH_D7 FLASH_WE_B FLASH_OE_B FLASH_CE_B FMC_PWR_GOOD_FLASH_RST_B 7 6 5 4 3 1 30 56 33 35 38 40 44 46 49 51 55 54 14 16

FPGA U1 Pin H12 D18 D17 G14 F14 C18 C17 F16 R13 T14 V14 U5 V5 R3 T3 R5 M16 L18 L17 B3

Note: Memory U10 pin 56 address A24 is not connected on the 16 MB device. It is made available
for larger density devices.

References
See the Numonyx Embedded Flash Memory Data Sheet for more information. [Ref 13] In addition, see the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]

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5. 10/100/1000 Tri-Speed Ethernet PHY

The SP601 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernet communications at 10, 100, or 1000 Mb/s. The board supports a GMII/MII interface from the FPGA to the PHY. The PHY connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector with built-in magnetics. On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY address 0b00111 using the settings shown in Table 1-8. These settings can be overwritten via software commands passed over the MDIO interface. Table 1-8:
Pin CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6

PHY Configuration Pins

Connection on Bit[2] Bit[1] Bit[0] Board Definition and Value Definition and Value Definition and Value VCC 2.5V Ground VCC 2.5V VCC 2.5V VCC 2.5V VCC 2.5V PHY_LED_RX PHYADR[2] = 1 ENA_PAUSE = 0 ANEG[3] = 1 ANEG[0] = 1 HWCFG_MD[2] = 1 DIS_FC = 1 SEL_BDT = 0 PHYADR[1] = 1 PHYADR[4] = 0 ANEG[2] = 1 ENA_XC = 1 HWCFG_MD[1] = 1 DIS_SLEEP = 1 INT_POL = 1 PHYADR[0] = 1 PHYADR[3] = 0 ANEG[1] = 1 DIS_125 = 1 HWCFG_MD[0] = 1 HWCFG_MD[3] = 1 75/50 = 0

Table 1-9:

Ethernet PHY Connections

U3 M88E111 Schematic Net Name Pin Number Pin Name MDIO MDC INT_B RESET_B CRS COL RXCLK RXER RXDV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 PHY_MDIO PHY_MDC PHY_INT PHY_RESET PHY_CRS PHY_COL PHY_RXCLK PHY_RXER PHY_RXCTL_RXDV PHY_RXD0 PHY_RXD1 PHY_RXD2 PHY_RXD3 PHY_RXD4 PHY_RXD5 33 35 32 36 115 114 7 8 4 3 128 126 125 124 123

FPGA U1 Pin P16 N14 J13 L13 M13 L14 L16 P17 N18 M14 U18 U17 T18 T17 N16

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Table 1-9:

Ethernet PHY Connections (Contd)

U3 M88E111 Schematic Net Name Pin Number Pin Name RXD6 RXD7 GTXCLK TXCLK TXER TXEN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 PHY_RXD6 PHY_RXD7 PHY_TXC_GTPCLK PHY_TXCLK PHY_TXER PHY_TXCTL_TXEN PHY_TXD0 PHY_TXD1 PHY_TXD2 PHY_TXD3 PHY_TXD4 PHY_TXD5 PHY_TXD6 PHY_TXD7 121 120 14 10 13 16 18 19 20 24 25 26 28 29

FPGA U1 Pin N15 P18 A9 B9 A8 B8 F8 G8 A6 B6 E6 F7 A5 C5

References
See the Marvell Alaska Gigabit Ethernet Transceivers product page for more information. [Ref 16] Also, see the LogiCORE IP Tri-Mode Ethernet MAC User Guide. [Ref 5]

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6. USB-to-UART Bridge
The SP601 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U4) which allows connection to a host computer with a USB cable. The USB cable is supplied in this evaluation kit (Type A end to host computer, Type Mini-B end to SP601 connector J9). Table 1-10 details the SP601 J9 pinout. Xilinx UART IP is expected to be implemented in the FPGA fabric. The FPGA supports the USB-to-UART bridge using four signal pins, transmit (TX), receive (RX), Request to Send (RTS), and Clear to Send (CTS). Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit the CP2103GM USB-to-UART bridge to appear as a COM port to host computer communications application software (for example, HyperTerm or TeraTerm). The VCP device driver must be installed on the host PC prior to establishing communications with the SP601. Refer to the SP601 Getting Started Guide for driver installation instructions. Table 1-10: USB Type B Pin Assignments and Signal Definitions
Signal Name VBUS USB_DATA_N USB_DATA_P GROUND Description +5V from host system (not used) Bidirectional differential serial data (N-side) Bidirectional differential serial data (P-side) Signal ground

USB Connector Pin 1 2 3 4

Table 1-11:

CP2103GM Connections
UART Function in FPGA RTS, output CTS, input TX, data out RX, data in Schematic Net Name USB_1_CTS USB_1_RTS USB_1_RX USB_1_TX U4 CP2103GM Pin 22 23 24 25 UART Function in CP2103GM CTS, input RTS, output RXD, data in TXD, data out

FPGA U1 Pin U10 T5 L12 K14

References
Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers. In addition, see some of the Xilinx UART IP specifications at: http://www.xilinx.com/support/documentation/ip_documentation/xps_uartlite.pdf http://www.xilinx.com/support/documentation/ip_documentation/xps_uart16550.pdf

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7. IIC Bus
The SP601 IIC bus hosts four items: FPGA U1 IIC interface 2-pin IIC external access header 8-Kb NV Memory VITA 57.1 FMC Connector J1

The SP601 IIC bus topology is shown in Figure 1-6.

X-Ref Target - Figure 1-6

VITA 57.1 FMC-LPC U1 C30 J1 C31

FMC-LPC GA0=1 GA1=0

U7 IIC_SDA_MAIN IIC_SCL_MAIN ST MICRO M24 C08-WDW6TP

Address range 54-56 0b10101000b1010110

FPGA IIC INTERFACE

1 J16

IIC EXTERNAL ACCESS CONNECTOR

UG518_13_070809

Figure 1-6:

IIC Bus Topology

The IIC Bus on the SP601 provides access to a 2-pin header, the onboard 8-Kb EEPROM, and the VITA 57.1 FMC interface. The user must ensure there are no IIC address conflicts with the onboard EEPROM address when attaching additional IIC devices via FMC or the IIC 2-pin header. Note that FMC Mezzanine cards are designed with 2-Kb IIC EEPROMs and will not conflict with the Carrier Card (SP601) 8-Kb EEPROM address range. This is because 2-Kb EEPROMs reside below the 8-Kb EEPROM space. See the VITA 57.1 specification along with any IIC 2-Kbit EEPROM data sheet for more details.

8-Kb NV Memory
The SP601 hosts a 8-Kb ST Microelectronics M24C08-WDW6TP IIC parameter storage memory device (U7). The IIC address of U7 is 0b1010100, and U7 is not write protected (WP pin 7 is tied to GND). Table 1-12: IIC Memory Connections
SPI Memory U7 FPGA U1 Pin Not Applicable Not Applicable Schematic Net Name Pin Number Tied to GND Tied to GND 1 2 Pin Name A0 A1

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Table 1-12:

IIC Memory Connections (Contd)

SPI Memory U7 Schematic Net Name Pin Number Pin Name A2 SDA SCL WP Pulled up (0) to VCC3V3 IIC_SDA_MAIN IIC_SCL_MAIN Tied to GND 3 5 6 7

FPGA U1 Pin Not Applicable N10 P11 Not Applicable

References
See the ST Micro M24C08 Data Sheet for more information. [Ref 17] In addition, see the Xilinx XPS IIC Bus Interface Data Sheet. [Ref 6] Also, see 9. VITA 57.1 FMC-LPC Connector, page 25.

8. Clock Generation
There are three clock sources available on the SP601.

Oscillator (Differential)
The SP601 has one 2.5V LVDS differential 200 MHz oscillator (U5) soldered onto the board and wired to an FPGA global clock input. Crystal oscillator: SiTime SiT9102AI-243N25E200.00000 PPM frequency stability: 50 ppm

References
See the SiTime SiT9102 Data Sheet for more information. [Ref 14]

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Oscillator Socket (Single-Ended, 2.5V or 3.3V)

One populated single-ended clock socket (X2) is provided for user applications. The option of 3.3V or 2.5V power may be selected via a 0 resistor selection. The SP601 board is shipped with a 27 MHz 2.5V oscillator installed. Figure 1-7 shows the unpopulated user oscillator socket, indicating the socket pin 1 location. Figure 1-8 shows the oscillator installed, indicating its pin 1 location.
X-Ref Target - Figure 1-7

Socket has notch in crossbar

Silkscreened outline has beveled corner

UG518_05_101409

Figure 1-7:
X-Ref Target - Figure 1-8

SP601 Oscillator Socket Pin 1 Location Identifiers

Oscillator top has corner dot marking

Oscillator body has one square corner

UG518_06_091009

Figure 1-8:

SP601 Oscillator Pin 1 Location Identifiers

SMA Connectors (Differential)

A high-precision clock signal can be provided to the FPGA using differential clock signals through the onboard 50 SMA connectors J8 (N) and J7 (P). Table 1-13: SP601 Clock Source Connections
FPGA U1 Pin K16 K15 V10 H18 H17 Schematic Net Name Pin Number Pin Name SYSCLK_N SYSCLK_P USER_CLOCK SMACLK_N SMACLK_P 5 4 5 J8.1 J7.1 OUT_B OUT OUT Source U5 200 MHz OSC X2 27 MHz OSC USER_SMA_CLOCK SMA Connectors

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9. VITA 57.1 FMC-LPC Connector

The VITA 57.1 FMC expansion connector (J1) on the SP601 implements the VITA 57.1.1 LPC format of the VITA 57.1 FMC standard specification. The VITA 57.1 FMC-LPC connector provides 68 single-ended (34 differential) user-defined signals. The VITA 57.1 FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low Pin Count (LPC) implementation. A common 10 x 40 position (400 pin locations) connector form factor is used for both versions. The HPC version has 400 pins present, the LPC version, 160 pins. The Samtec connector system is rated for signaling speeds up to 9 GHz (18 Gb/s) based on a -3dB insertion loss point within a two-level signaling environment. Refer to the Samtec website for data sheets and characterization information for the RoHS-compliant VITA 57.1 FMC-LPC connector (ASP-134603-01) and its mate. Note: The SP601 board VADJ voltage for the FMC LPC connector (J1) is fixed at 2.5V (nonadjustable). The 2.5V rail cannot be turned off. The FMC LPC J1 connector is a keyed connector oriented so that a plug-on card faces away from the SP601 board. The SP601 VITA 57.1 FMC interface is compatible with 2.5V mezzanine cards capable of supporting 2.5V VADJ.

Table 1-14 shows the VITA 57.1 FMC LPC connections. The connector pinout is in Appendix B, VITA 57.1 FMC LPC Connector Pinout. Any signal named FMC_HPC_xxxx that is wired between a U1 FPGA pin and some other device does not appear in this table. The SP601 supports all FMC LA Bus connections available on the FMC LPC connector, (LA[00:33]) along with all available FMC M2C clock pairs (CLK0_M2C_P/N and CLK1_M2C_P/N). The SP601 does not support the FMC DP Bus connections since the SP601 does not support any Gigabit Transceivers on the FMC DP Bus. Therefore, DP0_C2M_P/N, DP0_M2C_P/N and GBTCLK0_M2C_P/N are not supported by the SP601 FMC interface. For more details about FMC, see the VITA57.1 specification available at http://www.vita.com/fmc.html. Table 1-14:
J1 FMC LPC Pin C10 C11 C14 C15 C18 C19 C22 C23 C26 C27 C30 C31

VITA 57.1 FMC LPC Connections

Schematic Net Name FMC_LA06_P FMC_LA06_N FMC_LA10_P FMC_LA10_N FMC_LA14_P FMC_LA14_N FMC_LA18_CC_P FMC_LA18_CC_N FMC_LA27_P FMC_LA27_N IIC_SCL_MAIN IIC_SDA_MAIN U1 FPGA Pin D12 C12 D8 C8 B2 A2 R10 T10 R11 T11 P11 N10 J1 FMC LPC Pin D1 D8 D9 D11 D12 D14 D15 D17 D18 D20 D21 D23 Schematic Net Name FMC_PWR_GOOD_FLASH_RST_B FMC_LA01_CC_P FMC_LA01_CC_N FMC_LA05_P FMC_LA05_N FMC_LA09_P FMC_LA09_N FMC_LA13_P FMC_LA13_N FMC_LA17_CC_P FMC_LA17_CC_N FMC_LA23_P U1 FPGA Pin B3 D11 C11 B14 A14 G11 F10 B11 A11 R8 T8 N5

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Table 1-14:
J1 FMC LPC Pin

VITA 57.1 FMC LPC Connections (Contd)

Schematic Net Name U1 FPGA Pin J1 FMC LPC Pin D24 D26 D27 Schematic Net Name FMC_LA23_N FMC_LA26_P FMC_LA26_N U1 FPGA Pin P6 U7 V7

G2 G3 G6 G7 G9 G10 G12 G13 G15 G16 G18 G19 G21 G22 G24 G25 G27 G28 G30 G31 G33 G34 G36 G37

FMC_CLK1_M2C_P FMC_CLK1_M2C_N FMC_LA00_CC_P FMC_LA00_CC_N FMC_LA03_P FMC_LA03_N FMC_LA08_P FMC_LA08_N FMC_LA12_P FMC_LA12_N FMC_LA16_P FMC_LA16_N FMC_LA20_P FMC_LA20_N FMC_LA22_P FMC_LA22_N FMC_LA25_P FMC_LA25_N FMC_LA29_P FMC_LA29_N FMC_LA31_P FMC_LA31_N FMC_LA33_P FMC_LA33_N

T9 V9 D9 C9 C13 A13 F11 E11 D6 C6 C7 A7 N7 P8 R7 T7 M11 N11 M8 N8 T6 V6 M10 N9

H2 H4 H5 H7 H8 H10 H11 H13 H14 H16 H17 H19 H20 H22 H23 H25 H26 H28 H29 H31 H32 H34 H35 H37 H38

FMC_PRSNT_M2C_L FMC_CLK0_M2C_P FMC_CLK0_M2C_N FMC_LA02_P FMC_LA02_N FMC_LA04_P FMC_LA04_N FMC_LA07_P FMC_LA07_N FMC_LA11_P FMC_LA11_N FMC_LA15_P FMC_LA15_N FMC_LA19_P FMC_LA19_N FMC_LA21_P FMC_LA21_N FMC_LA24_P FMC_LA24_N FMC_LA28_P FMC_LA28_N FMC_LA30_P FMC_LA30_N FMC_LA32_P FMC_LA32_N

U13 C10 A10 C15 A15 B16 A16 E7 E8 B12 A12 G9 F9 N6 P7 T4 V4 U8 V8 U11 V11 T12 V12 U15 V15

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Table 1-15:

Power Supply Voltages for LPC Connector

Voltage Fixed 2.5V NC 0-VADJ NC 3.3V 3.3V 12V Number of Pins 2 0 1 0 1 4 2 Maximum Current 2A 0A 0.001A 0A 0.020A 3A 1A Tolerance 5% N/A 2% N/A 5% 5% 5%

Voltage Supply VADJ VIO_B_M2C VREF_A_M2C VREF_B_M2C 3P3VAUX 3P3V 12P0V

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10. Status LEDs

Table 1-16 defines the status LEDs. Table 1-16:
Reference Designator DS1 DS2 DS3 DS4 DS5 DS6 DS7 DS8 DS9

Status LEDs
Signal Name FMC_PWR_GOOD_FLASH_RST_B PHY_LED_LINK10 PHY_LED_LINK100 PHY_LED_LINK1000 PHY_LED_DUPLEX PHY_LED_RX PHY_LED_TX FPGA_AWAKE FPGA_DONE Color Green Green Green Green Green Green Green Green Green Label PWR GOOD 10 100 1000 DUP RX TX AWAKE DONE Description Indicates power available for VITA 57.1 FMC expansion connector. Indicates link speed 10 Mb/s. Indicates link speed 100 Mb/s. Indicates link speed 1 Gb/s. Indicates duplex data. Indicates RX data activity. Indicates TX data activity. FPGA is not in low-power suspend mode. Illuminates to indicate the status of the DONE pin when the FPGA is successfully configured. Illuminates after power-up to indicate that the FPGA has successfully powered up and completed its internal power-on process. Illuminates when 5V supply is applied. STATUS USB to JTAG logic. Illuminates to indicate that the board power is good.

DS10

FPGA_INIT

Red

INIT

DS15 DS16 DS17

VCC5 LED_GRN, LED_RED LTC_PWR_GOOD

Green Green/ Red Green

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11. FPGA Awake LED and Suspend Jumper

The suspend mode jumper permits the FPGA to enter an inactive, "suspend" mode. The FPGA Awake LED DS8 will go out when the FPGA enters this mode.
X-Ref Target - Figure 1-9

FPGA AWAKE VCC2V5

DS8

Figure 1-9: Table 1-17:

FPGA U1 Pin P15 R16

See the Spartan-6 FPGA Power Management User Guide for more information. [Ref 10]

LED-GRN-SMT 1 2

FPGA SUSPEND
1 1 R18 4.7K 5% 1/16W

J14 Suspend Jumper

R88 27.4 1% 1/16W

H-1X2

1 J14

OFF = AWAKE (default) ON = SUSPEND

UG518_19_070809

FPGA Awake LED and Suspend Jumper

FPGA Awake/Suspend Mode Jumper Connections

Schematic Net Name FPGA_AWAKE FPGA_SUSPEND Suspend Mode I/O Awake LED DS8.2 Suspend J14.2

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12. FPGA INIT and DONE LEDs

The typical Xilinx FPGA power up and configuration status LEDs are present on the SP601. The INIT LED DS10 comes on after the FPGA powers up and completes its internal poweron process. The DONE LED DS9 comes on after the FPGA programming bitstream has been downloaded and the FPGA successfully configured.
X-Ref Target - Figure 1-10

VCC2V5

VCC2V5
2

R113 332 1% 1/16W

FPGA DONE
2 2 LED-RED-SMT
DS10

LED-GRN-SMT

DS9

VCC2V5

INIT_B = 0, LED: ON INIT_B = 1, LED: OFF

1 2

R23 4.7K 5% 1/16W

1 2

FPGA INIT B

R90 27.4 1% 1/16W

1 2

R89 27.4 1% 1/16W

UG518_21_070809

Figure 1-10: Table 1-18:

FPGA INIT and DONE LEDs

FPGA INIT and DONE LED Connections

Schematic Net Name FPGA_INIT_B FPGA_DONE Controlled LED DS10 INIT DS9 DONE

FPGA U1 Pin U3 V17

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13. User I/O

The SP601 provides the following user and general purpose I/O capabilities: User LEDs User DIP switch Pushbutton switches CPU Reset pushbutton switch GPIO male pin header

User LEDs
The SP601 provides four active high, green LEDs, as described in Figure 1-11 and Table 1-19.
X-Ref Target - Figure 1-11

GPIO LED 3 GPIO LED 2 GPIO LED 1 GPIO LED 0

2 LED-GRN-SMT LED-GRN-SMT
DS11

2 LED-GRN-SMT
DS12

2 LED-GRN-SMT
DS13

2
DS14

1 2

R91 27.4 1% 1/16W

1 2

R92 27.4 1% 1/16W

1 2

R93 27.4 1% 1/16W

1 2

R94 27.4 1% 1/16W

UG518_23_070809

Figure 1-11: User LEDs Table 1-19:

Reference Designator DS11 DS12

User LEDs
Signal Name GPIO_LED_0 GPIO_LED_1 Color Green Green Label FPGA Pin E13 C14

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Table 1-19:
Reference Designator DS13 DS14

User LEDs (Contd)

Signal Name GPIO_LED_2 GPIO_LED_3 Color Green Green Label FPGA Pin C4 A4

User DIP switch

The SP601 includes an active high four pole DIP switch, as described in Figure 1-12 and Table 1-20.
X-Ref Target - Figure 1-12

VCC2V5

GPIO_SWITCH_0 GPIO_SWITCH_1 GPIO_SWITCH_2 GPIO_SWITCH_3

1 2 3 4

8 7 6 5

SW8 SDMX-4-X

1 2

R22 4.7K 5% 1/16W

1 2

R21 4.7K 5% 1/16W

1 2

R20 4.7K 5% 1/16W

1 2

R19 4.7K 5% 1/16W

UG518_24_070809

Figure 1-12: Table 1-20:

User DIP Switch

User DIP Switch Connections

Schematic Net Name GPIO_SWITCH_0 GPIO_SWITCH_1 GPIO_SWITCH_2 GPIO_SWITCH_3 SW8 Pin Number 1 2 3 4

FPGA U1 Pin D14 E12 F12 V13

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User Pushbutton Switches

The SP601 provides five active high pushbutton switches: SW6, SW4, SW5, SW7 and SW9. The five pushbuttons all have the same topology as the sample shown in Figure 1-13. Four pushbuttons are assigned as GPIO, and the fifth is assigned as a CPU_RESET. Figure 1-13 and Table 1-21 describe the pushbutton switches.
X-Ref Target - Figure 1-13

VCC1V8

Pushbutton 1 CPU_RESET 2
P1 P4

4 3

P2

P3

SW9 1 2 R188
4.7K 5% 1/16W

UG518_25_070809

Figure 1-13: Table 1-21:

User Pushbutton Switch (Typical)

Pushbutton Switch Connections

Schematic Net Name GPIO_BUTTON_0 GPIO_BUTTON_1 GPIO_BUTTON_2 GPIO_BUTTON_3 CPU_RESET Switch Pin SW6.2 SW4.2 SW5.2 SW7.2 SW9.2

FPGA U1 Pin P4 F6 E4 F5 N4

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GPIO Male Pin Header

The SP601 provides a 2X6 GPIO male pin header supporting 3.3V power, GND and eight I/Os which support LVCMOS25 signaling. Figure 1-14 and Table 1-22 describe the J13 GPIO Male Pin Header. Note: I/Os connected to J13 are powered by 2.5V.
X-Ref Target - Figure 1-14

2 R98 200 5% 1/16W 1 2

R100 200 5% 1/16W

R99 200 5% 1/16W

R102 200 5% 1/16W 2 1 R103 200 5% 1/16W 2 1

GPIO HDR0 GPIO HDR1 GPIO HDR2 GPIO HDR3

GPIO HDR4 GPIO HDR5 GPIO HDR6 GPIO HDR7

1 3 5 7 9 11

2 4 6 8 10 12

J13

VCC3V3
UG518_24_091009

Figure 1-14: Table 1-22:

GPIO Male Pin Header Topology

GPIO Header Pins

Signal Name GPIO_HDR0 GPIO_HDR1 GPIO_HDR2 GPIO_HDR3 GPIO_HDR4 GPIO_HDR5 GPIO_HDR6 GPIO_HDR7 J13 Pin 1 3 5 7 2 4 6 8

FPGA U1 Pin N17 M18 A3 L15 F15 B4 F13 P12

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R97 200 5% 2 1/16W 1 R96 200 5% 1/16W 2 1

2 2

1 1

R101 200 5% 1/16W

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14. FPGA_PROG_B Pushbutton Switch

The SP601 provides one dedicated, active low FPGA_PROG_B pushbutton switch, as shown in Figure 1-15.
X-Ref Target - Figure 1-15

VCC2V5

1 2

R24 4.7K 5% 1/16W

Pushbutton
FPGA PROG B

1 2

P1 P2

P4

4 3

P3

SW3

UG518_28_041210

Figure 1-15: Table 1-23:

FPGA_PROG_B Pushbutton Switch Topology

FPGA_PROG_B Pushbutton Switch Connections

Schematic Net Name FPGA_PROG_B SW3 Pin 1

FPGA U1 Pin V2

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15. Configuration Options

The FPGA on the SP601 Evaluation Board can be configured by the following methods: 3. SPI x4 Flash, page 15 4. Linear Flash BPI, page 17 JTAG Configuration, page 36

For more information, refer to the Spartan-6 FPGA Configuration User Guide. [Ref 2] Table 1-24: Mode Pin Settings (M2 = 0)
Configuration Mode Master Byte Peripheral Interface (BPI) Master SPI x1, x2, or x4 Not implemented on SP601 Not implemented on SP601

Mode Pins (M1, M0) 00 01 10 11

JTAG Configuration
JTAG configuration is provided through onboard USB-to-JTAG configuration logic where a computer host accesses the SP601 JTAG chain through a Type-A (computer host side) to Type-Mini-B (SP601 side) USB cable. The JTAG chain of the board is illustrated in Figure 1-16. JTAG configuration is allowable at any time under any mode pin setting. JTAG initiated configuration takes priority over the mode pin settings. FMC bypass jumper J4 must be connected between pins 1-2 for JTAG access to the FPGA on the basic SP601 board, as shown in Figure 1-16. When the VITA 57.1 FMC expansion connector is populated with an expansion module that has a JTAG chain, then jumper J4 must be set to connect pins 2-3 in order to include the FMC expansion module's JTAG chain in the main SP601 JTAG chain.
X-Ref Target - Figure 1-16

J10 USB Mini-B Connector TDI

FPGA FMC LPC Expansion TDO U1 TDI J1 J4

1

TDO

*Default jumper setting excludes FMC. To include FMC, jumper pins 2-3.
UG518_31_070809

Figure 1-16:

JTAG Chain

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X-Ref Target - Figure 1-17

J4 1 Bypass FMC LPC J1 = Jumper 12 2 Include FMC LPC J1 = Jumper 23 H - 1x3 3 JTAG_TD0 FMC_TD0
UG518_32_040910

FPGA_TD0

Figure 1-17:

VITA 57.1 FMC JTAG Bypass Jumper

The JTAG chain can be used to program the FPGA and access the FPGA for hardware and software debug. The JTAG connector (USB Mini-B J10) allows a host computer to download bitstreams to the FPGA using the iMPACT software tool, and also allows debug tools such as the ChipScope Pro Analyzer tool or a software debugger to access the FPGA. The iMPACT software tool can also program the SPI x4 flash or the BPI flash via the USB J10 connection. iMPACT can download a temporary design to the FPGA through the JTAG. This provides a connection within the FPGA from the FPGA's JTAG port to the FPGA's SPI or BPI interface. Through the connection made by the temporary design in the FPGA, iMPACT can indirectly program the SPI flash or BPI flash from the JTAG USB J10 connector.

16. Power Management

AC Adapter and 5V Input Power Jack/Switch
The SP601 is powered from a 5V source that is connected through a 2.1 mm x 5.5 mm type plug (center positive). SP601 power can be turned on or off through a board mounted slide switch. When the switch is in the on position, a green LED (DS15) is illuminated.

Onboard Power Supplies

The diagram in Figure 1-18 shows the power supply architecture and maximum current handling on each supply. The typical operating currents are significantly below the maximum capable. The board is normally shipped with a 15W power supply, which should be sufficient for most applications. The SP601 uses power solutions from Linear Technology Corporation (LTC).

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Power System Test Points

The SP601 has 17 Keystone 5002 miniature PC test points, TP1 to TP17. These test points are identified in the SP601 board schematic, and the function of each is listed in Table 1-25. Table 1-25:
REFDES TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 5.0V Input Voltage GND 2.5V VCCO and Logic 3.3V FMC and Logic LTM4616 U15 ITH pin M8 for 2.5V regulator LTM4616 U15 ITH pin F8 for 3.3V regulator 1.2V VCCINT 1.8V DDR2 LTM4616 U19 ITH pin M8 for 1.2V regulator LTM4616 U19 ITH pin F8 for 1.8V regulator 0.9V VTT_DDR2 memory termination voltage 12V FMC 3.0V J3D U10 Flash GND GND GND GND

SP601 Power System Test Points

Function

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X-Ref Target - Figure 1-18

5V PWR Jack J18

DDR2 Memory Termination Linear Regulator U18 LTC3413 0.9V@3A max System, FMC Connector FPGA VCCAUX, VCCO FMC VADJ, System U19 FPGA DDR2 Memory VCCINT VCC1V8 VTT_DDR2 VCC3V3 VCC2V5

Dual Switcher LTM4616 3. 3V@8A max 2. 5V@8A max

U15

Dual Switcher LTM4616 1. 2V@8A max 1. 8V@8A max

Linear Regulator LT1763 3. 0V@500mA max

U11

SPI x4 Memory BPI Memory FMC Connector

VCC3V0

Buck-Boost Regulator LT1731 12V@1A max U8

VCC12VP

UG518_03_060210

Figure 1-18: Table 1-26: Onboard Power System Devices

Reference Designator U19 U19 U15 U15 U18 U11 U8 Description 1/2 Dual 8A Switching uModule 1/2 Dual 8A Switching uModule 1/2 Dual 8A Switching uModule 1/2 Dual 8A Switching uModule 3A Memory Term. Switching Regulator 500 mA LDO Linear Regulator 3A Switching Regulator

Power Supply

Device Type LTM4616IV#PBF LTM4616IV#PBF LTM4616IV#PBF LTM4616IV#PBF LTC3413EFE#PBF LTC1763CS8#TRPBF LT1371CR#TRPBF

Notes:

Power Rail Net Name VCCINT (1) VCC1V8 VCC2V5 VCC3V3 VTT_DDR2 VCC3V0 VCC12V_P

Power Rail Voltage (V) 1.20 1.80 2.50 3.30 0.9 3.0 12

Schematic Page 12 12 11 11 13 13 13

1. VCCINT tolerance meets or exceeds the VCCINT 5% specification in the Recommended Operating Conditions table in the Spartan-6 FPGA Data Sheet. [Ref 1]

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Appendix A

Default Jumper and Switch Settings

Table A-1 shows the default jumper and switch settings for the SP601. Table A-1: Default Jumper and Switch Settings
Type/Function SLIDE, POWER ON-OFF DIP, 2-POLE, MODE M0 M1 DIP, 4-POLE, GPIO OFF OFF OFF OFF HDR_1X3, JTAG BYPASS HDR_1X2, SUSPEND HDR_1X2, SPI SELECT JUMP 1-2 (EXCLUDE FMC) OPEN (0 = AWAKE) ON (U17 SPI MEM SELECTED) ON (1) OFF (0) Default OFF

REFDES SW1 SW2 1 2 SW8 1 2 3 4 J4 J14 J15

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Appendix A: Default Jumper and Switch Settings

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Appendix B

VITA 57.1 FMC LPC Connector Pinout

Figure B-1 shows the pinout of the FMC LPC connector. Pins marked NC are not connected.
X-Ref Target - Figure B-1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

K NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

J NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

H VR EF _A_M2C PR SNT_M2C_L GND CLK0_M2C _P CLK0_M2C _N GND LA02_P LA02_N GND LA04_P LA04_N G ND LA07_P LA07_N G ND LA11_P LA11_N G ND LA15_P LA15_N G ND LA19_P LA19_N G ND LA21_P LA21_N G ND LA24_P LA24_N G ND LA28_P LA28_N G ND LA30_P LA30_N G ND LA32_P LA32_N G ND V ADJ

G GND C LK 1_M2C_P C LK 1_M2C_N GND GND LA00_P _C C LA00_N_C C GND LA03_P LA03_N GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND VADJ G ND

F NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

E D NC P G_C2M NC G ND NC G ND NC G BT CLK0_M2C _P NC G BT CLK0_M2C _N NC G ND NC G ND NC LA01_P _C C NC LA01_N_C C NC GND NC LA05_P NC LA05_N NC GND NC LA09_P NC LA09_N NC GND NC LA13_P NC LA13_N NC GND NC LA17_P _C C NC LA17_N_C C NC GND NC LA23_P NC LA23_N NC GND NC LA26_P NC LA26_N NC GND NC T CK NC TDI NC TDO NC 3P3VAUX NC TMS NC TR ST _L NC G A1 NC 3P 3V NC GND NC 3P3V NC GND NC 3P 3V

C G ND DP 0_C2M_P DP 0_C2M_N GND GND DP 0_M2C_P DP 0_M2C_N G ND G ND LA06_P LA06_N GND G ND LA10_P LA10_N G ND GND LA14_P LA14_N G ND G ND LA18_P _C C LA18_N_C C GND G ND LA27_P LA27_N G ND GND S CL S DA GND G ND GA0 12P0V GND 12P0V G ND 3P3V GND

B NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

A NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

Figure B-1:

FMC LPC Connector Pinout

For more information, refer to the VITA 57.1 FMC LPC Connections table (Table 1-14).

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Appendix C

SP601 Master UCF

The UCF template is provided for designs that target the SP601. Net names provided in the constraints below correlate with net names on the SP601 schematic. On identifying the appropriate pins, the net names below should be replaced with net names in the user RTL. See the Constraints Guide for more information. The latest version of the UCF can be found on the SP601 board documentation website at http://www.xilinx.com/sp601.
NET ## NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "CPU_RESET" "DDR2_A0" "DDR2_A1" "DDR2_A2" "DDR2_A3" "DDR2_A4" "DDR2_A5" "DDR2_A6" "DDR2_A7" "DDR2_A8" "DDR2_A9" "DDR2_A10" "DDR2_A11" "DDR2_A12" "DDR2_BA0" "DDR2_BA1" "DDR2_BA2" "DDR2_CAS_B" "DDR2_CKE" "DDR2_CLK_N" "DDR2_CLK_P" "DDR2_DQ0" "DDR2_DQ1" "DDR2_DQ2" "DDR2_DQ3" "DDR2_DQ4" "DDR2_DQ5" "DDR2_DQ6" "DDR2_DQ7" "DDR2_DQ8" "DDR2_DQ9" "DDR2_DQ10" "DDR2_DQ11" "DDR2_DQ12" "DDR2_DQ13" "DDR2_DQ14" "DDR2_DQ15" "DDR2_LDM" "DDR2_LDQS_N" "DDR2_LDQS_P" LOC = "N4"; ## 2 on SW9 pushbutton LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = "J7"; "J6"; "H5"; "L7"; "F3"; "H4"; "H3"; "H6"; "D2"; "D1"; "F4"; "D3"; "G6"; "F2"; "F1"; "E1"; "K5"; "H7"; "G1"; "G3"; "L2"; "L1"; "K2"; "K1"; "H2"; "H1"; "J3"; "J1"; "M3"; "M1"; "N2"; "N1"; "T2"; "T1"; "U2"; "U1"; "K3"; "L3"; "L4"; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 L2 L3 L1 L7 K2 K8 J8 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 F3 E8 F7 on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2 U2

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Appendix C: SP601 Master UCF

NET NET NET NET NET NET ## NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET ## NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET

"DDR2_ODT" "DDR2_RAS_B" "DDR2_UDM" "DDR2_UDQS_N" "DDR2_UDQS_P" "DDR2_WE_B" "FLASH_A0" "FLASH_A1" "FLASH_A2" "FLASH_A3" "FLASH_A4" "FLASH_A5" "FLASH_A6" "FLASH_A7" "FLASH_A8" "FLASH_A9" "FLASH_A10" "FLASH_A11" "FLASH_A12" "FLASH_A13" "FLASH_A14" "FLASH_A15" "FLASH_A16" "FLASH_A17" "FLASH_A18" "FLASH_A19" "FLASH_A20" "FLASH_A21" "FLASH_A22" "FLASH_A23" "FLASH_A24" "FLASH_CE_B" "FLASH_D3" "FLASH_D4" "FLASH_D5" "FLASH_D6" "FLASH_D7" "FLASH_OE_B" "FLASH_WE_B" "FMC_CLK0_M2C_N" "FMC_CLK0_M2C_P" "FMC_CLK1_M2C_N" "FMC_CLK1_M2C_P" "FMC_LA00_CC_N" "FMC_LA00_CC_P" "FMC_LA01_CC_N" "FMC_LA01_CC_P" "FMC_LA02_N" "FMC_LA02_P" "FMC_LA03_N" "FMC_LA03_P" "FMC_LA04_N" "FMC_LA04_P" "FMC_LA05_N" "FMC_LA05_P" "FMC_LA06_N" "FMC_LA06_P" "FMC_LA07_N" "FMC_LA07_P" "FMC_LA08_N" "FMC_LA08_P" "FMC_LA09_N" "FMC_LA09_P"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

"K6"; "L5"; "K4"; "P1"; "P2"; "E3"; "K18"; "K17"; "J18"; "J16"; "G18"; "G16"; "H16"; "H15"; "H14"; "H13"; "F18"; "F17"; "K13"; "K12"; "E18"; "E16"; "G13"; "H12"; "D18"; "D17"; "G14"; "F14"; "C18"; "C17"; "F16"; "L17"; "U5"; "V5"; "R3"; "T3"; "R5"; "L18"; "M16"; "A10"; "C10"; "V9"; "T9"; "C9"; "D9"; "C11"; "D11"; "A15"; "C15"; "A13"; "C13"; "A16"; "B16"; "A14"; "B14"; "C12"; "D12"; "E8"; "E7"; "E11"; "F11"; "F10"; "G11";

| | | | | |

IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## 32 28 27 26 25 24 23 22 20 19 18 17 13 12 11 10 8 7 6 5 4 3 1 30 56 14 40 44 46 49 51 54 55 on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on on U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10 U10

= = = = = =

SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II SSTL18_II

; ; ; ; ; ;

## ## ## ## ## ##

K9 K7 B3 A8 B7 K3

on on on on on on

U2 U2 U2 U2 U2 U2

H5 on J1 H4 on J1 G3 on J1 G2 on J1 G7 on J1 G6 on J1 D9 on J1 D8 on J1 H8 on J1 H7 on J1 G10 on J1 G9 on J1 H11 on J1 H10 on J1 D12 on J1 D11 on J1 C11 on J1 C10 on J1 H14 on J1 H13 on J1 G13 on J1 G12 on J1 D15 on J1 D14 on J1

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NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET ## NET NET NET NET NET NET NET NET NET NET NET NET NET NET

"FMC_LA10_N" "FMC_LA10_P" "FMC_LA11_N" "FMC_LA11_P" "FMC_LA12_N" "FMC_LA12_P" "FMC_LA13_N" "FMC_LA13_P" "FMC_LA14_N" "FMC_LA14_P" "FMC_LA15_N" "FMC_LA15_P" "FMC_LA16_N" "FMC_LA16_P" "FMC_LA17_CC_N" "FMC_LA17_CC_P" "FMC_LA18_CC_N" "FMC_LA18_CC_P" "FMC_LA19_N" "FMC_LA19_P" "FMC_LA20_N" "FMC_LA20_P" "FMC_LA21_N" "FMC_LA21_P" "FMC_LA22_N" "FMC_LA22_P" "FMC_LA23_N" "FMC_LA23_P" "FMC_LA24_N" "FMC_LA24_P" "FMC_LA25_N" "FMC_LA25_P" "FMC_LA26_N" "FMC_LA26_P" "FMC_LA27_N" "FMC_LA27_P" "FMC_LA28_N" "FMC_LA28_P" "FMC_LA29_N" "FMC_LA29_P" "FMC_LA30_N" "FMC_LA30_P" "FMC_LA31_N" "FMC_LA31_P" "FMC_LA32_N" "FMC_LA32_P" "FMC_LA33_N" "FMC_LA33_P" "FMC_PRSNT_M2C_L" "FMC_PWR_GOOD_FLASH_RST_B" "FPGA_AWAKE" "FPGA_CCLK" "FPGA_CMP_CLK" "FPGA_CMP_CS_B" "FPGA_CMP_MOSI" "FPGA_D0_DIN_MISO_MISO1" "FPGA_D1_MISO2" "FPGA_D2_MISO3" "FPGA_DONE" "FPGA_HSWAPEN" "FPGA_INIT_B" "FPGA_M0_CMP_MISO" "FPGA_M1" "FPGA_MOSI_CSI_B_MISO0"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

"C8"; "D8"; "A12"; "B12"; "C6"; "D6"; "A11"; "B11"; "A2"; "B2"; "F9"; "G9"; "A7"; "C7"; "T8"; "R8"; "T10"; "R10"; "P7"; "N6"; "P8"; "N7"; "V4"; "T4"; "T7"; "R7"; "P6"; "N5"; "V8"; "U8"; "N11"; "M11"; "V7"; "U7"; "T11"; "R11"; "V11"; "U11"; "N8"; "M8"; "V12"; "T12"; "V6"; "T6"; "V15"; "U15"; "N9"; "M10"; "U13"; "B3";

## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##

C15 on J1 C14 on J1 H17 on J1 H16 on J1 G16 on J1 G15 on J1 D18 on J1 D17 on J1 C19 on J1 C18 on J1 H20 on J1 H19 on J1 G19 on J1 G18 on J1 D21 on J1 D20 on J1 C23 on J1 C22 on J1 H23 on J1 H22 on J1 G22 on J1 G21 on J1 H26 on J1 H25 on J1 G25 on J1 G24 on J1 D24 on J1 D23 on J1 H29 on J1 H28 on J1 G28 on J1 G27 on J1 D27 on J1 D26 on J1 C27 on J1 C26 on J1 H32 on J1 H31 on J1 G31 on J1 G30 on J1 H35 on J1 H34 on J1 G34 on J1 G33 on J1 H38 on J1 H37 on J1 G37 on J1 G36 on J1 H2 on J1 D1 on J1, 16 on U10

LOC = "P15"; ## 2 on DS8 LED LOC = "R15"; ## 16 on U17, 7 on J12 LOC = "U16"; ## 3 on J3 LOC = "P13"; ## 4 on J3 LOC = "V16"; ## 2 on J3 LOC = "R13"; ## 8 on U17 (thru series R187 100 ohm), 33 on U10, 6 on J12 LOC = "T14"; ## 9 on U17 (thru series R186 100 ohm), 35 on U10, 3 on J12 LOC = "V14"; ## 1 on U17, 38 on U10, 2 on J12 LOC = "V17"; ## 2 on DS9 LED LOC = "D4"; ## 1 on R81 100 ohm to GND LOC = "U3"; ## 1 on DS10 (thru series R90 27.4 ohm) LOC = "T15"; ## 1 on J3, 1 on SW2 DIP Sw LOC = "N12"; ## 2 on SW2 DIP Sw LOC = "T13"; ## 15 on U17, 5 on J12

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NET NET NET NET NET NET NET NET NET ## NET NET NET NET ## NET NET NET NET NET NET NET NET ## NET NET NET NET ## NET NET NET NET ## NET NET ## NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET

"FPGA_ONCHIP_TERM1" "FPGA_ONCHIP_TERM2" "FPGA_PROG_B" "FPGA_SUSPEND" "FPGA_TCK_BUF" "FPGA_TDI_BUF" "FPGA_TDO" "FPGA_TMS_BUF" "FPGA_VTEMP" "GPIO_BUTTON0" "GPIO_BUTTON1" "GPIO_BUTTON2" "GPIO_BUTTON3" "GPIO_HDR0" "GPIO_HDR1" "GPIO_HDR2" "GPIO_HDR3" "GPIO_HDR4" "GPIO_HDR5" "GPIO_HDR6" "GPIO_HDR7" "GPIO_LED_0" "GPIO_LED_1" "GPIO_LED_2" "GPIO_LED_3" "GPIO_SWITCH_0" "GPIO_SWITCH_1" "GPIO_SWITCH_2" "GPIO_SWITCH_3" "IIC_SCL_MAIN" "IIC_SDA_MAIN" "PHY_COL" "PHY_CRS" "PHY_INT" "PHY_MDC" "PHY_MDIO" "PHY_RESET" "PHY_RXCLK" "PHY_RXCTL_RXDV" "PHY_RXD0" "PHY_RXD1" "PHY_RXD2" "PHY_RXD3" "PHY_RXD4" "PHY_RXD5" "PHY_RXD6" "PHY_RXD7" "PHY_RXER" "PHY_TXCLK" "PHY_TXCTL_TXEN" "PHY_TXC_GTXCLK" "PHY_TXD0" "PHY_TXD1" "PHY_TXD2" "PHY_TXD3" "PHY_TXD4" "PHY_TXD5" "PHY_TXD6" "PHY_TXD7"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = =

"L6"; "C2"; "V2"; "R16"; "A17"; "D15"; "D16"; "B18"; "P3"; "P4"; "F6"; "E4"; "F5"; "N17"; "M18"; "A3"; "L15"; "F15"; "B4"; "F13"; "P12"; "E13"; "C14"; "C4"; "A4"; "D14"; "E12"; "F12"; "V13";

## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##

ZIO no connect (R86 is DNP) RZQ 100 ohm to GND 1 on SW3 pushbutton 2 on J14 14 on U21, D29 on J1 18 on U21 1 on J4, D30 on J1 16 on U21, D31 on J1 2 on R87 150 ohm p/u to VCC1V8 2 2 2 2 1 3 5 7 2 4 6 8 2 2 2 2 1 2 3 4 on on on on on on on on on on on on on on on on on on on on SW6 SW4 SW5 SW7 J13 J13 J13 J13 J13 J13 J13 J13 DS11 DS12 DS13 DS14 SW8 SW8 SW8 SW8 pushbutton pushbutton pushbutton pushbutton (thru (thru (thru (thru (thru (thru (thru (thru LED LED LED LED DIP DIP DIP DIP Sw Sw Sw Sw series series series series series series series series R100 200 ohm) R102 200 ohm) R101 200 ohm) R103 200 ohm) R99 200 ohm) R98 200 ohm) R97 200 ohm) R96 200 ohm)

LOC = "P11"; ## 6 on U7 (thru series R203 0 ohm), C30 on J1, 2 on J16 LOC = "N10"; ## 5 on U7 (thru series R204 0 ohm), C31 on J1, 1 on J16 LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = = = = = = = = = = = = = = = = = = "L14"; "M13"; "J13"; "N14"; "P16"; "L13"; "L16"; "N18"; "M14"; "U18"; "U17"; "T18"; "T17"; "N16"; "N15"; "P18"; "P17"; "B9"; "B8"; "A9"; "F8"; "G8"; "A6"; "B6"; "E6"; "F7"; "A5"; "C5"; ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## 114 on U3 115 on U3 32 on U3 35 on U3 33 on U3 36 on U3 7 on U3 4 on U3 3 on U3 128 on U3 126 on U3 125 on U3 124 on U3 123 on U3 121 on U3 120 on U3 8 on U3 10 on U3 16 on U3 14 on U3 18 on U3 19 on U3 20 on U3 24 on U3 25 on U3 26 on U3 28 on U3 29 on U3

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NET ## NET NET ## NET ## NET NET ## NET NET NET NET ## NET

"PHY_TXER" "SMACLK_N" "SMACLK_P" "SPI_CS_B" "SYSCLK_N" "SYSCLK_P" "USB_1_CTS" "USB_1_RTS" "USB_1_RX" "USB_1_TX" "USER_CLOCK"

LOC = "A8";

## 13 on U3

LOC = "H18"; ## 1 on J8 SMA LOC = "H17"; ## 1 on J7 SMA LOC = "V3"; ## 1 on J15, 4 on J12

LOC = "K16"; ## 5 on U5 EG2121CA, 5 of U20 SI500D (DNP) LOC = "K15"; ## 6 on U5 EG2121CA, 4 of U20 SI500D (DNP) LOC LOC LOC LOC = = = = "U10"; "T5"; "L12"; "K14"; ## ## ## ## 22 23 24 25 on on on on U4 U4 U4 U4

LOC = "V10"; ## 5 on X2 USER OSC Socket

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Appendix C: SP601 Master UCF

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Appendix D

References
This section provides references to documentation supporting Spartan-6 FPGAs, tools, and IP. For additional information, see www.xilinx.com/support/documentation/index.htm. Documents supporting the SP601 Evaluation Board:
1. 2. 3. 4. 5. 6. 7. 8. 9. DS162, Spartan-6 FPGA Data Sheet: DC and Switching Characteristics UG380, Spartan-6 FPGA Configuration User Guide UG388, Spartan-6 FPGA Memory Controller User Guide DS570, XPS Serial Peripheral Interface (SPI) Data Sheet UG138, LogiCORE IP Tri-Mode Ethernet MAC v4.2 User Guide DS606, XPS IIC Bus Interface (v2.00a) Data Sheet UG381, Spartan-6 FPGA SelectIO Resources User Guide DS614, Clock Generator (v3.01a) Data Sheet DS643, Multi-Port Memory Controller (MPMC) (v5.02a) Data Sheet

10. UG394, Spartan-6 FPGA Power Management User Guide

Additional documentation:
11. Elpida, DDR2 SDRAM Specifications (EDE1116ACBG) 12. Winbond, Serial Flash Memory Data Sheet (W25Q64VSFIG) 13. Numonyx, Embedded Flash Memory Data Sheet (TE28F128J3D-75) 14. SiTime, Oscillator Data Sheet (SiT9102AI-243N25E200.00000) 15. PCI SIG, PCI Express Specifications 16. Marvell, Alaska Gigabit Ethernet Transceivers Product Page 17. ST Micro, M24C08 Data Sheet

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Appendix D: References

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