Digital Electronics
Flip-Flops
Objectives
Draw the symbol for the D-Latch and D Flip Flop.
Given a D flip flop and input waveforms, draw the
output waveform for Q. Given a J-K flip flop and input waveforms, draw the output waveform for Q. Define Asynchronous and Synchronous.
Given a J-K flip flop, identify the synchronous
and asynchronous inputs.
FLIP-FLOP TYPES
S CLK R Q Q
RS FLIP FLOP (Reset/Set) a.k.a. Set/Clear Most basic flip flop can be made by cross coupling NAND or NOR gates Activating Set and Reset is invalid
D CLK
Q Q
D Flip Flop (Data or Delay) Has only a single data input and clock input Input transfers to output on clock pulse T Flip Flop (Toggle) Output toggles on each clock pulse Q output divides clock frequency in half J-K Flip Flop Universal, can make all other flip flops Has no prohibited states
Q T Q
J CLK K
Q Q
POSITIVE LEVEL TRIGGERED Symbol: D FLIP-FLOP
D
D
CLK
Q Q
Q NOT
EN
Truth Table:
EN 0 1 1 D X 0 1 Q* No change 0 1
*Q follows D input while EN is HIGH
POSITIVE LEVEL TRIGGERED D FLIP-FLOP
TIMING DIAGRAMS
D EN Q Q
C D Q
EN 0 1 1
D X 0 1
Q* No change 0 1
C D Q C D Q
*Q follows D input while EN is HIGH
POSITIVE EDGE TRIGGERED D FLIP-FLOP
TIMING DIAGRAMS
D CLK Q Q
C D Q
CLK
D X 0 1
Q* No change 0 1
C D Q C D Q
*Q follows D input when CLK is HIGH
NEGATIVE EDGE TRIGGERED T FLIP-FLOP Symbol:
D Q
Q T Q
CLK Q
Output toggles on each clock pulse Q output divides clock frequency in half Usually made with JK Flip Flop
Truth Table:
CLK Q QO Q= QO MEANS THAT THE NEW VALUE OF Q WILL BE THE INVERSE OF THE VALUE IT HAD PRIOR TO THE NGT
NEGATIVE EDGE TRIGGERED T FLIP-FLOP
Timing Diagrams
Q T Q
T Q
CLK
Q QO
T Q
Q= QO
MEANS THAT THE NEW VALUE OF Q WILL BE THE INVERSE OF THE VALUE IT HAD PRIOR TO THE NGT
J-K FLIP-FLOP
UNIVERSAL Flip Flop can make all others from JK (T, D and RS)
J CLK K
Q Q
The J input acts like SET, K acts like RESET No illegal state, activating both inputs causes Q to TOGGLE
J-K FLIP-FLOP
J CLOCK
Symbol:
Q NOT
J CLK K
Q Q
Truth Table:
CLK 0 1 J X X X 0 0 1 1 K X X X 0 1 0 1 Q NO CHG NO CHG NO CHG NO CHG 0 1 QO MODE HOLD HOLD HOLD HOLD RESET SET TOGGLE
NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP
Timing Diagrams
J CLK K
CLK J 0 0 1 1
Q Q
C J K Q
K Q 0 NO CHG 1 0 1 0 1 QO
C J K Q
POSITIVE EDGE TRIGGERED J-K FLIP-FLOP
Timing Diagrams
J CLK K
CLK J 0 0 1 1
Q Q
C J K
K Q 0 NO CHG 1 0 1 0 1 QO
C J K Q
C J K Q
ASYNCHRONOUS OVERRIDES
Asynchronous Inputs a.k.a. Overide Inputs operate independent of the control and clock inputs
PRE
J CLK K Q Q
PRE
PRESET Active-low override Q=1 overrides all other inputs
CLR
CLR
CLEAR Active-low override Q=0 overrides all other inputs
J-K FLIP-FLOP ASYNCHRONOUS OVERRIDES
PRE
J CLK K Q Q
CLR
PRE 1 1 0 0
CLR 1 0 1 0
Q* No effect; FF can respond to J, K, and CLK Q=0 independent of synchronous inputs Q=1 independent of synchronous inputs Ambiguous (not used)
*CLK can be in any state
J-K FLIP-FLOP
Symbol:
J
Clk
Q __ Q
Truth Table:
Mode of Operation PS Asynchronous set 0 Inputs Clr Clk 1 x J x K x Outputs Q Q 1 0
Asynchronous reset 1 0 x x x 0 1 Prohibited 0 0 x x x 1 1 ------------------------------------------------------------------------Hold 1 1 0 0 no change Reset 1 1 0 1 0 1 Set 1 1 1 0 1 0 Toggle 1 1 1 1 opposite
x = Irrelevant = H-to-L transition of clock pulse
J-K FLIP-FLOP ASYNCHRONOUS OVERRIDES
Timing Diagrams
PRE
J CLK K Q Q
CLOCK PRESET CLEAR J K Q
CLR
PRE 1 1 0 0
CLR 1 0 1 0
Q No effect Q=0 Q=1 Illegal
TEST
Data Delay 1. The D in D flip flop stands for _________ or _________ .
D 2. With a D flip flop, Q follows _____ when triggered by the clock.
3. The J input on a J-K flip flop acts like what input on an RS Latch?
Set
4. The K input on a J-K flip flop acts like what input on an RS Latch?
Reset
5. What inputs on a J-K flip flop are the Asynchronous inputs?
Preset/Set
J&K
Clear/Reset
6. What inputs on a J-K flip flop are the Synchronous inputs?
