ADVANCED MICROPROCESSORS Pin Function of 8088 and 8086

Contents
Pin Diagram of 8086 Pin Details Pin Diagram of 8088 Comparison of 8086 and 8088

8086 Pin diagram

8086 is a 40 pin DIP using MOS technology. It has 2 GNDs as circuit complexity demands a large amount of current flowing through the circuits, and multiple grounds help in dissipating the accumulated heat etc. 8086 works on two modes of operation namely, Maximum Mode and Minimum Mode.

Power Connections
GND 1 40 VCC

8086
CLK GND 19 20

Pin Description: GND Pin no. 1, 20 Ground CLK Pin no. 19 Type I Clock: provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty cycle to provide optimized internal timing. VCC Pin no. 40 VCC: +5V power supply pin

Address/ Data Lines

AD14 AD13 AD12 AD11 AD10 AD9 2 3 39 AD15

4
5 6 7 8

AD8
AD7 AD6 AD5 AD4

8086

9 10
11 12

AD3
AD2 AD1 AD0

13
14 15 16

Continued

Pin Description
AD15-AD0 Pin no. 2-16, 39 Type I/O
Address Data bus: These lines constitute the time multiplexed memory/ IO address (T1) and data (T2, Tw, T3, T4) bus. A0 is analogous to BHE* for the lower byte of the data bus, pins D7D0. It is low when a byte is to be transferred on the lower portion of the bus in memory or I/O operations. Eight bit oriented devices tied to the lower half would normally use A0 to condition chip select functions. These lines are active HIGH and float to 3state OFF during interrupt acknowledge and local bus hold acknowledge.

Address Lines
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 2 3 4 39 38 37 A15
A 16
A 17

5
6 7 8 9 10 11 12 13 14 15 16

8086

36
35

A 18 A 19

A3
A2 A1 A0

Continued

A19/S6, A18/S5, A17/S4, A16/S3 Pin no. 35-38 Type O Address / Status: During T1 these are the four most significant address lines for memory operations. During I/O operations these lines are low. During memory and I/O operations, status information is available on these lines during T2, Tw, T3 and T4. The status of the interrupt enable FLAG bit (S5) is updated at the beginning of each CLK cycle. A17/S4 and A16/S3 are encoded as shown.
Continued

A17/S4 0 (LOW) 0 1(HIGH) 1

A16/S3 0 1 0 1

Characteristics Alternate Data Stack Code or None Data

S6 is 0 (LOW)
This information indicates which relocation register is presently being used for data accessing. These lines float to 3-state OFF during local bus hold acknowledge.

Status Pins S0-S7

38 S3

37
36 35

S4
S5 S6 S7
S2 S1

8086

34 28 27 26

(M/I O )
(DT / R )

S 0 ( DEN)

Continued

Pin Description
S 2 , S1 , S 0

- Pin no. 26, 27, 28 Type O

Status: active during T4, T1 and T2 and is returned to the passive state (1,1,1) during T3 or during TW when READY is HIGH. This status is used by the 8288 Bus Controller to generate all memory and I/O access control signals. Any change by , or during T4 is used to indicate the beginning of a bus cycle and the return to the passive state in T3 or TW is used to indicate the end of a bus cycle.

Continued

These signals float to 3-state OFF in hold acknowledge. These status lines are encoded as shown. S2* S1* S0* Characteristics 0(LOW) 0 0 Interrupt acknowledge 0 0 1 Read I/O Port 0 1 0 Write I/O Port 0 1 1 Halt 1(HIGH) 0 0 Code Access 1 0 1 Read Memory 1 1 0 Write Memory 1 1 1 Passive

Continued

Status Details
S2
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1
S1
S 0 Indication

0 1 0 1 0 1 0 1

Interrupt Acknowledge Read I/O port Write I/O port Halt Code access Read memory Write memory Passive

Continued

S4
0 0 1

S3
0 1 0

Indications
Alternate data Stack Code or none

Data
Continued

S5
S6

----- Value of Interrupt Enable flag

----- Always low (logical) indicating 8086 is on the bus. If it is tristated another bus master has taken control of the system bus. ----- Used by 8087 numeric coprocessor to determine whether the CPU is a 8086 or 8088

S7

Interrupts
Pin Description: NMI Pin no. 17 Type I Non Maskable Interrupt: an edge triggered input which causes a type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally by software. A transition from a LOW to HIGH initiates the interrupt at the end of the current instruction. This input is internally synchronized.
Continued

8086
NMI 17

INTR

18

INTR Pin No. 18 Type I Interrupt Request: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.

Common Signals

Continued

Pin Description: RD* - Pin no. 34, Type O Read: Read strobe indicates that the processor is performing a memory of I/O read cycle, depending on the state of the S2 pin. This signal is used to read devices which reside on the 8086 local bus. RD* is active LOW during T2, T3 and TW of any read cycle, and is guaranteed to remain HIGH in T2 until the 8086 local bus has floated. This signal floats to 3-state OFF in hold acknowledge. READY Pin no. 22, Type I READY: is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. The READY signal from memory / IO is synchronized by the 8284A Clock Generator to form READY. This signal is active HIGH. The 8086 READY input is not synchronized. Correct operation is not guaranteed if the setup and hold times are not met.
Continued

Pin Description
HOLD, HLDA Pin no. 31, 30 Type I/O HOLD: indicates that another master is requesting a local bus hold. To be acknowledged, HOLD must be active HIGH. The processor receiving the hold request will issue HLDA (HIGH) as an acknowledgement in the middle of a T1 clock cycle. Simultaneous with the issuance of HLDA the processor will float the local bus and control lines. After HOLD is detected as being LOW, the processor will LOWer the HLDA, and when the processor needs to run another cycle, it will again drive the local bus and control lines. The same rules as apply regarding when the local bus will be released. HOLD is not an asynchronous input. External synchronization should be provided if the system can not otherwise guarantee the setup time. Continued

BHE*/S7- Pin No. 34 Type O Bus High Enable / Status: During T1 the Bus High Enable signal (BHE*) should be used to enable data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices tied to the upper half of the bus would normally use BHE* to condition chip select functions. BHE* is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus. The S,7 status information is available during T2, T3 and T4. The signal is active LOW and floats to 3-state OFF in hold. It is LOW during T1 for the first interrupt acknowledge cycle. BHE* 0 0 A0 0 1 Characteristics Whole word Upper byte from / to odd address

1
1

0
1

Lower byte from / to even address

None
Continued

MN/MX* - Pin no. 33 Type - I Minimum / Maximum: indicates what mode the processor is to operate in. If the local bus is idle when the request is made the two possible events will follow: Local bus will be released during the next clock. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied.

Min mode signals

33
31 VCC MN/ MX HOLD HLDA

30
29

WR
M/I O
DT/ R

8086

28 27 26 25 24

DEN
ALE
INTA

Continued

TEST* - Pin No 23 Type I TEST* : input is examined by the Wait instruction. If the TEST* input is LOW execution continues, otherwise the processor waits in an idle state. This input is synchronized internally during each clock cycle on the leading edge of CLK.
RESET Pin no. 21 Type I Reset: causes the processor to immediately terminate its present activity. The signal must be active HIGH for at least four clock cycles. It restarts execution, as described in the instruction set description, when RESET returns LOW. RESET is internally synchronized.
Continued

WR* - Pin no. 29 Type O Write: indicates that the processor is performing a write memory or write I/O cycle, depending on the state of the M/IO* signal. WR* is active for T2, T3 and TW of any write cycle. It is active LOW, and floats to 3-state OFF in local bus hold acknowledge.

M/IO* - Pin no. 28 type O Status line: logically equivalent to S2 in the maximum mode. It is used to distinguish a memory access from an I/O access. M/IO* becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle (M=HIGH), IO=LOW). M/IO* floats to 3-state OFF in local bus hold acknowledge.
Continued

DT/R* - Pin no. 27 Type O Data Transmit / Receive: needed in minimum system that desires to use an 8286/8287 data bus transceiver. It is used to control the direction of data flow through the transceiver. Logically DT/R* is equivalent to S1* in the maximum mode, and its timing is the same as for M/IO*. (T=HIGH, R=LOW). This signal floats to 3-state OFF in local bus hold acknowledge. DEN* - Pin no. 26 Type O Data Enable: provided as an output enable for the 8286/8287 in a minimum system which uses the transceiver. DEN* is active LOW during each memory and I/O access and for INTA cycles. For a read or INTA* cycle it is active from the middle of T2 until the middle of T4, while for a write cycle it is active from the beginning of T2 until the middle of T4. DEN* floats to 3-state OFF in local bus hold acknowledge. Continued

ALE Pin no. 25 Type O Address Latch Enable: provided by the processor to latch the address into the 8282/8283 address latch. It is a HIGH pulse active during T1 of any bus cycle. Note that ALE is never floated. INTA* - Pin no. 24 Type O INTA* is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3 and TW of each interrupt acknowledge cycle.

Max mode signals

33 31 30 29 GND
RQ/ GT0

RQ/ GT 1
LOCK
S2 S1 S0

8086

28 27

26
25 24

QS0 QS1

Continued

Pin Description: RQ*/GT0*, RQ*/GT1* - Pin no. 30, 31 Type I/O Request /Grant: pins are used by other local bus masters to force the processor to release the local bus at the end of the processors current bus cycle. Each pin is bidirectional with RQ*/GT0* having higher priority than RQ*/GT1*. RQ*/GT* has an internal pull up resistor so may be left unconnected. The request/grant sequence is as follows:
Continued

1. A pulse of 1 CLK wide from another local bus master indicates a local bus request (hold) to the 8086 (pulse 1) 2. During a T4 or T1 clock cycle, a pulse 1 CLK wide from the 8086 to the requesting master (pulse 2), indicates that the 8086 has allowed the local bus to float and that it will enter the hold acknowledge state at the next CLK. The CPUs bus interface unit is disconnected logically from the local bus during hold acknowledge. 3. A pulse 1 CLK wide from the requesting master indicates to the 8086 (pulse 3) that the hold request is about to end and that the 8086 can reclaim the local bus at the next CLK. Continued

Each master-master exchange of the local bus is a sequence of 3 pulses. There must be one dead CLK cycle after each bus exchange. Pulses are active LOW. If the request is made while the CPU is performing a memory cycle, it will release the local bus during T4 of the cycle when all the following conditions are met: Request occurs on or before T2. Current cycle is not the low byte of a word (on an odd address) Current cycle is not the first acknowledge of an interrupt acknowledge sequence. A locked instruction is not currently executing.
Continued

LOCK* - Pin no. 29 Type O LOCK* : output indicates that other system bus masters are not to gain control of the system bus while LOCK* is active LOW. The LOCK* signal is activated by the LOCK prefix instruction and remains active until the completion of the next instruction. This signal is active LOW, and floats to 3-state OFF in hold acknowledge. QS1, QS0 Pin no. 24, 25 Type O Queue Status: the queue status is valid during the CLK cycle after which the queue operation is performed. QS1 and QS0 provide status to allow external tracking of the internal 8086 instruction queue.
Continued

QS1

QS0

Characteristics

0(LOW)
0 1 (HIGH) 1

0
1 0 1

No operation
First Byte of Op Code from Queue Empty the Queue Subsequent byte from Queue

8088 Pin Diagram

Comparison of 8086 and 8088

1. In 8088 we have A15-8, instead of AD15-8 of 8086. this is because, the 8088 can communicate with the outside world using only 8 bits o data. However, the registers in 8088 and 8086 are same, and the instruction set is also the same. So, for word operations, the 8088 has to access information twice. Thus the execution time is increased in the case of 8088.
Continued

2. In 8086 pin 28 is assigned for the signal M/IO* in the minimum mode. But in 8088, this pin is assigned to the signal IO/M* in the minimum mode. This change has been done in 8088 so that the signal is compatible with 8085 bus structure. 3. The instruction queue length in the case of 8086 is 6 bytes. The BIU in 8088 needs more time to fill up the queue a byte at a time. Thus to prevent overuse of the bus by the BIU, the instruction queue in 8088 is shortened to 4 bytes. 4. To optimize the working of the queue, the 8086 BIU will fetch a word into the queue whenever there is a space for a word in the queue. The 8088 BIU will fetch a byte into the queue whenever there is space for a byte in the queue. Continued

5. Pin number 34 of 8086 is BHE*/S7. BHE* is irrelevant for 8088, which can only access 8 bits at a time. Thus pin 34 o 8088 is assigned for the signal SSO*. This pin acts like SO* status line in the minimum mode of operation. So, in the minimum mode, DT/R*, IO/M*, and SSO* provide the complete bus status as shown.

Continued

IO/M* 1 1 1 1 0 0 0 0

DT/R* SSO* 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

Bus Cycle Interrupt acknowledge Read I/O port Write I/O port Halt Code Access Read Memory Write Memory Passive
Continued

6. In the maximum mode for 8088 the SSO* (pin 34) signal is always a 1. In the maximum mode for 8086, the BHE*/S7 (pin 34) will provide BHE* information during the first clock cycle, and will be 0 during subsequent clock cycles. In maximum mode, 8087 will monitor this pin to identify the CPU as a 8088 or a 8086, and accordingly sets its own queue length to 4 or 6 bytes.

8288 Bus Controller

Separate signals are used for I/O ( IORC and IOWC ) and memory ( MRDC and MWTC ). Also provided are advanced memory ( AIOWC ) and I/O ( AIOWC ) write strobes plus INTA .

A8-A15

74LS244

10.5 The 8288 Bus Controller

CPU Address Bus (A16-A19, if needed, should be latched the same way like AD0-AD7) Data to be transferred in the current bus cycle
CPU Data Bus

G1 G2 8282 AD0-AD7
D Q LE

Identify the Memory Byte (one of 220 (216 in example)) OR the I/O port (one of 216) to be read OR write in the current bus cycle
Advanced Write Commands, providing additional access time for the selected circuit

STB OE 8088 8286

OE

S0 S1 S2 Status Signals (codify the bus cycle type) Address Latch Enable

Max one active at a time, identifying Memory vs. I/O Data Transmit/Receive T and Read vs. Write Memory ReaD Command DEN DT/R MRDC Memory WriTe Command ALE MWTC Input/Output Read Command S0 IORC Input/Output Write Command S1 8288 IOWC INTerrupt Acknowledge S2 INTA Advanced Memory Write Command AMWC Advanced Input/Output Write Command AIOWC 5V IOB AEN CEN Command Enable Control

Data Enable

CLK

I/O Bus only

Address Enable

Bus

System Timing Diagrams

T-State:
One clock period is referred to as a T-State

T-State

An operation takes an integer number of T-States

CPU Bus Cycle:

A bus cycle consists of 4 or more T-States

T1

T2

T3

T4

Memory Read Timing Diagrams

Dump address on address bus. Issue a read ( RD ) and set M/ IO to 1. Wait for memory access cycle.

Memory Read Timing Diagrams

T1
CLK ALE A[19:16] A[15:8] A[19:16] A[15:8] S3-S6

T2

T3

T4
A[15:8]
Buffer A[15:0]

8088
AD[7:0] D latch

AD[7:0] A[7:0]
IO/M DT/R DEN

D[7:0]
D[7:0] DT/R DEN IO/M Trans -ceiver

Memory

RD WR

WR RD

Memory Write Timing Diagrams

Dump address on address bus. Dump data on data bus. Issue a write ( WR ) and set M/ IO to 1.

Memory Write Timing Diagrams

T1
CLK ALE A[19:16] A[15:8] A[19:16] A[15:8] S3-S6

T2

T3

T4
A[15:8]
Buffer A[15:0]

8088
AD[7:0] D latch

AD[7:0] A[7:0]
IO/M DT/R DEN

D[7:0]
D[7:0] DT/R DEN IO/M Trans -ceiver

Memory

RD WR

WR RD

Bus Timing
During T 1 : The address is placed on the Address/Data bus. Control signals M/ IO , ALE and DT/ R specify memory or I/O, latch the address onto the address bus and set the direction of data transfer on data bus. During T 2 : 8086 issues the RD or WR signal, DEN , and, for a write, the data. DEN enables the memory or I/O device to receive the data for writes and the 8086 to receive the data for reads. During T 3 : This cycle is provided to allow memory to access data. READY is sampled at the end of T 2 . If low, T 3 becomes a wait state. Otherwise, the data bus is sampled at the end of T 3 . During T 4 : All bus signals are deactivated, in preparation for next bus cycle. Data is sampled for reads, writes occur for writes.

Bus Timing Diagram

Bus Timing
Timing: Each BUS CYCLE on the 8086 equals four system clocking periods (T states). The clock rate is 5MHz , therefore one Bus Cycle is 800ns . The transfer rate is 1.25MHz . Memory specs (memory access time) must match constraints of system timing.

For example, bus timing for a read operation shows almost 600ns are needed to read data. However, memory must access faster due to setup times, e.g. Address setup and data setup. This subtracts off about 150ns . Therefore, memory must access in at least 450ns minus another 30-40ns guard band for buffers and decoders. 420ns DRAM required for the 8086.

10.6 System Time Diagrams - CPU Bus Cycle

CLK ALE IO/M A16- A19 A16-A19 T1 T2 T3 TW T4

Address latches store the actual values

Memory Cycle (I/O cycle is similar but IO/M = 1) S3- S6

A8- A15

A8- A15
the P samples READY (if 0 a WAIT state follows) P reads Data Bus

READY The slow device drives READY= 0 RD AD0- AD7 A0- A7

Read Cycle (instruction fetch and memory operand read)

Tri-state

D0- D7 (Data in)

DT/R DEN
WR AD0- AD7 DT/R DEN A0- A7

Direction READ for the Data Buffer

Enables Data Buffer Memory reads Data Bus

Write Cycle (memory operand write) D0- D7 (Data out)

Direction READ for the Data Buffer Enables Data Buffer

Interrupt Acknowledge Timing Diagrams

T1 T2 T3 T4

CLK INTR INTA D[7:0]

8088 INTR External device

INTA
Int. Type

Data bus

It takes one bus cycle to perform an interrupt acknowledge During T1, the process tri-states the address bus During T2, INTA is pulled low and remains low until it becomes inactive in T4 The interrupting devices places an 8-bit interrupt type during INTA is active

HOLD/HLDA Timing Diagrams

T2 T3 T4

CLK

8088 HOLD
HLDA

HOLD
HLDA

Device 2

Bus

Hold State

Memory

The processor will examine HOLD signal at every rising clock edge

If HOLD=1, the processor will pull HLDA high at the end of T4 state (end of the execution of the current instruction) and suspend its normal operation
If HOLD=0, the processor will pull down HLDA at the falling clock edge and resume its normal operation

10.6 System Time Diagrams - INT and HOLD

Maxmode Interrupt acknowledge timing
CLK LOCK

T1

T2

T3

T4

T1

T2

T3

T4

Prevents P to enter a HOLD state

INTA
AD0- AD7 Tri-state First INTA cycle INT type Second INTA cycle two INTA cycles in maxmode, the device requesting INT has to drive the INT type on the Data Bus, during the second cycle. a single INTA cycle in minmode. Tri-state INT type

Minmode Interrupt acknowledge timing

CLK

T1

T2

T3

T4

INTA
AD0- AD7

HOLD/HLDA Timing
T4 T1

only after ending the current bus cycle

CLK
HOLD

HOLD state: the P releases the Address, HLDA Data, Control and Status buses (these pins are tri-sated (high impedance)