INTERRUPTS

Interrupt is a process where an external device can get the attention of the microprocessor.
The process starts from the I/O device The process is asynchronous.

What happens when MP is interrupted ?

When the Microprocessor receives an interrupt signal, it suspends the currently executing program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt. Each interrupt will most probably have its own ISR.

 Classification of Interrupts
Interrupts can be classified into two types:
Maskable Interrupts (Can be delayed or Rejected) Non-Maskable Interrupts (Can not be delayed or Rejected)

Interrupts can also be classified into:

Vectored The address of the subroutine is already known to the

Microprocessor Non-vectored The device will have to supply the address of the subroutine to the Microprocessor

 The 8085 has 5 interrupt inputs.

The INTR input.
The INTR input is the only non-vectored interrupt. INTR is maskable using the EI/DI instruction pair.

RST 5.5, RST 6.5, RST 7.5 are all automatically vectored.
RST 5.5, RST 6.5, and RST 7.5 are all maskable.

TRAP is the only non-maskable interrupt in the 8085

TRAP is also automatically vectored

The 8085 Non-Vectored Interrupt Process

1. The interrupt process should be enabled using the EI instruction. 2. The 8085 checks for an interrupt during the execution of every instruction. 3. If INTR is high, MP completes current instruction, disables the interrupt and sends INTA (Interrupt acknowledge) signal to the device that interrupted 4. INTA allows the I/O device to send a RST instruction through data bus. 5. Upon receiving the INTA signal, MP saves the memory location of the next instruction on the stack and the program is transferred to call location (ISR Call) specified by the RST instruction

6. Microprocessor Performs the ISR. 7. ISR must include the EI instruction to enable the further interrupt within the program. 8. RET instruction at the end of the ISR allows the MP to retrieve the return address from the stack and the program is transferred back to where the program was interrupted.

8085 recognizes 8 RESTART instructions: RST0 - RST7. each of these would send the execution to a predetermined
hard-wired memory location

Hardware Generation of RST Opcode

How does the external device produce the opcode for the appropriate RST instruction?
The opcode is simply a collection of bits. So, the device needs to set the bits of the data bus to the appropriate value in response to an INTA signal.

 The following is an example of generating RST 5: RST 5s opcode is EF = D D 76543210 11101111

Write a program to count continuously in binary with one second delay between each Count. Service routine at XX70H to flush FFH five times when the interrrupt occurs with some appropriate delay between flash

Main program

Service routine XX70: SERV: PUSH B PUSH PSW MVI B, 0AH MVI A, 00H OUT PORT1 CALL DELAY CMA DCR B JNZ FLASH POP PSW POP B EI RET

XX00 XX03 XX04 XX06 L1 XX08 XX0A XX0D XX0E

LXI SP, XX99H EI MVI A, 00H OUT PORT1 MVI C,01H CALL DELAY INR A JMP L1

FLASH:

Interrupt instr: EF At 0028H JMP xx70H

Issues in Implementing INTR Interrupts

How long must INTR remain high?
The microprocessor checks the INTR line one clock cycle before the last T-state of each instruction. The INTR must remain active long enough to allow for the longest instruction. The longest instruction for the 8085 is the conditional CALL instruction which requires 18 T-states.

Therefore, the INTR must remain active for 17.5 T-states. If f= 3MHZ then T=1/f and so, INTR must remain active for [ (1/3MHZ) * 17.5 5.8 micro seconds].

 How long can the INTR remain high?

The INTR line must be deactivated before the EI is executed. Otherwise, the microprocessor will be interrupted again. Once the microprocessor starts to respond to an INTR interrupt, INTA becomes active (=0).

Therefore, INTR should be turned off as soon as the INTA signal is received.

 Can the microprocessor be interrupted again before the completion of the ISR?
As soon as the 1st interrupt arrives, all maskable interrupts are disabled. They will only be enabled after the execution of the EI instruction.

Therefore, the answer is: only if we allow it to. If the EI instruction is placed early in the ISR, other interrupt may occur before the ISR is done.

Multiple Interrupts & Priorities

How do we allow multiple devices to interrupt using the INTR line?
The microprocessor can only respond to one signal on INTR at a time. Therefore, we must allow the signal from only one of the devices to reach the microprocessor. We must assign some priority to the different devices and allow their signals to reach the microprocessor according to the priority.

The Priority Encoder

The solution is to use a circuit called the priority encoder (74LS148).
This circuit has 8 inputs and 3 outputs. The inputs are assigned increasing priorities according to the increasing index of the input.
Input 7 has highest priority and input 0 has the lowest.

The 3 outputs carry the index of the highest priority active input

The Priority Encoder

Multiple Interrupts & Priorities

Note that the opcodes for the different RST instructions follow a set pattern.
Bit D5, D4 and D3 of the opcodes change in a binary sequence from RST 7 down to RST 0. The other bits are always 1. This allows the code generated by the 74366 to be used directly to choose the appropriate RST instruction.

The one draw back to this scheme is that the only way to change the priority of the devices connected to the 74366 is to reconnect the hardware.

The 8085 Maskable/Vectored Interrupts

The 8085 has 4 Masked/Vectored interrupt inputs INTERRUPTS CALL LOCATION TRAP 0024H RST 5.5 002CH RST 6.5 0034H RST 7.5 003CH

TRAP
TRAP is the only non-maskable interrupt. It does not need to be enabled because it cannot be disabled. It has the highest priority amongst interrupts. It is edge and level sensitive. It needs to be high and stay high to be recognized. Once it is recognized, it wont be recognized again until it goes low, then high again. TRAP is usually used for power failure and emergency shutoff.

The 8085 Maskable/Vectored Interrupts

The 8085 has 4 Masked/Vectored interrupt inputs.
Maskable interrupts:RST 5.5, RST 6.5, RST 7.5
They are all maskable. They are automatically vectored according to the following table:
Interrupt RST 5.5 RST 6.5 RST 7.5 Vector 002CH 0034H 003CH

The vectors for these interrupt fall in between the vectors for the RST instructions. Thats why they have names like RST 5.5 (RST 5 and a half).

Masking RST 5.5, RST 6.5 and RST 7.5

These three interrupts are masked at two levels:
Through the Interrupt Enable flip flop and the EI/DI instructions.
The Interrupt Enable flip flop controls the whole maskable interrupt process.

Through individual mask flip flops that control the availability of the individual interrupts.
These flip flops control the interrupts individually.

Maskable Interrupts and vector locations

The 8085 Maskable/Vectored Interrupt Process

1. The interrupt process should be enabled using the EI instruction. 2. The 8085 checks for an interrupt during the execution of every instruction. 3. If there is an interrupt, and if the interrupt is enabled using the interrupt mask, the microprocessor will complete the executing instruction, and reset the interrupt flip flop. 4. The microprocessor then executes a call instruction that sends the execution to the appropriate location in the interrupt vector table.

The 8085 Maskable/Vectored Interrupt Process

5. When the microprocessor executes the call instruction, it saves the address of the next instruction on the stack. 6. The microprocessor jumps to the specific service routine. 7. The service routine must include the instruction EI to re-enable the interrupt process. 8. At the end of the service routine, the RET instruction returns the execution to where the program was interrupted.

Manipulating the Masks

The Interrupt Enable flip flop is manipulated using the EI/DI instructions. The individual masks for RST 5.5, RST 6.5 and RST 7.5 are manipulated using the SIM instruction.
This instruction takes the bit pattern in the Accumulator and applies it to the interrupt mask enabling and disabling the specific interrupts.

How SIM Interprets the Accumulator

7 6 5 4 3 2 1 0

SDO SDE XXX R7.5 MSE M7.5 M6.5 M5.5

RST5.5 Mask RST6.5 Mask RST7.5 Mask

Serial Data Out

0 - Available 1 - Masked

Enable Serial Data 0 - Ignore bit 7 1 - Send bit 7 to SOD pin

Mask Set Enable 0 - Ignore bits 0-2 1 - Set the masks according to bits 0-2

Not Used

Force RST7.5 Flip Flop to reset If it is 1, RST 7.5 flip flop is reset,OFF

SIM and the Interrupt Mask

Bit 0 is the mask for RST 5.5, bit 1 is the mask for RST 6.5 and bit 2 is the mask for RST 7.5.
If the mask bit is 0, the interrupt is available. If the mask bit is 1, the interrupt is masked.

Bit 3 (Mask Set Enable - MSE) is an enable for setting the mask.
If it is set to 0 the mask is ignored and the old settings remain. If it is set to 1, the new setting are applied. The SIM instruction is used for multiple purposes and not only for setting interrupt masks.
It is also used to control functionality such as Serial Data Transmission. Therefore, bit 3 is necessary to tell the microprocessor whether or not the interrupt masks should be modified

SIM and the Interrupt Mask

The RST 7.5 interrupt is the only 8085 interrupt that has memory.
If a signal on RST7.5 arrives while it is masked, a flip flop will remember the signal. When RST7.5 is unmasked, the microprocessor will be interrupted even if the device has removed the interrupt signal. This flip flop will be automatically reset when the microprocessor responds to an RST 7.5 interrupt.

Bit 4 of the accumulator in the SIM instruction allows explicitly resetting the RST 7.5 memory even if the microprocessor did not respond to it. Bit 5 is not used by the SIM instruction

Using the SIM Instruction to Modify the Interrupt Masks

Enable all the interrupts in an 8085 system. PROGRAM: EI MVI A,08H SIM

Using the SIM Instruction to Modify the Interrupt Masks

Set the interrupt masks so that RST5.5 is enabled, RST6.5 is masked, and RST7.5 is enabled.

 First, determine the contents of the accumulator

- Enable 5.5 - Disable 6.5 - Enable 7.5 - Allow setting the masks - Dont reset the flip flop - Bit 5 is not used - Dont use serial data - Serial data is ignored

bit 0 = 0 bit 1 = 1 bit 2 = 0 bit 3 = 1 bit 4 = 0 bit 5 = 0 bit 6 = 0 bit 7 = 0

Contents of accumulator are: 0AH

EI MVI A, 0A SIM

; Enable interrupts including INTR ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5 ; Apply the settings RST masks

SDO SDE XXX R7.5 MSE M7.5 M6.5 M5.5 0 0 0 0 1 0 1 0

How RIM sets the Accumulators different bits

The RIM Instruction and the Masks

Bits 0-2 show the current setting of the mask for each of RST 7.5, RST 6.5 and RST 5.5 They return the contents of the three mask flip flops. They can be used by a program to read the mask settings in order to modify only the right mask. Bit 3 shows whether the maskable interrupt process is enabled or not. It returns the contents of the Interrupt Enable Flip Flop. It can be used by a program to determine whether or not interrupts are enabled.

The RIM Instruction and the Masks

Bits 4-6 show whether or not there are pending interrupts on RST 7.5, RST 6.5, and RST 5.5
Bits 4 and 5 return the current value of the RST5.5 and RST6.5 pins. Bit 6 returns the current value of the RST7.5 memory flip flop.

Bit 7 is used for Serial Data Input.

The RIM instruction reads the value of the SID pin on the microprocessor and returns it in this bit.

Assuming the MP is completing an RST 7.5 interrupt request, check to see if RST 6.5 is pending, enable RST 6.5 without affecting any other interrupts; otherwise return to main program.

The 8085 Interrupts

Interrupt Name INTR RST 5.5 / RST 6.5 RST 7.5 Maskable Masking Method DI / EI DI / EI SIM Vectored Memory Triggering Method Level Sensitive Level Sensitive

Yes Yes Yes

No Yes Yes

No No Yes

DI / EI SIM
None

Edge Sensitive
Level & Edge Sensitive

TRAP

No

Yes

No

RESTART AS SOFTWARE INSTRUCTION

A breakpoint is a Restart(RST) instruction in a program where the execution of program stops temporarily and program control is transferred to the RST location. The program should be transferred from the RST location to the breakpoint service routine to allow the user to examine register or memory contents when specified keys are pressed.

The breakpoint procedure allows the user to test programs in segments.

PROBLEM STATEMENT Implement a breakpoint facility at RST 5 for user. When the user writes RST 5 in the program the program should 1. be interrupted at the instruction RST 5 . 2. display the accumulator content and the flags when Hex key A(1010) is pressed. 3. Exit the breakpoint routine and continue execution when the Zero key(0000) is pressed.

PUSH B PUSH D
POP D POP B POP PSW RET