Reduced Instruction Set Computers
{Make hardware Simpler, but quicker}
Key features
Large number of general purpose registers Use of compiler technology to optimize register use Limited and simple instruction set Emphasis on optimising the instruction pipeline
Comparison of processors
CISC IBM DEC VAX Intel 370/168 11/780 486 1973 1978 1989 No. of instruction 208 303 RISC Motorola MIPS 88000 R4000 1988 1991 Superscalar IBM Intel RS/6000 80960 1990 1989
235
51
94
184
62
Instruction size (octets) 2-6 2-57 1-11
Addressing modes 4 22 GP Registers 16 16
32
4 or 8
11
11
32
32
32
23-256
Control memory (k bytes) (microprogramming) 420 480 246 0
Driving force for CISC
Software costs far exceed hardware costs Increasingly complex high level languages Semantic gap Leads to:
Large instruction sets More addressing modes Hardware implementations of HLL statements
e.g. CASE (switch) on VAX
Intention of CISC
Ease compiler writing Improve execution efficiency
Complex operations in microcode
Support more complex HLLs
=Program Execution Characteristics:
Operations performed Operands used Execution sequencing Studies have been done based on programs written in HLLs Dynamic studies are measured during the execution of the program
-Operations
Assignments
Movement of data
Conditional statements (IF, LOOP)
Sequence control
Procedure call-return is very time consuming Some HLL instruction lead to many machine code operations
-Relative Dynamic Frequency
Dynamic Machine Instruction Memory
Assign Loop Call If GoTo Other
Pascal C 45 38 5 3 15 12 29 43 3 6 1
Pascal C 13 13 42 32 31 33 11 21 3 1
Pascal C 14 15 33 26 44 45 7 13 2 1
-Operands
Mainly local scalar variables Optimisation should concentrate on accessing local variables Pascal 16 58 26 C 23 53 24 Average 20 55 25
Integer constant Scalar variable Array/structure
-Procedure Calls
Very time consuming Depends on number of parameters passed Depends on level of nesting Most programs do not do a lot of calls followed by lots of returns Most variables are local (c.f. locality of reference)
Implications: RISC
Best support is given by optimising most used and most time consuming features Large number of registers
Operand referencing
Careful design of pipelines
Branch prediction etc.
Simplified (reduced) instruction set
-Large Register File
Software solution
Require compiler to allocate registers Allocate based on most used variables in a given time Requires sophisticated program analysis
Hardware solution
Have more registers Thus more variables will be in registers
-Registers for Local Variables //
Store local scalar variables in registers Reduces memory access Every procedure (function) call changes locality Parameters must be passed Results must be returned Variables from calling programs must be restored all in registers
-Register Windows
Only few parameters Limited range of depth of call Use multiple small sets of registers Calls switch to a different set of registers Returns switch back to a previously used set of registers
Register Windows cont.
Three areas within a register set
Parameter registers (ins) Local registers (locals) Temporary registers (outs)
Temporary registers from one set overlap parameter registers from the next This allows parameter passing without moving data
Overlapping Register Windows
Circular (call and return registers) e.g. 24 reg/wind * 8 wind
Circular Buffer diagram
Operation of Circular Buffer
When a call is made, a current window pointer is moved to show the currently active register window If all windows are in use, an interrupt is generated and the oldest window (the one furthest back in the call nesting) is saved to memory A saved window pointer indicates where the next saved windows should restore to
Global Variables
Allocated by the compiler to memory
Inefficient for frequently accessed variables
Have a set of registers for global variables
=Registers v Cache
Large Register File Cache
All local scalars Recently used local scalars Individual variables Blocks of memory Compiler assigned global variables Recently used global variables Save/restore based on procedure Save/restore based on nesting caching algorithm Register addressing Memory addressing
Referencing a Scalar Window Based Register File
Referencing a Scalar - Cache
Compiler Based Register Optimization
Assume small number of registers (16-32) Optimizing use is up to compiler HLL programs have no explicit references to registers
usually - think about C - register int
Assign symbolic or virtual register to each candidate variable Map (unlimited) symbolic registers to real registers Symbolic registers that do not overlap can share real registers If you run out of real registers, some variables use memory
Why CISC (1)?
Compiler simplification?
Disputed Complex machine instructions harder to exploit Optimization more difficult
Smaller programs?
Program takes up less memory but Memory is now cheap May not occupy less bits, just look shorter in symbolic form
More instructions require longer op-codes Register references require fewer bits
Why CISC (2)?
Faster programs?
Bias towards use of simpler instructions More complex control unit Microprogram control store larger thus simple instructions take longer to execute
It is far from clear that CISC is the appropriate solution
RISC Characteristics
One instruction per cycle Register to register operations Few, simple addressing modes Few, simple instruction formats Hardwired design (no microcode) Fixed instruction format More compile time/effort
=RISC v CISC
Not clear cut Many designs borrow from both philosophies e.g. PowerPC and Pentium II
RISC Pipelining
Most instructions are register to register Two phases of execution
I: Instruction fetch E: Execute
ALU operation with register input and output
For load and store
I: Instruction fetch E: Execute
Calculate memory address
D: Memory
Register to memory or memory to register operation
Controversy
Quantitative
compare program sizes and execution speeds
Qualitative
examine issues of high level language support and use of VLSI real estate
Problems
No pair of RISC and CISC that are directly comparable No definitive set of test programs Difficult to separate hardware effects from complier effects Most comparisons done on toy rather than production machines Most commercial devices are a mixture
Required Reading
Stallings chapter 12 Manufacturer web sites
