ELE 711

Testing
Week 11

VLSI Realization Process

Customers need Determine requirements Write specifications

Design synthesis and Verification

Test development

Fabrication
Manufacturing test
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Chips to customer

Definitions
Design synthesis: Given an I/O function,

develop a procedure to manufacture a device using known materials and processes. Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Verification vs. Test

Verifies correctness of design. Performed by simulation, Verifies correctness of

hardware emulation, or formal methods. Performed once prior to manufacturing. Responsible for quality of design.

manufactured hardware. Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware Test application performed on every manufactured device. Responsible for quality of devices.

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Test Classification
Diagnostic test

used in chip/board debugging defect localization used to determine whether a chip is functional simpler than diagnostic test; must be simple & swift x e [v,i] versus x e [0,1]

Go/no-go or production test

Parametric test (static/dc and dynamic/ac tests)

check parameters such as Vt, tp, T

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Why such a big deal?

High speed testers are astronomically costly!

Reducing test time can help increase

throughput of tester

impacts testing cost

Testing must be considered from early

phases of the design process

Validation and Test of Manufactured Circuits

Goals of Design-for-Test (DFT)

make testing of manufactured part swift & comprehensive provide controllability and observability provide circuitry to enable test provide test patterns that guarantee reasonable coverage
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

DFT mantra

Components of DFT strategy

Design for Testability (DFT)

DFT refers to hardware design styles or added hardware that reduces test generation complexity.
Motivation: Test generation complexity increases exponentially with the size of the circuit. Example: Test hardware applies tests to blocks A and B and to internal bus; avoids test generation for combined A and B blocks. Int. Logic bus Logic PO PI block A block B Test input Test output

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Costs of Testing
Design for testability (DFT) Chip area overhead and yield reduction Performance overhead Software processes of test Test generation and fault simulation Test programming and debugging Manufacturing test Automatic test equipment (ATE) capital cost Test center operational cost
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Cost of Manufacturing Testing in 2000AD

0.5-1.0GHz, analog instruments,1,024 digital pins:

ATE purchase price

= $1.2M + 1,024 x $3,000 = $4.272M

Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Roles of Testing
Detection: Determination whether or not the device

under test (DUT) has some fault. Diagnosis: Identification of a specific fault that is present on DUT. Device characterization: Determination and correction of errors in design and/or test procedure. Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Testing as Filter Process

Good chips Prob(pass test) = high Prob(good) = y Fabricated chips Defective chips Prob(bad) = 1- y Prob(fail test) = high Mostly bad chips Mostly good chips

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Testing Principle

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Problem: Controllability & Observability

Combinational circuits

controllable and observable relatively easy to determine test patterns turn into combination circuits or, use self-test use self-test

Sequential circuits: have state!

Memory: requires complex patterns

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

A Modern VLSI Device System-on-a-chip (SOC)

Data terminal

DSP core Interface logic

RAM ROM

Mixedsignal Codec

Transmission medium

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Generating and Validating Test-Vectors

Automatic test-pattern generation (ATPG)

for given fault, determine excitation vector (called test vector) that will propagate error to primary (observable) output majority of available tools: combinational only sequential ATPG available from academic research
determines test coverage of proposed test-vector set simulates correct network in parallel with faulty networks

Fault simulation

Both require adequate models of faults in CMOS

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

ATPG definition
Operations on digital hardware:

Inject fault into circuit modeled in computer Use various ways to activate and propagate fault effect through hardware to circuit output Output flips from expected to faulty signal Electron-beam (E-beam) test observes internal signals picture of nodes charged to 0 and 1 in different colors Too expensive Scan design add test hardware to all flip-flops to make them a giant shift register in test mode Can shift state in, scan state out Widely used makes sequential test combinational Costs: 5 to 20% chip area, circuit delay, extra pin, longer test sequence

Some Real Defects in Chips

Processing defects

Missing contact windows Parasitic transistors Oxide breakdown ... Bulk defects (cracks, crystal imperfections) surface impurities (ion migration) ...

Material defects

Time-dependent failures

Dielectric breakdown Electromigration ...

Contact degradation Seal leaks ...

Packaging failures

Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation Semiconductor Devices and Circuits, Wiley, 1981.
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Observed PCB Defects

Defect classes Shorts Opens Missing components Wrong components Reversed components Bent leads Analog specifications Digital logic Performance (timing) Occurrence frequency (%) 51 1 6 13 6 8 5 5 5

Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Stuck At hatalar
Eldred (1959) First use of structural

testing for the Honeywell Datamatic 1000 computer Galey, Norby, Roth (1961) First publication of stuck-at-0 and stuck-at-1 faults Seshu & Freeman (1962) Use of stuckfaults for parallel fault simulation Poage (1963) Theoretical analysis of stuck-at faults

Common Fault Models

Single stuck-at faults

Transistor open and short faults

Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Delay faults (transition, path) Analog faults

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Fault Models
Most Popular - Stuck - at model

0 1

sa0 (output)

sa1 (input)

Covers almost all (other) occurring faults, such as opens and shorts.
Z

x1

x3

x2
[Adapted from http://infopad.eecs.berkeley.edu/~icdes ign/. Copyright 1996 UCB]

, : x1 sa1 : x1 sa0 or x2 sa0 : Z sa1

Single Stuck-at Fault

Three properties define a single stuck-at fault Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate

Example: XOR circuit has 12 fault sites ( ) and 24 single

stuck-at faults
c
1 0 s-a-0

Faulty circuit value Good circuit value

a b

d
e f

0(1) 1(0) 1

g
1

h i k

Test vector for h s-a-0 fault

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Equivalence Rules
sa0 sa0 sa1

sa0 sa1

sa1

sa0 sa1

AND
sa0 sa1

sa0 sa1 sa0 sa1

OR

sa0 sa1

WIRE

sa0 sa1 sa0 sa1 sa0 sa1

NOT

sa1 sa0

NAND
sa0 sa1

sa0 sa1 sa0 sa1

NOR

sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1

FANOUT
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Equivalence Example
sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 20 Collapse ratio = ----- = 0.625 32 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 Faults in red removed by equivalence collapsing

sa0 sa1
sa0 sa1

sa0 sa1

sa0 sa1

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Problem with stuck-at model: CMOS open fault

x1 Z x1 x2 x2

Sequential effect
Needs two vectors to ensure detection! Other options: use stuck-open or stuck-short models This requires fault-simulation and analysis at the switch or transistor level - Very expensive!
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Another Stuck-Short Example

Test vector for A s-a-0 pMOS FETs 1 0

VDD
Stuckshort

A B

IDDQ path in faulty circuit

Good circuit state

0 (X)

nMOS FETs
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Faulty circuit state

Summary of Fault Models

Fault models are analyzable approximations of

defects and are essential for a test methodology. For digital logic single stuck-at fault model offers best advantage of tools and experience. Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests. Stuck-short and delay faults and technologydependent faults require special tests. Memory and analog circuits need other specialized fault models and tests.

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Functional and Structural FPGA

Carry Circuit

Functional Structural ATPG

Functional ATPG generate complete set of tests for

circuit input-output combinations

129 inputs, 65 outputs: 2129 = 680,564,733,841,876,926,926,749,

214,863,536,422,912 patterns
Using 1 GHz ATE, would take 2.15 x 1022 years

Structural test: No redundant adder hardware, 64 bit slices Each with 27 faults (using fault equivalence) At most 64 x 27 = 1728 faults (tests) Takes 0.000001728 s on 1 GHz ATE Designer gives small set of functional tests augment

with structural tests to boost coverage to 98+ %

Circuits and BDD

BDD
BDD Follow path from source to sink node

product of literals along path gives Boolean value at sink Rightmost path: A B C = 1 Problem: Size varies greatly with variable order

Algorithmic Completeness
Definition: Algorithm is complete if it

ultimately can search entire binary decision tree, as needed, to generate a test Untestable fault no test for it even after entire tree searched Combinational circuits only untestable faults are redundant, showing the presence of unnecessary hardware

Exhaustive Solution
For n-input circuit, generate all 2^n input

patterns Infeasible, unless circuit is partitioned into cones of logic, with <= 15 inputs

Perform exhaustive ATPG for each cone Misses faults that require specific activation patterns for multiple cones to be tested

Random number
Flow chart for

method Use to get tests for 6080% of faults, then switch to D-algorithm or other ATPG for rest

Automatic Test Pattern Generation: Path Sensitization

Goals: Determine input pattern that makes a fault controllable (triggers the fault, and makes its impact visible at the output nodes) 1 1 sa0 1 1 0
Out

Fault enabling

1 1 Fault propagation 0

Techniques Used: D-algorithm, Podem

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Example

Using 5-Valued Logic

Failing Good Symbol Meaning Machine Machine 1 D 0/1 0 0 D 1/0 1 0 0 0/0 0 1 1 1/1 1 X X X/X X

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Represent two machines, which are simulated simultaneously: Good circuit machine (1st value) Bad circuit machine (2nd value)

Multiple Fault Masking

f sa0 masked when fault q sa1 also present

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Multipath Sensitization Problem

Path Sensitization Method Circuit Example

Try path f h k L blocked at j, since
there is no way to justify the 1 on i
1 1 D D D

1
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Path Sensitization Method Circuit Example

Try simultaneous paths f h k L and
g i j k L blocked at k because Dfrontier (chain of D or D) disappears
1 1 D D 1

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Path Sensitization Method Circuit Example

Final try: path g i j k L test found!
0 1

0
D D D

1 1

[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]

Path Sensitization Method

Final try: path g i j k L test found!

 The path-oriented decision making ( PODEM ) algorithm

1. 2. 3.

4.

solves the problem of reconvergent fanout and allows multipath sensitization [ Goel, 1981]. The method is similar to the basic algorithm we have already described except PODEM will retry a step, reversing an incorrect decision. There are four basic steps that we label: objective , backtrace , implication , and Dfrontier . These steps are as follows: Pick an objective to set a node to a value. Start with the fault origin as an objective and all other nodes set to 'X'. Backtrace to a PI and set it to a value that will help meet the objective. Simulate the network to calculate the effect of fixing the value of the PI (this step is called implication ). If there is no possibility of sensitizing a path to a PO, then retry by reversing the value of the PI that was set in step 2 and simulate again. Update the D-frontier and return to step 1. Stop if the D-frontier reaches a PO.

Podem at work

 We start with activation of the fault as our objective, U3.A2 = '0'. We

backtrace to J. We set J = '1'. Since K is still 'X', implication gives us no further information. We have no D-frontier to update. The objective is unchanged, but this time we backtrace to K. We set K = '1'. Implication gives us U2.ZN = 0' (since now J = '1' and K = '1') and therefore U7.ZN = '1'. We still have no D-frontier to update. We set U3.A1 = '1' as our objective in order to propagate the fault through U3. We backtrace to M. We set M = '1'. Implication gives us U2.ZN = '1' and U3.ZN = D. We update the D-frontier to reflect that U4.A2 = D and U6.A1 = D, so the D-frontier is U4 and U6. We pick U6.A2 = '1' as an objective in order to propagate the fault through U6. We backtrace to N. We set N = '1'. Implication gives us U6.ZN = D . We update the D-frontier to reflect that U4.A2 = D and U8.A1 = D , so the Dfrontier is U4 and U8. We pick U8.A1 = '1' as an objective in order to propagate the fault through U8. We backtrace to L. We set L = '0'. Implication gives us U5.ZN = '0' and therefore U8.ZN = 1' (this node is Z, the PO). There is then no possible sensitized path to the PO Z. We must have made an incorrect decision, we retry and set L = '1'. Implication now gives us U8.ZN = D and we have propagated the D-frontier to a PO.

ELE 711
TEST N TASARIM
DFT Week 11

DFT Definition
Design for testability (DFT) refers to those design

techniques that make test generation and test application cost-effective. DFT methods for digital circuits:

Ad-hoc methods Structured methods: Scan Partial Scan Built-in self-test (BIST) Boundary scan

DFT method for mixed-signal circuits: Analog test bus

Test Approaches
Problem gets harder

increasing complexity and heterogeneous combination of modules in systems-on-a-chip advanced packaging and assembly techniques extend problem to the board level

Data terminal

DSP cor e Interface logic

RAM ROM Mixedsignal Codec

Transmission medium

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Ad-hoc methods
Good design practices learnt through experience are used as

guidelines:

Avoid asynchronous (unclocked) feedback.

May result in oscillation Make flip-flops initializable. (clear + reset)

Avoid redundant gates. Avoid large fanin gates.(Large fan-in makes the inputs difficult to observe and the output difficult to control). Provide test control for difficult-to-control signals (long counter). Avoid gated clocks.

Disadvantages of ad-hoc DFT methods: Experts and tools not always available. Test generation is often manual with no guarantee of high fault coverage. Design iterations may be necessary.

Ad-hoc Test
Memory
address data data

Memory
address

test

select

Processor Processor

I/O bus I/O bus

Inserting multiplexer improves testability

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Scan
Proposed in '73 by Williams and Angell.
Two modes available: Normal and Test

Scan-based Test
ScanIn ScanOut Out

Register

Logic A

Register

In

Combinational

Combinational Logic B

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Scan-based Test: Operation

In 0 Test ScanIn Latch Test Test In1 Test Test In2 Test Test In 3 Test ScanOut Latch Latch Latch

Out0

Out1

Out2

Out3

Test 1 2 N cycles scan-in 1 cycle evaluation N cycles scan-out

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Scan Design

Circuit is designed using pre-specified design rules. Test structure (hardware) is added to the verified design: Add a test control (TC) primary input. Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. Make input/output of each scan shift register controllable/observable from PI/PO. Use combinational ATPG to obtain tests for all testable faults in the combinational logic. Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test.

Scan Design Rules!

A designer needs to observe four rules during functional design: Only D-type master-slave FFs should be used

No JK, toggle FFs or other forms of asynchronous logic.

At least one PI must be available for test. All FFs must be controlled from PIs. Simple circuit transformations can be used to change FFs whose Clk is "gated" by an internal logic signal. Clocks must not feed data inputs of the FFs. A race condition can result in normal mode otherwise. This is generally considered good design practice anyway.

 All clocks must be controlled from PIs.

Comb. logic D1 Q FF Comb. logic

D2 CK

Comb. logic D1 D2 Q

FF

CK

Comb. logic

Scan Flip Flop

D TC
Logic overhead

Master latch

Slave latch

Q
MUX

SD CK

D flip-flop

CK

Master open Slave open

t
Scan mode, SD selected

TC

Normal mode, D selected

scan is usually inserted after the circuit is verified to be functionally correct.

Scan yapsn eklemek

PI Combinational logic PO

SFF
SFF SFF

SCANOUT

TC or TCK SCANIN

Not shown: CK or MCK/SCK feed all SFFs.

Adding Scan
Scan flip-flops can be distributed among any number

of shift registers, each having a separate scanin and scanout pin. Test sequence length is determined by the longest scan shift register. Just one test control (TC) pin is essential.
PI/SCANIN Combinational logic SFF SFF TC SFF
M U X

PO/ SCANOUT

CK

Hierarchical Scan
Scan flip-flops are chained within subnetworks before

chaining subnetworks. Advantages:

Automatic scan insertion in netlist Circuit hierarchy preserved helps in debugging and design changes
Scanout

Disadvantage: Non-optimum chip layout.

Scanin SFF1 SFF4

Scanin
SFF2 SFF3

SFF1

SFF3
Scanout

SFF4

SFF2

Hierarchical netlist

Flat layout

Optimum Scan Layout

X IO pad Flipflop cell SFF cell SCANIN X

TC

SCAN OUT

Routing channels

Interconnects

Active areas: XY and XY

Boundary Scan (JTAG or IEEE1149)

Printed-circuit board Logic Packaged IC

normal interconnect

Scan-in Scan-out

si

so scan path

Bonding Pad

Board testing becomes as problematic as chip testing

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Automatic Scan Design

Rule violations
Scan design rule audits Gate-level netlist Combinational ATPG Combinational vectors Scan sequence and test program generation Scan chain order Scan hardware insertion

Behavior, RTL, and logic Design and verification

Scan netlist
Chip layout: Scanchain optimization, timing verification

Test program

Design and test data for manufacturing

Mask data

Analog Fault modelling not too practical for ATPG

Huge # of different possible analog faults

in digital circuit Exponential complexity of ATPG algorithm a 20 flip-flop circuit can take days of computing

Cannot afford to go to a lower-level model

Most test-pattern generators for digital

circuits cannot model at the transistor switch level

DFT Summary
Scan is the most popular DFT technique:

Rule-based design Automated DFT hardware insertion Combinational ATPG Design automation High fault coverage; helpful in diagnosis Hierarchical scan-testable modules are easily combined into large scan-testable systems Moderate area (~10%) and speed (~5%) overheads Large test data volume and long test time Basically a slow speed (DC) test

Advantages:

Disadvantages:

ELE 711
TEST
BIST Week 11

Built-in Self-test (BIST)

(Sub)-Circuit Stimulus Generator Under Test Response Analyzer

Test Controller

Rapidly becoming more important with increasing chip-complexity and larger modules
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

BIST Architecture

Definitions
Aliasing Due to information loss, signatures of

good some bad machines match Compaction Drastically reduce # bits in original response lose information Compression Reduce # bits in original circuit response no information loss fully invertible (can get back response) Signature analysis Compact good machine response good machine signature. Actual signature generated during testing, and compared with good machine Transition Count Response Compaction Count # transitions from 0 1 and 1 0 as a signature

LFSR

A linear feedback shift register (LFSR). A 3-bit maximal-length LFSR produces a repeating string of seven pseudorandom binary numbers: 7, 3, 1, 4, 2, 5, 6.

Linear-Feedback Shift Register (LFSR)

R S0 1 0 1 1 1 0 0 1 R S1 0 1 0 1 1 1 0 0 R S2 0 0 1 0 1 1 1 0

Pseudo-Random Pattern Generator: 2N-1 states

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Standard N Layer LFSR

Signature Analysis
In Counter R

Counts transitions on single-bit stream Compression in time

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Signature Generator

A 3-bit serial-input signature register (SISR) using an LFSR (linear feedback shift register). The LFSR is initialized to Q1Q2Q3 = '000' using the common RES (reset) signal. The signature, Q1Q2Q3, is formed from shift-and-add operations on the sequence of input bits (IN).

BIST example

BILBO
B0 B1 ScanOut R S0 R S1 R S2 D0 D1 D2

ScanIn

mux
1 0 1 0

B0=0

B0 B1 1 0 0 1

Operation mode Normal Scan Pattern generation or Signature analysis Reset

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

BILBO Application
ScanIn ScanOut

BILBO-A

Logic

BILBO-B

In

Combinational

Combinational Logic

Out

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Transition Count