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Seminar On 8257

The document discusses the 8257 DMA controller chip. It has 4 independently programmable channels that can transfer up to 64kb of data per channel using direct memory access. The chip contains address registers, count registers, and control logic to perform read, write, and verify transfers between IO devices and memory without CPU involvement. It interfaces with the 8085 processor using control signals like HOLD/HLDA to request and release control during DMA operations.

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132 views16 pages

Seminar On 8257

The document discusses the 8257 DMA controller chip. It has 4 independently programmable channels that can transfer up to 64kb of data per channel using direct memory access. The chip contains address registers, count registers, and control logic to perform read, write, and verify transfers between IO devices and memory without CPU involvement. It interfaces with the 8085 processor using control signals like HOLD/HLDA to request and release control during DMA operations.

Uploaded by

harmangahir
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Seminar on 8257

8257

It is a device that transfer the data directly between IO device and memory without passing through the CPU. So it performs a high-speed data transfer between memory and I/O device.

The Features of 8257


The 8257 has four channels and it can be used to provide DMA to four I/O devices Each channel can be independently programmable to transfer up to 64kb of data by DMA. Each channel can be independently perform read transfer, write transfer and verify transfer.

Pin Diagram
It is a 40 pin IC and the pin diagram is as follow

The functional blocks of 8257 are data bus buffer, read/write logic, control logic, priority resolver and four numbers of DMA channels.

Functional Block Diagram of 8257

Each channel of 8257 Block diagram has two programmable 16-bit registers named as address register and count register.

Functional Block Diagram of 8257

Block Diagram Description

DMA Channels
Address register is used to store the starting address of memor y location for DMA data transfer. The address in the address register is automatically incremented after ever y read/write/verify transfer.

The count register is used to count the number of byte or word transferred by DMA. The format of count register is

Block Diagram Description


Data Bus Buffer It is also known as Data Bus Lines(D007) These are bi-directional three-state lines. When the 8257 is being programmed by the CPU. Eight bits of data for DMA address register, terminal count register or the Mode Set register are received on the data bus.

Block Diagram Description

Read/Write Logi
The Read/Write Logic generates the I/O read and memory write (DMA write cycle) or I/O Write and memory read (DMA read cycle) signals which control the data link with the peripheral that has been granted the DMA cycle.

Block Diagram Description

Control Logi and mode set register


This block controls the sequence of operations during all DMA cycles by generating the appropriate control signals and the 16-bit address that specifies the memory location to be accessed. The use of mode set register is, 1. Enable/disable a channel 2. Fixed/rotating priority 3. Stop DMA on terminal count. 4.Extended/normal write time. 5. Auto reloading of channel-2.

The internal addresses of the registers of 8257 are listed in table.

INTERFACING OF DMA 8257 WITH 8085

Description OF DMA 8257 WITH 8085


A simple schematic for interfacing the 8257 with 8085 processor is shown. The 8257 can be either memory mapped or I/O mapped in the system. In the schematic shown in figure is I/O mapped in the system. Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices. The address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS-0 to IOCS-7) and in this the chip select signal IOCS-6 is used to select 8257. The address line A7 and the control signal IO/M (low) are used as enable for decoder. The D0-D7 lines of 8257 are connected to data bus lines D0-D7 for data transfer with processor during programming mode.

Description OF DMA 8257 WITH 8085


The 8257 also supply two control signals ADSTB and AEN to latch the address supplied by it during DMA mode on external latches. Two 8-bit latches are provided to hold the 16-bit memory address during DMA mode. During DMA mode, the AEN signal is also used to disable the buffers and latches used for address, data and control signals of the processor. The 8257 provide separate read and write control signals for memory and I/O devices during DMA. Therefore the RD (low), WR (low) and IO/M (low) of the 8085 processor are decoded by a suitable logic circuit to generate separate read and write control signals f memory and I/O devices.

Description OF DMA 8257 WITH 8085


The output clock of 8085 processor should be inverted and supplied to 8257 clock input for proper operation. The HRQ output of 8257 is connected to HOLD input of 8085 in order to make a HOLD request to the processor. The HLDA output of 8085 is connected to HLDA input of 8257, in order to receive the acknowledge signal from the processor once the HOLD request is accepted. The RESET OUT of 8085 processor is connected to RESET of 8257.

THANK YOU

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