INSTRUCTION SET OF 8085

Collected By

C.Gokul AP/EEE
Velalar College of Engg & Tech,Erode

References: http://www.slideshare.net/ , www.eazynotes.com , www.scribd.com 1. Stack & Subroutines by Safin Biswas 2. INSTRUCTION SET OF 8085 by Gursharan Singh Tatla 3. INSTRUCTION SET OF 8085 by Er. Swapnil Kaware

Instruction Set of 8085

An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions that a microprocessor supports is called Instruction Set. 8085 has 246 instructions. Each instruction is represented by an 8-bit binary value. These 8-bits of binary value is called Op-Code or Instruction Byte.

Classification of Instruction Set

Data Transfer Instruction Arithmetic Instructions Logical Instructions Branching Instructions Control Instructions

1.Data Transfer Instructions

These instructions move data between registers, or between memory and registers.

These instructions copy data from source to destination(without changing the original data ).

MOV-Copy from source to destination

Opcode Operand

MOV

Rd, Rs M, Rs Rd, M

This instruction copies the contents of the source

register into the destination register. (contents of the source register are not altered)
If one of the operands is a memory location, its location

is specified by the contents of the HL registers.

Example: MOV B, C or MOV B, M

BEFORE EXECUTION

AFTER EXECUTION

20 B

MOV B,A

20

20

A F B 30 C D E H 20 L 50 A B D H 20 F C E L 50

MOV M,B

A B

F 30 C 50

D E H 20 L

30

40

A B MOV C,M D H 20

F C 40 E L 50

40

MVI-Move immediate 8-bit

Opcode Operand
Rd, Data M, Data

MVI
memory.

The 8-bit data is stored in the destination register or If the operand is a memory location, its location is

specified by the contents of the H-L registers.

Example: MVI B, 60H

or

MVI M, 40H

BEFORE EXECUTION

AFTER EXECUTION

A B D H

F C E L

MVI B,60H

A B D H

F 60 C E L

BEFORE EXECUTION

AFTER EXECUTION

204FH

204F

HL=2050
2051H

MVI M,40H

HL=2050 40
2051H

LDA-Load accumulator
Opcode Operand 16-bit address

LDA

The contents of a memory location, specified by a 16-

bit address in the operand, are copied to the accumulator.

The contents of the source are not altered.

Example: LDA 2000H

BEFORE EXECUTION

AFTER EXECUTION

A 2000H

30

LDA 2000H

A 30
2000H

30

LDAX-Load accumulator indirect

Opcode

LDAX

Operand B/D Register Pair

The contents of the designated register pair point to a memory

location.

This instruction copies the contents of that memory location into

the accumulator. not altered.

The contents of either the register pair or the memory location are Example:

LDAX D

BEFORE EXECUTION A B F C 30

AFTER EXECUTION A 80 F

2030H 80

B LDAX D

C 30

2030H

80

D 20 E

D 20 E

LXI-Load register pair immediate

Opcode

LXI

Operand Reg. pair, 16-bit data

This instruction loads 16-bit data in the register pair.

Example: LXI H, 2030 H

BEFORE EXECUTION

AFTER EXECUTION

80

2030H 30 2031H 90

LXI H, 2030

9030H 50
30

H 90 L

M=50

LHLD-Load H and L registers direct

Opcode

LHLD

Operand 16-bit address

This instruction copies the contents of memory

location pointed out by 16-bit address into register L.

It copies the contents of next memory location into

register H.
Example: LHLD 2030 H

BEFORE EXECUTION

AFTER EXECUTION

80

2030H

00 85

LHLD 2030

8500H 60
00

H 85 L

M=60

STA-Store accumulator direct

Opcode

STA

Operand 16-bit address

The contents of accumulator are copied into the

memory location specified by the operand.

Example:

STA 2000

BEFORE EXECUTION

AFTER EXECUTION
A

A 50
2000H

50

STA 2000H

2000H

50

STAX-Store accumulator indirect

Opcode Operand
Reg. pair

STAX

The contents of accumulator are copied into the

memory location specified by the contents of the register pair.

Example: STAX B

collected by C.Gokul AP/EEE , Velalar college of Engineering and Technology, Erode

BEFORE EXECUTION

AFTER EXECUTION

B 85 C 00

A=1AH

STAX B

8500H 1A

SHLD-Store H and L registers direct

Opcode SHLD Operand 16-bit address

The contents of register L are stored into memory

location specified by the 16-bit address.

The contents of register H are stored into the next

memory location.
Example: SHLD

2550H

BEFORE EXECUTION

AFTER EXECUTION

E
8500H

H 70 L 80

SHLD 8500

80 70

8501H

XCHG-Exchange H and L with D and E

Opcode XCHG
contents of register D.

Operand None

The contents of register H are exchanged with the The contents of register L are exchanged with the

contents of register E.
Example: XCHG

BEFORE EXECUTION

AFTER EXECUTION

D 20 E 40 H 70 L 80

D 70 E

80 40

XCHG

H 20 L

SPHL-Copy H and L registers to the stack pointer

Opcode Operand None

SPHL

This instruction loads the contents of H-L pair into SP.

Example: SPHL

BEFORE EXECUTION

SP H 25 L 00

SPHL
AFTER EXECUTION

SP H

2500
25 L 00

XTHL-Exchange H and L with top of stack

Opcode Operand XTHL None
The contents of L register are exchanged with the

location pointed out by the contents of the SP.

The contents of H register are exchanged with the next

location (SP + 1).

Example: XTHL

L=SP H=(SP+1)
BEFORE EXECUTION AFTER EXECUTION

SP H

2700

2700H
40

50 60

SP H

2700

30 L

2700H
L

40 30

2701H 2702H

60

50

2701H

XTHL
2702H

Opcode Operand Description Load program counter with HPCHL None L contents
The contents of registers H and L are copied into the

program counter (PC).

The contents of H are placed as the high-order byte

and the contents of L as the low-order byte.

Example: PCHL

PUSH-Push register pair onto stack

Opcode PUSH Operand Reg. pair

The contents of register pair are copied onto stack.

SP is decremented and the contents of high-order

registers (B, D, H, A) are copied into stack.

SP is again decremented and the contents of low-order

registers (C, E, L, Flags) are copied into stack.

Example: PUSH B

PUSH H

POP- Pop stack to register pair

Opcode POP

Operand Reg. pair

The contents of top of stack are copied into register pair.

The contents of location pointed out by SP are copied to the

low-order register (C, E, L, Flags).

SP is incremented and the contents of location are

copied to the high-order register (B, D, H, A).

Example: POP H

POP H

IN- Copy data to accumulator from a port with 8-bit address

Opcode

IN
Example:

Operand 8-bit port address

The contents of I/O port are copied into accumulator.

IN 8C

BEFORE EXECUTION

PORT 80H

10

IN 80H
AFTER EXECUTION

PORT 80H

10

10

OUT- Copy data from accumulator to a port with 8-bit address

Opcode

OUT
port.
Example:

Operand 8-bit port address

The contents of accumulator are copied into the I/O

OUT 78H

BEFORE EXECUTION

PORT 50H

10

A 40

OUT 50H
AFTER EXECUTION

PORT 50H

40

40

2.Arithmetic Instructions

These instructions perform the operations like:

Addition

Subtract
Increment

Decrement

Addition

Any 8-bit number, or the contents of register, or the contents of memory location can be added to the contents of accumulator. The result (sum) is stored in the accumulator.

No two other 8-bit registers can be added directly.

Example: The contents of register B cannot be added directly to the contents of register C.

ADD
Opcode Operand Description R Add register or memory to ADD M accumulator
The contents of register or memory are added to the

contents of accumulator.

The result is stored in accumulator. If the operand is memory location, its address is specified by

H-L pair.

Example: ADD B or ADD M

BEFORE EXECUTION
A B D H

AFTER EXECUTION

04
C E L

09
C E L 05

05

ADD C A=A+C

B D H

04+05=09 BEFORE EXECUTION

AFTER EXECUTION

A
B D H

04
C E 20 L 50

ADD M A B A=A+M D
10
2050
H

14
C E 20 L 50

10

04+10=14

2050

ADC
Opcode Operand Description R Add register or memory to ADC M accumulator with carry
The contents of register or memory and Carry Flag (CY) are added to the

contents of accumulator.

The result is stored in accumulator.

If the operand is memory location, its address is specified by H-L pair. All flags are modified to reflect the result of the addition. Example: ADC B or ADC M

BEFORE EXECUTION CY A B D H

AFTER EXECUTION

01
50
C E L

A 56

05

ADC C A=A+C+CY

20

D
H

E
L

50+05+01=56
BEFORE EXECUTION CY A H 20 AFTER EXECUTION

1
06
L

2050H
50

30

ADC M A=A+M+CY
H

A 20

37
L

2050H 30
50

06+1+30=37

ADI
Opcode Operand 8-bit data Description Add immediate to accumulator

ADI

The 8-bit data is added to the contents of accumulator.

The result is stored in accumulator.

All flags are modified to reflect the result of the

addition.
Example: ADI 45 H

BEFORE EXECUTION

AFTER EXECUTION

A 03

ADI 05H A=A+DATA(8)

A 08
03+05=08

collected by C.Gokul AP/EEE , Velalar college of Engineering and Technology, Erode

ACI
Opcode Operand Description

ACI

8-bit data Add immediate to accumulator with carry

The 8-bit data and the Carry Flag (CY) are added to the contents of accumulator.
The result is stored in accumulator. All flags are modified to reflect the result of the addition. Example: ACI 45 H

BEFORE EXECUTION

AFTER EXECUTION

CY

A 05

ACI 20H A=A+DATA (8)+CY

26

05+20+1=26

DAD
Opcode Operand Description DAD Reg. pair Add register pair to H-L pair
The 16-bit contents of the register pair are added to

the contents of H-L pair.

The result is stored in H-L pair.

If the result is larger than 16 bits, then CY is set.

No other flags are changed.

Example: DAD B

or

DAD D

BEFORE EXECUTION

AFTER EXECUTION

D 12 E 34 H 23 L 45

D 12 E

34

DAD D H 35 L 79

1234 2345 + ------3579

DAD D HL=HL+DE DAD B HL=HL+BC

Subtraction

Any 8-bit number, or the contents of register, or the contents of memory location can be subtracted from the contents of accumulator. The result is stored in the accumulator.

Subtraction is performed in 2s complement form.

If the result is negative, it is stored in 2s complement form. No two other 8-bit registers can be subtracted directly.
collected by C.Gokul AP/EEE,VCET

SUB
Opcode Operand Description SUB R Subtract register or memory M from accumulator
The contents of the register or memory location are

subtracted from the contents of the accumulator.

The result is stored in accumulator. If the operand is memory location, its address is specified by

H-L pair.
All flags are modified to reflect the result of subtraction.
Example: SUB B or SUB M

BEFORE EXECUTION
A B D H

AFTER EXECUTION

09
C E L

05
C E L 04

04

SUB C A=A-C

B D H

09-04=05 BEFORE EXECUTION

AFTER EXECUTION

A
B D H

14
C E 20 L 50

SUB M A=A-M
10
2050

A
B D H

04
C E 20 L 50

10

14-10=04

2050

SBB
Opcode Operand Description SBB R Subtract register or memory M from accumulator with borrow

The contents of the register or memory location and Borrow Flag (i.e. CY)

are subtracted from the contents of the accumulator.

The result is stored in accumulator.

If the operand is memory location, its address is specified by H-L pair. All flags are modified to reflect the result of subtraction. Example: SBB B or SBB M

BEFORE EXECUTION
CY

AFTER EXECUTION

01
08
C E L

A
B D H

A 02

05

SBB C A=A-C-CY

05

D
H

E
L

08-05-01=02 BEFORE EXECUTION

CY A H 20

AFTER EXECUTION

1
06
L

2050H
50

02

SBB M A=A-M-CY

A H 20

03
L

2050H 02
50

06-02-1=03

SUI
Opcode Operand SUI 8-bit data Description Subtract immediate from accumulator

The 8-bit data is subtracted from the contents of the

accumulator.
The result is stored in accumulator. All flags are modified to reflect the result of subtraction. Example: SUI 05H

BEFORE EXECUTION

AFTER EXECUTION

A 08

SUI 05H A=A-DATA(8)

A 03
08-05=03

SBI
Opcode Operand Description 8-bit data Subtract immediate from SBI accumulator with borrow
The 8-bit data and the Borrow Flag (i.e. CY) is subtracted

from the contents of the accumulator.

The result is stored in accumulator. All flags are modified to reflect the result of subtraction. Example: SBI 45 H
collected by C.Gokul AP/EEE,VCET

BEFORE EXECUTION

AFTER EXECUTION

CY

1
25

SBI 20H A=A-DATA (8)-CY

04

25-20-01=04

Increment / Decrement

The 8-bit contents of a register or a memory location can be incremented or decremented by 1.

The 16-bit contents of a register pair can be incremented or decremented by 1.

Increment or decrement can be performed on any register or a memory location.

INR
Opcode Operand Description INR R Increment register or M memory by 1
The contents of register or memory location are incremented

by 1.

The result is stored in the same place. If the operand is a memory location, its address is specified by

the contents of H-L pair.

Example: INR B or INR M

BEFORE EXECUTION

AFTER EXECUTION

A B D H 10 C E L

INR B R=R+1

B
D H

11

C
E L

10+1=11
BEFORE EXECUTION AFTER EXECUTION

H 20

L 50

2050H

10

INR M M=M+1

H 20

L 50

11

2050H

10+1=11

INX
Opcode Operand Description INX R Increment register pair by 1
The contents of register pair are incremented by 1.

The result is stored in the same place.

Example: INX H

or INX B or INX D

BEFORE EXECUTION

AFTER EXECUTION

SP

SP

B D H 10

C E L 20

INX H RP=RP+1

B D H 10

C E L

21

1020+1=1021

DCR
Opcode Operand DCR R M Description Decrement register or memory by 1

The contents of register or memory location are decremented

by 1.

The result is stored in the same place. If the operand is a memory location, its address is specified by

the contents of H-L pair. or

Example: DCR B

DCR M

BEFORE EXECUTION

AFTER EXECUTION

A B D H C E L

20

DCR E R=R-1

B
D H

C
E L

19

20-1=19
BEFORE EXECUTION AFTER EXECUTION

H 20

L 50

2050H

21

L
20 50 2050H

DCR M M=M-1

20

21-1=20

DCX
Opcode DCX Operand R Description Decrement register pair by 1

The contents of register pair are decremented by 1.

The result is stored in the same place.

Example: DCX H or DCX B

or DCX D

BEFORE EXECUTION

AFTER EXECUTION
SP

SP

B D H 10

C E L 21

DCX H RP=RP-1

B D H 10

C E L

20

3.Logical Instructions

These instructions perform logical operations on data stored in registers, memory and status flags. The logical operations are:
AND
OR XOR

Rotate
Compare Complement

AND, OR, XOR

Any 8-bit data, or the contents of register, or memory location can logically have
AND operation

OR operation
XOR operation

with the contents of accumulator.

The result is stored in accumulator.

Opcode Operand
ANA R M

Description
Logical AND register or memory with accumulator

The contents of the accumulator are logically ANDed with the contents of

register or memory.

The result is placed in the accumulator.

If the operand is a memory location, its address is specified by the contents

of H-L pair.

S, Z, P are modified to reflect the result of the operation.

CY is reset and AC is set.

Example: ANA B or ANA M.
collected by C.Gokul AP/EEE,VCET

BEFORE EXECUTION CY A B D H AA AC

1010 1010=AAH 0000 1111=0FH 0000 1010=0AH

AFTER EXECUTION CY 0 AC 1

A
B
D H

0A
0F C
E L

10 0F

C E L

ANA B A=A and R

BEFORE EXECUTION 0101 0101=55H 1011 0011=B3H 2050H L 50 B3 0001 0001=11H

AFTER EXECUTION

CY A H 55 20

AC

CY
A H

AC 1
2050H 50 B3

11
20 L

ANA M A=A and M

Opcode Operand Description ANI 8-bit data Logical AND immediate with accumulator
The contents of the accumulator are logically ANDed with the

8-bit data.

The result is placed in the accumulator. S, Z, P are modified to reflect the result.

CY is reset, AC is set.
Example: ANI 86H.

BEFORE EXECUTION

AFTER EXECUTION

1011 0011=B3H 0011 1111=3FH 0011 0011=33H

CY

AC

B3

ANI 3FH A=A and DATA(8)

CY 0 A

AC

33

Opcode

Operand

Description

ORA

R M

Logical OR register or memory with accumulator

The contents of the accumulator are logically ORed with the contents of the

register or memory.
The result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of H-L

pair.
S, Z, P are modified to reflect the result. CY and AC are reset. Example: ORA B or ORA M.

1010 1010=AAH 0001 0010=12H

BEFORE EXECUTION

1011 1010=BAH

AFTER EXECUTION

CY

AC

CY 0

AC

ORA B A=A or R
A B D H AA 12 C E L A B D H BA 12 C E L

0101 0101=55H 1011 0011=B3H

BEFORE EXECUTION

1111 0111=F7H

AFTER EXECUTION

CY

AC

CY

AC

A H

55 20 L

2050H
50

B3

ORA M A=A or M
A H F7 20 L

2050H
50

B3

Opcode Operand ORI 8-bit data

Description Logical OR immediate with accumulator

The contents of the accumulator are logically ORed with the

8-bit data.

The result is placed in the accumulator. S, Z, P are modified to reflect the result.

CY and AC are reset.

Example: ORI 86H.

1011 0011=B3H 0000 1000=08H BEFORE EXECUTION

1011 1011=BBH

AFTER EXECUTION

CY A B3

AC

ORI 08H A=A or DATA(8)

CY 0 A BB

AC 0

Opcode XRA

Operand R M

Description Logical XOR register or memory with accumulator

The contents of the accumulator are XORed with the contents of

the register or memory.

The result is placed in the accumulator.

If the operand is a memory location, its address is specified by the

contents of H-L pair.

S, Z, P are modified to reflect the result of the operation.

CY and AC are reset.

Example: XRA B or XRA M.

BEFORE EXECUTION

1010 1010=AAH 0010 1101=2DH

AFTER EXECUTION

1000 0111=87H

CY A B D H AA 10

AC

CY A

0 87

AC 0

C E L

2D

XRA C A=A xor R

B D H

C E L

2D

BEFORE EXECUTION

0101 0101=55H 1011 0011=B3H

AFTER EXECUTION

1110 0110=E6H

CY A 55

AC

2050H
L 50

B3

XRA M A=A xor M

CY A
H

0 E6
20

AC 0

2050H
L 50

B3

20

Opcode XRI

Operand 8-bit data

Description XOR immediate with accumulator

The contents of the accumulator are XORed with the

8-bit data.
The result is placed in the accumulator. S, Z, P are modified to reflect the result.

CY and AC are reset.

Example: XRI 86H.

1011 0011=B3H 0011 1001=39H BEFORE EXECUTION

1000 1010=8AH

AFTER EXECUTION

CY A B3

AC

XRI 39H A=A xor DATA(8)

CY 0 A 8A

AC 0

Compare

Any 8-bit data, or the contents of register, or memory location can be compares for:
Equality

Greater Than
Less Than

with the contents of accumulator.

The result is reflected in status flags.

Opcode Operand Description CMP R Compare register or M memory with accumulator

The contents of the operand (register or memory) are

compared with the contents of the accumulator.

Both contents are preserved .

BEFORE EXECUTION CY A B D H 10 Z

A>R: CY=0 A=R: ZF=1 A<R: CY=1

AFTER EXECUTION CY A

01 Z
10

10
20

C E L

CMP D A-R
A>M: CY=0 A=M: ZF=1 A<M: CY=1 B8

B
D H 20

C
E L

10<20:CY=01
BEFORE EXECUTION AFTER EXECUTION

CY A H B8 20

Z 2050H L 50

CY

0 A H

ZF
B8 20 L

1
2050H 50 B8

CMP M A-M

B8=B8 :ZF=01

Opcode Operand CPI 8-bit data

Description Compare immediate with accumulator

The 8-bit data is compared with the contents of

accumulator.
The values being compared remain unchanged.

BEFORE EXECUTION

AFTER EXECUTION

A>DATA: CY=0 A=DATA: ZF=1 A<DATA: CY=1

CY A BA Z

CPI 30H A-DATA

CY 0 A BA

AC 0

BA>30 :

CY=00

Rotate

Each bit in the accumulator can be shifted either left or right to the next position.

Opcode RLC

Operand None

Description Rotate accumulator left

Each binary bit of the accumulator is rotated left by one

position. flag.

Bit D7 is placed in the position of D0 as well as in the Carry

CY is modified according to bit D7.

S, Z, P, AC are not affected.

Example: RLC.

BEFORE EXECUTION

CY

B7

B6

B5

B4

B3

B2

B1

B0

AFTER EXECUTION

B7

B6

B5

B4

B3

B2

B1

B0

B7

Opcode Operand RRC None

Description Rotate accumulator right

Each binary bit of the accumulator is rotated right by one

position. flag.

Bit D0 is placed in the position of D7 as well as in the Carry

CY is modified according to bit D0.

S, Z, P, AC are not affected.

Example: RRC.

BEFORE EXECUTION

B7

B6

B5

B4

B3

B2

B1

B0

CY

AFTER EXECUTION

B0

B7

B6

B5

B4

B3

B2

B1

B0

collected by C.Gokul AP/EEE , Velalar college of Engineering and Technology, Erode

Opcode Operand RAL None

Description Rotate accumulator left through carry

Each binary bit of the accumulator is rotated left by one

position through the Carry flag.

Bit D7 is placed in the Carry flag, and the Carry flag is placed

in the least significant position D0.

CY is modified according to bit D7.

S, Z, P, AC are not affected.

Example: RAL.

BEFORE EXECUTION

CY

B7

B6

B5

B4

B3

B2

B1

B0

AFTER EXECUTION

B7

B6

B5

B4

B3

B2

B1

B0

CY

Opcode RAR

Operand None

Description Rotate accumulator right through carry

Each binary bit of the accumulator is rotated right by one

position through the Carry flag.

Bit D0 is placed in the Carry flag, and the Carry flag is placed

in the most significant position D7.

CY is modified according to bit D0.

S, Z, P, AC are not affected.

Example: RAR.

BEFORE EXECUTION

B7

B6

B5

B4

B3

B2

B1

B0

CY

AFTER EXECUTION

CY

B7

B6

B5

B4

B3

B2

B1

B0

Complement

The contents of accumulator can be complemented. Each 0 is replaced by 1 and each 1 is replaced by 0.

Opcode CMA

Operand None

Description Complement accumulator

The contents of the accumulator are complemented.

No flags are affected.

Example: CMA.
BEFORE EXECUTION

A=A
AFTER EXECUTION

A 00

A FF

Opcode

Operand

Description

CMC

None

Complement carry

The Carry flag is complemented.

No other flags are affected.

Example: CMC
BEFORE EXECUTION

=> c=c
AFTER EXECUTION

C 00

C FF

Opcode STC

Operand None Set carry

Description

The Carry flag is set to 1.

No other flags are affected.

Example: STC

CF=1

S-set (1)

C-clear (0)

4.Branching Instructions
The branch group instructions allows the microprocessor to change the sequence of program either conditionally or under certain test conditions.The group includes, (1) Jump instructions, (2) Call and Return instructions, (3) Restart instructions,

Opcode
JMP

Operand
16-bit address

Description
Jump unconditionally

The program sequence is transferred to the memory

location specified by the 16-bit address given in the operand.

Example: JMP 2034 H.

Opcode Jx

Operand 16-bit address

Description Jump conditionally

The program sequence is transferred to the memory

location specified by the 16-bit address given in the operand based on the specified flag of the PSW.
Example: JZ 2034 H.

Jump Conditionally
Opcode Description Status Flags

JC
JNC JZ JNZ JPE JPO

Jump if Carry
Jump if No Carry Jump if Zero Jump if No Zero Jump if Parity Even Jump if Parity Odd

CY = 1
CY = 0 Z=1 Z=0 P=1 P=0

A-Above , B-Below , C-Carry , Z-Zero , P-Parity

Opcode CALL

Operand 16-bit address

Description Call unconditionally

The program sequence is transferred to the memory

location specified by the 16-bit address given in the operand.

Before the transfer, the address of the next instruction after

CALL (the contents of the program counter) is pushed onto the stack.
Example: CALL 2034 .
H

Call Conditionally
Opcode Description Status Flags

CC CNC
CP CM CZ CNZ CPE CPO

Call if Carry Call if No Carry

Call if Positive Call if Minus Call if Zero Call if No Zero Call if Parity Even Call if Parity Odd

CY = 1 CY = 0
S=0 S=1 Z=1 Z=0 P=1 P=0

Opcode Operand RET None

Description Return unconditionally

The program sequence is transferred from the

subroutine to the calling program.

The two bytes from the top of the stack are copied into

the program counter, and program execution begins at the new address.
Example: RET.

Return Conditionally
Opcode Description Status Flags

RC RNC
RP RM RZ RNZ RPE RPO

Return if Carry Return if No Carry

Return if Positive Return if Minus Return if Zero Return if No Zero Return if Parity Even Return if Parity Odd

CY = 1 CY = 0
S=0 S=1 Z=1 Z=0 P=1 P=0

Opcode

Operand

Description

RST

07

Restart (Software Interrupts)

The RST instruction jumps the control to one of eight

memory locations depending upon the number.

These are used as software instructions in a program to

transfer program execution to one of the eight locations.

Example: RST 1

or RST 2 .

Instruction Code RST 0 RST 1

Vector Address 0*8=0000H 1*8=0008H

RST 2
RST 3 RST 4 RST 5 RST 6

2*8=0010H
3*8=0018H 4*8=0020H 5*8=0028H 6*8=0030H

RST 7

7*8=0038H

5. Control Instructions

The control instructions control the operation of microprocessor.

collected by C.Gokul AP/EEE , Velalar college of Engineering and Technology, Erode

Opcode

Operand

Description

NOP

None

No operation

No operation is performed.

The instruction is fetched and decoded but no

operation is executed.
Example: NOP

Opcode Operand HLT None Halt

Description

The CPU finishes executing the current instruction

and halts any further execution.

An interrupt or reset is necessary to exit from the halt

state.
Example: HLT

Opcode

Operand

Description

DI

None

Disable interrupt

The interrupt enable flip-flop is reset and all the

interrupts except the TRAP are disabled.

No flags are affected. Example: DI

Opcode Operand

Description

EI

None

Enable interrupt

The interrupt enable flip-flop is set and all interrupts

are enabled.
No flags are affected. This instruction is necessary to re-enable the

interrupts (except TRAP).

Example: EI

Opcode RIM

Operand None

Description Read Interrupt Mask

This is a multipurpose instruction used to read the

status of interrupts 7.5, 6.5, 5.5 and read serial data input bit.
The instruction loads eight bits in the accumulator

with the following interpretations.

Example: RIM

RIM Instruction

Opcode SIM

Operand None

Description Set Interrupt Mask

This is a multipurpose instruction and used to

implement the 8085 interrupts 7.5, 6.5, 5.5, and serial data output.
The instruction interprets the accumulator contents as

follows.
Example: SIM

SIM Instruction

References
www.slideshare.net www.docstoc.com www.slideworld.com www.nptel.ac.in www.scribd.com http://opencourses.emu.edu.tr/ http://engineeringppt.blogspot.in/ http://www.pptsearchengine.net/ www.4shared.com www.eazynotes.com http://8085projects.info/ Books: Microprocessors and microcontrollers by krishnakanth Microprocessors and microcontrollers by Nagoor Kani

Staff references

8085 microprocessor by Sajid Akram, researcher/lecturer at c.abdul hakeem college of engineering and technology Timingdiagram by puja00 (slideshare.net) Microprocessor 8086 by Gopikrishna Madanan, Assistant Professor of Physics at Collegiate Education, Kerala, India

collected by C.Gokul AP/EEE,VCET