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High-Speed Adder Designs in VLSI

The document discusses different types of high speed adders used in VLSI design, including carry-skip adders, carry-select adders, and carry-save adders. Carry-skip adders detect when the carry-in can be passed directly to the next block to speed up operation. Carry-select adders split the addition problem into smaller groups to use multiple narrow adders. Carry-save adders are based on full adders acting as reduction networks and avoid carry delays, making them faster than normal adders.

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Tamil Selvan
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234 views15 pages

High-Speed Adder Designs in VLSI

The document discusses different types of high speed adders used in VLSI design, including carry-skip adders, carry-select adders, and carry-save adders. Carry-skip adders detect when the carry-in can be passed directly to the next block to speed up operation. Carry-select adders split the addition problem into smaller groups to use multiple narrow adders. Carry-save adders are based on full adders acting as reduction networks and avoid carry delays, making them faster than normal adders.

Uploaded by

Tamil Selvan
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© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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HIGH SPEED ADDERS

NAME : TAMILSELVAN.R DEPT. : M.E. VLSI DESIGN(1ST YEAR) SUBJECT : VLSI DESIGN TECHNIQUES DATE : 16.11.2013

HIGH SPEED ADDERS


CARRY-SKIP ADDERS CARRY-SELECT ADDERS

CARRY-SAVE ADDERS

Carry-Skip Adder is also called as Carry-bypass Adder To speed up operation, propagation is skipped to position i without waiting for rippling

Carry-skip logic is added to each block to detect when carry-in the block can be passed directly to the next block

If each block is 4bits, Group carry propagate signal is P(i+3:i)=Pi+(3Pi+2Pi+Pi) Carry out of this group is Cout= Ci+4+P(i+3:i)Ci
Where, Ci is Carry in Performance of Carry-Skip Adder is calculated by number of bits in each group N bit adder using n.k bit groups tskip=tpg+2(n-1)+(k-1)tAO+ txor

Use multiple narrow adders to create fast wide adders

Consider thee addition two n bit numbers

a=an-1...a0 and b=bn-1b0

At the bit level, the adder delay increases from least significant 0-th position upward, with (n-1)th requiring the most complex logic

Carry-Select adder break the addition problem into smaller groups.

By splitting n-bit problem into two n/2 bit sections.

Higher order groups adds word segments an-1an/2 and bn-1.bn/2 The carry out cn/2 produced by the sum of lower order word segments a(n/2)-1a0 and b(n/2)-1b0 Only two possibilities off carry bit cn/2=0 and cn/2=1 Use two 4 bit adder on upper words, one for each possibility, Mux is used to valid result

Example:

The carry bit C4 from the adder L is used as Mux select signal(Fig:12.35) If, C4=0, the result of U0 sent to output C4=1, the result of U1 sent to output Advantage:

The Speed of operation is high

Dis Advantage:
Cost is high High area consumption

Carry Save Adder(CSA) based on the idea of Full

Adder(FA)

Full Adder has three inputs and two outputs

FA is used as 3-2 reduction network(Fig 12.36)


We can build n-bit Carry save adder by using n separate adders

Carry save adder useful in need to add more than 2


numbers

Avoids delay in carry out bits Faster than the normal adders

Example:

This starts with 7 n-bit words(a, b, c,g) Use 5 Carry Save Adders to reduce it down to 2 words Carry propagate adder used to add the final sum of these two words

1.

2.

3.

Introduction to VLSI Circuits and Systems by John P. Uyemura, 2002. Introduction to VLSI Systems A Logic Circuit and System Perspective by Ming-Bo Lin CMOS VLSI Design, A Circuits and Systems Perspective 3rd Edition by Neil H. E. Weste

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