0 Course Logistics Contents
1) Topics 2) Course outline & Evaluation Strategy 3) References 4) Homework Problems(#1, 2, 3) and term projects
5) Exam : Problems & answers
6) Etc.
Introduction to VLSI Lecture_1 #1
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Introduction to VLSI
Lecture_1 #2
1) Topics(# of course units)
EE573 Introduction to VLSI Systems
Lecture #1 : 0. Course Logistics Lecture #1 : 1. Motivation & Objectives(1) Lecture #2 : 2. ASIC Design Methodology(2) Lecture #3-6 : 3. Process & Device Physics(3) Lecture #7-9 : 4. Circuit Characterization(3) Lecture #10-15 : 5. CMOS Logic Basics(5) Lecture #18 : 12. Special topic 1:(1) Lecture #19-22 : 7. Memory Subsystem(3.5) Lecture #23-24 : 8. Timing Issues(2) Lecture #25-26 : 9. Interconnects(2) Lecture #27 : 11. Low Power Techniques(1) Lecture #28 : 10. Testing(1)
Lecture #16-17 : 6. ALU Blocks & Control(3.5) Exam. (2) Total
Introduction to VLSI
(31)
Lecture_1 #3
2) Course Outline and Evaluation Strategy
1. Lecturer : Prof. Chong-Min Kyung( ), Dept. Electrical Eng. KAIST 2. Teaching Assistants : Y.S.Chang & B.I.Park Tel:866-0848(05-848) 3. Web site : http://sonata.kaist.ac.kr/~kyung/ Students are encouraged to preview the lecture note from the web site : it will be available at least one week before the lecture. 4. Evaluation(each 25%) 1) Home work : issued every Wednesday, due next Wed.(25%) 2) Term Project : design of circuit or modules/CAD algorithm or tools(25%) 3) Mid-term Exam(25%) 4) Final Exam(25%)
Introduction to VLSI
Lecture_1 #4
3) References(in the order of expected frequency of reference)
1. Jan. M. Rabaey, Digital Integrated Circuits ; A Design Perspective, Prentice-Hall, 1996 2. Michael J. S. Smith, Application-Specific Integrated Circuits, Addison Wesley, 1997 3. Neil H. E. Weste & Kamran Eshraghian, Principles of CMOS VLSI Design ; A Systems Perspective, Addison Wesley, 1992 4. Gary K. Yeap. Practical Low Power Digital VLSI Design, Kluwer, 1998 5. , VLSI , 1993 6. H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI, Addison Wesley, 1990 7. SIA, National Technology Roadmap for Semiconductors, 1997
Introduction to VLSI
Lecture_1 #5
1 Motivation and Objectives
Contents
1) Historical Perspective
Change of Human Life & Major Industry
History of IC Development
Korean History
2) Role of ICs in present & future 3) SIA Technology Roadmap 4) Future Challenges
Introduction to VLSI Lecture_1 #6
1) Historical Perspective
Change of Human Life & Major Industry Phase I
Major Industry Hunting, Fishing Cattle Breeding Agriculture
?
Phase Duration(years) 104~103 (several thousand years)
Phase II
Achievement Feeding Stable Feeding Stable Feeding
Phase III
Activity Domain raw material(m) domesticated m domesticated m m deformation (with energy) new material & new energy Information, idea
Lecture_1 #7
II
103~102 Machinery Mass Production (several hundred years) Chemistry, Nuclear Environment Pollution 102~ ? (several ten years?) Electronics Information Control, Computing and Communication
III
Introduction to VLSI
Questions thereof
Between phase I&II, how much mass is needed to store/produce some energy, E ? 2
E = mc (Einstein)
Between phase II&III, the question is, how much energy is needed to store/transmit/transform some information, I ?
E = ln I(Shannon)
What is the bottleneck(most limiting resource) in information age, among(Mass, Energy and Idea) ?
I = exp(energy, mass, or population)
Amount of information is proportional to exp(population), and so is value of idea. Probability of coming up with the best idea is exp-1 (population).
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History of IC Development
Mechanical Computing Device 1642, Pascal : Counter Wheel Calculator for(+, -)
) 1671, Leibniz : Counter Wheel for(+, -) and Chain & Pulley for( ,
1823, Babbage : Difference Engine for Table Construction using Finite Difference
1834, Babbage : Analytical Engine performing four operations, conditional branch.
Mill (ALU) Operation Cards ) (+, -, , Program
Introduction to VLSI Lecture_1 #9
data
Store (Counter Wheels)
Card Punch
instructions Variable Cards
Electromechanical Computing Device(magnetic relay & wheels)
1941, Zuse : first operational general-purpose computer 1944, Aiken : Harvard Mark I(3 sec for 10-digit multiplication)
Electronic Computers(vacuum tubes)
1943-1946, Maughly & Eckert : ENIAC(for computing artillery trajectory)
18,000 tubes, 30 tons
decimal(rather than binary) computing using one hot coding (10 vacuum tubes for one digit number) reliability, power consumption problems
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Bipolar Transistor
before 1947 : semiconductor used only for thermistors, photodiode, and rectifiers 1948, Bardeen & Brattain : point-contact transistor 1949, Schockley : Junction diode and Bipolar Junction Transistor(BJT) theory published
MOSFET(IGFET, MISFET)
1930, Lilienfeld & Heil : proposed the principle 1960, Kahng( ) & Atalla : first demo. of MOSFET (Silicon planar process)
Logic gate
1956, Harris : bipolar digital logic gate 1960, Fairchild, Inc : commercial logic gate IC(Fairchild Micrologic) 1962, Beeson : TTL(Transistor-Transistor Logic) 1974, Masaki : ECL(Emitter-Coupled Logic) 1972, Hart : I2L(Integrated-Injection Logic)
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Microprocessor & Memories(Technology Leader & Champion Product)
1972, Intel : 4004 microprocessor 1974, Intel 8080 1970, Hoff : 4 kbit MOS memory
CMOS technology
Weimer patent on CMOS flip-flop(1962 filed-1965 issued)
Wanlass(Fairchild) Patent on CMOS concept & inverter, NAND and NOR gates
CMOS initially used only for low-power applications such as wrist watch chip, due to process & area overhead CMOS acceptance widened as VLSI era comes in to solve the power consumption problem.
Others : BiCMOS, GaAs, SiGe, Superconducting, etc.
Introduction to VLSI
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Korean IC History
~ 1960 : Signetics, Fairchild, Motorola Korea, Anam : IC assembly 1972 : (:) by Applewine Paradise, Inc. Sold to Samsung in 1976 ; Produced CMOS Watch Chips ~ 1970 : KIST () ; moved to , KIET in 1978(?) 1975 : KAIST () 1976 : ; sold to ; merged KIET facility in Kumi in 1980(?) 1983. 12 : Samsung developed 64K DRAM with Microns mask 1985 : Hyundai joined DRAM race with , LG 1993-1995 : All three highly profitable due to good DRAM market. 1995/2H : DRAM price fall begins. Now : System industries as well as semiconductor industries rely on non-memory IC for their future.
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2) Role of ICs in Present & Future
Product value is mostly increased by putting more idea, rather than mass, or energy, recently.
mass
idea energy
() : 100 20
100 : 1Km/liter
now : 20Km/liter
Battery( charge storage efficiency ) : 5 - 8 fold improvement in 200 years
200 years ago : 25 W.H/Kg (Lead)
30 years ago : 50 W.H/Kg (NiCd) 125 W.H/Kg (Alkaline) 10 years later : 200 W.H/Kg (Lithium Polymer)
Introduction to VLSI Lecture_1 #14
Semiconductor IC technology
CPU speed : 100-fold increase in 10 years Memory storage density : 4-fold increase in every 3 years
IC is the most efficient means for the storage(memory), processing(ASIC, processor), and transmission(communication chip) of information. Ever more intelligence is being put into almost all things :
Car : from mechanical stuff, to a system with various control, computing, communication occurring within .
Building : from a chunk of steel-concrete, to a system with various control,
computing, communication occurring within. People : equipped with various monitoring, computing, communicating and actuating device connected via wireless human body network(?)
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IC performs information processing being connected with other ICs through interconnection within a Board, and possibly running software downloaded from a memory module. Board
CHIP #2
CHIP #1
CHIP #3
Memory (SW)
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IC Design Environment
System Specification & Verification
Interconnection
IC ( Hardware )
Software
CAD
Library
Device & Int. model
Process Integration
Material Lithography
Introduction to VLSI
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3) 1997 SIA Technology Roadmap
Semiconductor Industry Association initiative version 1992, 1994 & 1997 objective :
Setting up goals for the future work and effort of each technologist(equipment manufacturer, material provider, process integration experts, CAD & test expert, etc) to maintain the growth rate based on Moores law.
Seven Focus TWGs
From Cross-out TWGs
Design & Test Process Integration, Device & Structures Front End Process Lithography Interconnect Factory Integration Assembly & Packaging
ESH(Environment, Safety and Health) Defect reduction Metrology Modeling & Simulation
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Roadmap Technology Characteristics 1/4
Year DRAM Half-pitch(nm) MPU Gate Length(nm) DRAM samples DRAM production DRAM bits/cm2
1997 250 200 256M
1999 180 140 1G
2001 150 120
2003 130 100 4G
2006 2009 100 70 70 50
2012 50 35 256G 64G 17B
16G 64G 4G 4G
64M 256M
1G
1G
96M 270M 380M 770M 2.2B 6.1B
High-Vol. Logic transistors/cm2
ASIC Usable transistors/cm2
3.7M 6.2M 10M
8M 14M 16M
18M
24M
39M 84M 180M
40M 64M 100M
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Roadmap Technology Characteristics 2/4
Year
Number of Chip I/Os( high perf.) Number of Chip I/Os( low cost)
1997 1999 2001 2003 2006 2009 2012
1450 2000 800 975 2400 1195 3000 1460 4000 5400 7300 1970 2655 3585
Number of Package Pins/Balls(P)
Number of Package Pins (ASIC) On-chip local clock(MHz)
600
1100 750
810
1500 1250
900
1800 1500
1100
2200 2100
1500 2000 2700
3000 4100 5500 3500 6000 10000
Chip to board(off-chip) clock(MHz) reduced-width, multiplexed bus
Chip to board(off-chip) clock(MHz) peripheral buses
750
250
1200 1400 1600 2000 2500 3000
480 785 885 1035 1285 1540
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Roadmap Technology Characteristics 3/4
Year
Chip Size(DRAM) mm2 Chip Size(Microprocessor) mm2 Chip Size(ASIC)[max litho field ]
1997 1999 2001 2003 2006 2009 2012
280 300 480 400 340 800 445 385 850 560 430 900 790 520 1000 1120 620 1100 1580 750 1300
Lithographic Field Size(mm2)
22x22 25x32 25x34 25x36 25x40 25x44 25x52 484 800 850 900 1000 1100 1300 6 6-7 7 7 7-8 8-9 9
Maximum Number Wiring Levels
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Roadmap Technology Characteristics 4/4
Year Minimum mask count Substrate Diameter(mm2) Bulk or epitaxial or SOI wafer Power Supply, Vdd(V)
Max. Power High-performance with heat sink(W)
1997 22 200
1999 22/24 300
2001 23 300
2003 24 300
2006 24/26 300
2009 26/28 450
2012 28 450
1.8-2.5 1.5-1.8 1.2-1.5 1.2-.15 0.9-1.2 0.6-0.9 0.5-0.6 70 1.2 90 1.4 110 1.7 130 2.0 160 2.4 170 2.8 175 3.2
Max Power Battery(W)--(Hand-held)
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Resources for addressing the Roadmap(ex:litho.)
Year pitch(nm) Solutions Risk
1997 250 DUV existing limited
1999 180 DUV
2001 150 DUV few moderate
2003 130
2006 100 no known high
EUV, E-beam, Ion-beam Prox. X-ray
Industry internal industry coop. R&D fund sematech
SRC & university
Federal program production integration development
Introduction to VLSI
focus centers research
Lecture_1 #23
4) Grand Challenges
Ability to continue scaling according to Moores law
( new material, technologies, approaches must be invented )
Lithography below 100nm
No materials exist that are optically transparent for <= 193nm through-the-lens exposure scheme impossible totally new scheme needed high conductivity interconnection (copper) low- dielectric good contact material
New materials and structures
similarly for packaging
GHz frequency operation
10 GHz : = 3cm comparable to chip size (treating circuit & packaging as a whole)
Metrology and test R & D challenge (due to down-sizing)
Introduction to VLSI Lecture_1 #24
