Microcomputer
Microcomputer
Microcomputer
microcomputer
What is Microcomputer?
A microcomputer is a general purpose system; i.e.; the system is organized in such a way that it can perform a large variety of computation.
microcomputer
microcomputer
Processor
Memory Subsystem
I/O Subsystem
I/O devices
microcomputer
microcomputer
Processor
It is the computing engine of the microcomputer; it executes the sequence of instructions i.e.. the program. it is also known as Central Processing Unit.
microcomputer
Memory Subsystem
It stores the program as well as the data used by the program. The memory is divided into locations, such as bytes and words; these locations are identified by their address.
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Memory operations
Read: the processor provides the address and receives the data read from the location addressed. Write: the processor provides both address and the data to be stored at the corresponding location.
microcomputer
I/O subsystem
It contains the interface to devices that allow transferring data input to/ from the computer.
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Read 0
0 1
Write 0
1 0
Enable 0
1 1
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Architecture of ALU
architecture alu of alu is begin aluproc: process (a, b, sel) begin
case sel is
when alupass => c <= a after 1 ns; when andOp => c <= (a and b) after 1 ns;
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Architecture..
when orOp => c <= a or b after 1 ns; when xorOp => c <= a xor b after 1 ns; when notOp => c <= not a after 1 ns;
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Architecture..
when plus => c <= a + b after 1 ns; when alusub => c <= a - b after 1 ns; when inc => c <= a + "0000000000000001" after 1 ns;
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Architecture..
when dec => c <= a - "0000000000000001" after 1 ns; when zero => c <= "0000000000000000" after 1 ns; when others => c <= "0000000000000000" after 1 ns;
end case;
end process; end alu;
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Package( work.pack.all)
Package used in ALU library IEEE; use IEEE.STD_LOGIC_1164.all; package pack is type opcode is (alupass ,andop ,orop ,xorop ,notop ,plus ,alusub ,inc ,dec ,zero); function "+"(opd1,opd2:std_logic_vector( 15 downto 0))return std_logic_vector; function "-"(opd1,opd2:std_logic_vector(15 downto 0))return std_logic_vector; end package;
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Package Body(work.pack.all)
package body pack is function "+"(opd1,opd2:std_logic_vector( 15 downto 0))return std_logic_vector is variable sum:std_logic_vector(15 downto 0); variable carry:std_logic:='0'; begin for i in 15 downto 0 loop sum(i):= opd1(i) xor opd2(i)xor carry; carry:= (opd1(i) and opd2(i))or(opd2(i) and carry)or (opd1(i) and carry); end loop; return sum; end function;
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Package Body(work.pack.all)..
function "-"(opd1,opd2:std_logic_vector( 15 downto 0))return std_logic_vector is variable diff:std_logic_vector( 15 downto 0); variable borrow:std_logic:='0'; begin for i in 15 downto 0 loop diff(i):= opd1(i) xor opd2(i)xor borrow; borrow:= ( (not opd1(i)) and borrow)or((not opd1(i))and opd2(i) )or (opd2(i) and borrow); end loop; \ return diff; end function; end pack;
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Simulation
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