Flynns Classification Of Computer

Architectures
In 1966, Michael Flynn proposed a classification for
computer architectures based on the number of
instruction steams and data streams (Flynns
Taxonomy).
Flynn uses the stream concept for describing a
machine's structure
A stream simply means a sequence of items (data or
instructions).
The classification of computer architectures based on
the number of instruction steams and data streams
(Flynns Taxonomy).

Flynns Taxonomy
SISD: Single instruction single data
Classical von Neumann architecture
SIMD: Single instruction multiple data
MISD: Multiple instructions single data
Non existent, just listed for completeness
MIMD: Multiple instructions multiple data
Most common and general parallel machine
Flynn Classification Of
Computer architectures
SISD
SISD (Singe-Instruction stream, Singe-Data
stream)
SISD corresponds to the traditional mono-
processor ( von Neumann computer). A single
data stream is being processed by one
instruction stream OR
A single-processor computer (uni-processor) in
which a single stream of instructions is
generated from the program.
SISD
where CU= Control Unit, PE= Processing Element,
M= Memory
SIMD
SIMD (Single-Instruction stream, Multiple-
Data streams)
Each instruction is executed on a different set
of data by different processors i.e multiple
processing units of the same type process on
multiple-data streams.
This group is dedicated to array processing
machines.
Sometimes, vector processors can also be seen
as a part of this group.
SIMD
where CU= Control Unit, PE= Processing Element,
M= Memory
MISD
MISD (Multiple-Instruction streams, Singe-
Data stream)
Each processor executes a different sequence
of instructions.
In case of MISD computers, multiple
processing units operate on one single-data
stream .
In practice, this kind of organization has never
been used
MISD
where CU= Control Unit, PE= Processing Element,
M= Memory
MIMD
MIMD (Multiple-Instruction streams,
Multiple-Data streams)
Each processor has a separate program.
An instruction stream is generated from each
program.
Each instruction operates on different data.
This last machine type builds the group for the
traditional multi-processors. Several
processing units operate on multiple-data
streams.
MIMD Diagram
Processor Organizations

Computer Architecture Classifications

Single Instruction, Single Instruction, Multiple Instruction Multiple Instruction
Single Data Stream Multiple Data Stream Single Data Stream Multiple Data Stream
(SISD) (SIMD) (MISD) (MIMD)


Uniprocessor Vector Array Shared Memory Multicomputer
Processor Processor (tightly coupled) (loosely coupled)

12
Organization of Multiprocessor
Systems
Flynns Classification
Was proposed by researcher Michael J. Flynn in 1966.
It is the most commonly accepted taxonomy of computer
organization.
In this classification, computers are classified by whether it
processes a single instruction at a time or multiple
instructions simultaneously, and whether it operates on one
or multiple data sets.
13
Taxonomy of Computer
Architectures
4 categories of Flynns classification of multiprocessor
systems by their instruction and data streams
Simple Diagrammatic Representation
14
Single Instruction, Single Data
(SISD)
SISD machines executes a single instruction on
individual data values using a single processor.
Based on traditional Von Neumann uniprocessor
architecture, instructions are executed sequentially or
serially, one step after the next.
Until most recently, most computers are of SISD
type.
15
SISD


Simple Diagrammatic Representation


16
Single Instruction, Multiple Data
(SIMD)
An SIMD machine executes a single instruction on
multiple data values simultaneously using many
processors.
Since there is only one instruction, each processor
does not have to fetch and decode each instruction.
Instead, a single control unit does the fetch and
decoding for all processors.
SIMD architectures include array processors.
17
SIMD


Simple Diagrammatic Representation


18
Multiple Instruction, Multiple
Data (MIMD)
MIMD machines are usually referred to as
multiprocessors or multicomputers.
It may execute multiple instructions simultaneously,
contrary to SIMD machines.
Each processor must include its own control unit that
will assign to the processors parts of a task or a
separate task.
It has two subclasses: Shared memory and distributed
memory
19
MIMD
Simple Diagrammatic Representation
(Shared Memory)
Simple Diagrammatic
Representation(DistributedMemory)
20
Multiple Instruction, Single Data
(MISD)
This category does not actually exist. This
category was included in the taxonomy for the
sake of completeness.
21
Flynns Taxonomy
Flynn classified by data and control streams in 1966






SIMD Data Level Parallelism
MIMD Thread Level Parallelism
MIMD popular because
Flexible: N pgms and 1 multithreaded pgm
Cost-effective: same MPU in desktop & MIMD
Single Instruction Single
Data (SISD)
(Uniprocessor)
Single Instruction Multiple
Data SIMD
(single PC: Vector, CM-2)
Multiple Instruction Single
Data (MISD)
(????)
Multiple Instruction Multiple
Data MIMD
(Clusters, SMP servers)
Instruction and Data Streams
An alternate classification
Data Streams
Single Multiple
Instruction
Streams
Single SISD:
Intel Pentium 4
SIMD: SSE
instructions of x86
Multiple MISD:
No examples today
MIMD:
Intel Xeon e5345
SPMD: Single Program Multiple Data
A parallel program on a MIMD computer
Conditional code for different processors
SIMD
Operate element wise on vectors of data
E.g., MMX and SSE instructions in x86
Multiple data elements in 128-bit wide registers
All processors execute the same instruction at
the same time
Each with different data address, etc.
Simplifies synchronization
Reduced instruction control hardware
Works best for highly data-parallel
applications

Vector Processors
Highly pipelined function units
Stream data from/to vector registers to units
Data collected from memory into registers
Results stored from registers to memory
Example: Vector extension to MIPS
32 64-element registers (64-bit elements)
Vector instructions
lv, sv: load/store vector
addv.d: add vectors of double
addvs.d: add scalar to each element of vector of double
Significantly reduces instruction-fetch bandwidth
Vector vs. Scalar
Vector architectures and compilers
Simplify data-parallel programming
Explicit statement of absence of loop-carried
dependences
Reduced checking in hardware
Regular access patterns benefit from interleaved
and burst memory
Avoid control hazards by avoiding loops
More general than ad-hoc media extensions
(such as MMX, SSE)
Better match with compiler technology