The 8051 Assembly

Language

Overview
Addressing modes
Data transfer instructions
Data processing (arithmetic and logic)
Program flow instructions

Addressing Modes
Immediate Mode specify data by its
value
mov a, #0
;put 0 in the accumulator
a = 00000000
mov a, #0x11
; put 11hex in the accumulator
a = 00010001
mov a, #11
; put 11 decimal in accumulator
a = 00001011
mov a, #77h
; put 77 hex in accumulator
a = 01110111
Mov P1,#55h
; put 55 hex in port 1
P1= 01010101

Addressing Modes
Register Addressing
either source or destination is one of R0R7
Ex: mov R0, a
mov a, R0
source & destination operands must match
same size
EX: mov a, dptr
dptr is a 16-bit register and A is 8-bit register
MOV R1,R2 (is invalid)

Addressing Modes
Direct Mode specify data by its 8-bit address
mov a, 0x70
or
Mov a,70h

; copy contents of RAM at 70h to a

Addressing Modes
Direct Mode specify data by its 8-bit
address
Ram

location 00-07h are used for Bank 0

Regs R0-R7

Ex:
Mov a,4;
mov R2,#5
or
mov a,2
Mov a,R4;
mov b,2
mov 2,7
(copying data from R2 to R7)
Since mov R2,R7 is invalid

Addressing Modes
Register Indirect the address of the source or
destination is specified in registers.
Use only registers R0 or R1 for 8-bit address:
R2 R7 cant use for storing the address
mov
mov
mov
;

psw,#0
; use register bank 0
r0,#3C
@r0,#3
; memory at 3C gets #3
M[3C] 3

Uses DPTR register for 16-bit addresses:

mov dptr, #0x9000
; dptr 9000h
movx a, @dptr ; a M[9000]
Note that 9000 is an address in external data memory

Addressing Modes
Ex:
mov R0,50
mov R0,#50h
Here 50 is address location in
Here 50 is data is
loaded in R0
RAM
mov a,@R0
mov a,R0
Copy the content of data where content of R0 will
be copied in
Address is loaded in R0
Accumulator Register
a=[50]

a=50h

Addressing Modes
Indexed Mode source or destination
address is the sum of the base address and
the accumulator.
Accessing data from ROM(internal/external)
Base address can be DPTR or PC
mov dptr, #4000h
mov a, #5

movc

a, @a + dptr ;a M[4005]

Stacks
push

pop

stack pointer
stack

Go do the stack exercise..

PUSH and POP the

Stack
SP+
3
SP+
2
SP+
1

PUSH Y
PUSH X

INCREMENTING
BEFORE PUSHing

SP

POP Y
POP X

INTERNAL RAM

SP
SP1
SPDECEREMENT
2

AFTER POPing

Bit Addressable Memory

2F

7F

78

2E
2D
2C

Bit addressing:
mov C, 1Ah
or
mov C, 23h.2

2B
2A
29
28
27
26
25
24
23

1
A

22

10

21
20

20h 2Fh (16 locations X

8-bits = 128 bits)

0F
07

08
06

05

04

03

02

01

00

Special Function Registers

SPRs that are Bit

Addressable
SPRs with
addresses of
multiples of 0 and
8 are bit
addressable.
Notice that all 4
parallel I/O ports
are bit
addressable.

Address

SFRs
Pink are
implemented in
enhanced
C8051F020

Register

0xF8

SPI0CN

0xF0

0xE8

ADC0CN

0xE0

ACC

0xD8

PCA0CN

0xD0

PSW

0xC8

T2CON

0xC0

SMB0CN

0xB8

IP

0xB0

P3

0xA8

IE

0xA0

P2

0x98

SCON

0x90

P1

0x88

TCON

0x80

P0

Data Transfer Instructions

MOV dest, source

dest source

6 basic types:
MOV a, byte
MOV Rn, byte
MOV direct, byte
MOV @Rn, byte
MOV DPTR, data16

;move byte to accumulator

;move byte to register of
;current bank
;move byte to internal RAM
;move byte to internal RAM
;with address contained in Rn
;move 16-bit data into data
;pointer

Other Data Transfer

Instructions
Stack instructions
PUSH byte
;move byte
POP byte
;decrement

;increment stack pointer,

on stack
;move from stack to byte,
stack pointer

Exchange instructions
XCH a, byte ;exchange accumulator and
;byte
XCHD a, byte ;exchange low nibbles of
;accumulator and byte

Arithmetic Instructions

Add

Mnemonic

Description

Subtract

ADD A, byte

add A to byte, put result in A

ADDC A, byte

add with carry

Increment

SUBB A, byte

subtract with borrow

INC A

increment A

Decremen
t

INC byte

increment byte in memory

INC DPTR

increment data pointer

DEC A

decrement accumulator

Multiply

DEC byte

decrement byte

MUL AB

multiply accumulator by b register

Divide

DIV AB

divide accumulator by b register

DA A

decimal adjust the accumulator

Decimal

Logic Instructions
Bitwise logic operations (AND, OR, XOR,
NOT)
Clear
Rotate
Swap
Logic instructions do NOT affect the flags in
PSW

Bitwise Logic
ANL AND
ORL OR
XRL eXclusive OR
CPL Complement

Examples:

00001111
ANL 10101100
00001100

ORL

00001111
10101100
10101111

XRL

00001111
10101100
10100011

CPL

10101100
01010011

Other Logic Instructions

CLR clear
RL rotate left
RLC rotate left through Carry
RR rotate right
RRC rotate right through Carry
SWAP swap accumulator nibbles

CLR Set all bits to 0

CLR
CLR
CLR
CLR

A
byte
Ri
@Ri

(direct mode)
(register mode)
(register indirect mode)

Rotate
Rotate instructions operate only on a
rl a
mov a, #0xF0
rl a

; a 11110000
; a 11100001

Rotate through Carry

rrc a

mov a, #0A9h
add a, #14h
rrc a

; a A9
; a BD (10111101), C0
; a 01011110, C1

Swap
swap a

mov a, #72h
swap a

; a 27h

Bit Logic Operations

Some logic operations can be used with
single bit operands
ANL C, bit
ORL C, bit
CLR C
CLR bit
CPL C
CPL bit
SETB C
SETB bit

ANL C, /bit
ORL C, /bit

bit can be any of the bit-addressable RAM

locations or SFRs.

Rotate and
Multiplication/Division
Note that a shift left is the same as
multiplying by 2, shift right is divide by
2
mov
clr
rlc
rlc
rrc

a, #3 ; A 00000011 (3)
C ; C 0
a ; A 00000110 (6)
a ; A 00001100 (12)
a ; A 00000110 (6)

Program Flow Control

Unconditional jumps (go to)
Conditional jumps
Call and return

Unconditional Jumps
SJMP <rel addr>

Short jump, relative

address is 8-bit 2s complement number, so jump can
be up to 127 locations forward, or 128 locations back.

LJMP <address 16> ;

Long jump

AJMP <address 11> ;

Absolute jump to
anywhere within 2K block of program memory

JMP @A + DPTR

Long indexed jump

Infinite Loops

Start: mov C, p3.7

mov p1.6, C
sjmp Start
Microcontroller application programs are almost always infinite loops!

Conditional Jumps
These instructions cause a jump to occur
only if a condition is true. Otherwise,
program execution continues with the
next instruction.

loop: mov a, P1
jz loop ; if a=0, goto loop,
;else goto next
;instruction
mov b, a

Conditional jumps
Mnemonic
JZ <rel addr>
JNZ <rel addr>
JC <rel addr>
JNC <rel addr>
JB <bit>, <rel addr>
JNB <bit>,<rel addr>
JBC <bir>, <rel addr>
CJNE A, direct, <rel
addr>

Description
Jump if a = 0
Jump if a != 0
Jump if C = 1
Jump if C != 1
Jump if bit = 1
Jump if bit != 1
Jump if bit =1, clear
bit
Compare
A
and
memory, jump if not
equal

Conditional Jumps for

Branching
if condition is true

condition
false

goto label

else
goto next
instruction

if a = 0 is true
send a 0 to LED

else
send a 1 to LED

true
label

jz led_off
setb C
mov P1.6, C
sjmp skipover
led_off: clr C
mov P1.6, C
skipover: mov A, P0

More Conditional Jumps

Mnemonic

Description

CJNE A, #data <rel addr>

Compare A and data,

jump if not equal

CJNE Rn, #data <rel addr>

Compare Rn and data,

jump if not equal

CJNE @Rn, #data <rel addr>

Compare data in Rn
and memory, jump if
not equal

DJNZ Rn, <rel addr>

Decrement Rn and then

jump if not zero

DJNZ direct, <rel addr>

Decrement memory and

then jump if not zero

Iterative Loops
For A = 0 to 4 do
{}

For A = 4 to 0 do
{}

clr a
loop: ...
inc a
cjne a, #4, loop

mov R0, #4
loop: ...
...
djnz R0, loop

Call and Return

Call is similar to a jump, but
Call instruction pushes PC on stack
before branching
acall <address ll>

; stack PC
; PC address 11

lcall <address 16>

; stack PC
; PC address 16

Return
Return is also similar to a jump, but
Return instruction pops PC from stack to
get address to jump to
ret

; PC stack

Subroutines
call to the subroutine

Main:

...
acall sublabel
...
...
sublabel:...
the subroutine
...
ret

Initializing Stack Pointer

The Stack Pointer (SP) is initialized to 0x07.
(Same address as R7)
When using subroutines, the stack will be used to
store the PC, so it is very important to initialize
the stack pointer. Location 2F is often used.

mov SP, #0x2F

Why Subroutines?
Subroutines allow us to have "structured"
assembly language programs.
This is useful for breaking a large design
into manageable parts.
It saves code space when subroutines
can be called many times in the same
program.