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ECE2030 Introduction To Computer Engineering Lecture 13: Building Blocks For Combinational Logic (4) Shifters, Multipliers

This document discusses shifters and multipliers in computer engineering. It begins by explaining logical and arithmetic shifting operations and how they are implemented using multiplexers. It then covers different designs for shifters, including 4-bit logical and arithmetic shifters, rotators, and barrel shifters. The document also discusses unsigned and signed binary multiplication and different multiplier designs like array multipliers and carry-save multipliers.

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68 views30 pages

ECE2030 Introduction To Computer Engineering Lecture 13: Building Blocks For Combinational Logic (4) Shifters, Multipliers

This document discusses shifters and multipliers in computer engineering. It begins by explaining logical and arithmetic shifting operations and how they are implemented using multiplexers. It then covers different designs for shifters, including 4-bit logical and arithmetic shifters, rotators, and barrel shifters. The document also discusses unsigned and signed binary multiplication and different multiplier designs like array multipliers and carry-save multipliers.

Uploaded by

Jbanful
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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ECE2030

Introduction to Computer Engineering


Lecture 13: Building Blocks for
Combinational Logic (4) Shifters,
Multipliers
Prof. Hsien-Hsin Sean Lee
School of Electrical and Computer Engineering
Georgia Tech

Basic Shifting
Shift directions
Left (multiply by 2)
Right (divide by 2)
Take floor value if the result is not an integer
Floor value of X (or X ) is the greatest
integer number less than or equal to X, E.g.
5/2 = 2
-3/2 = -2

Shift types
Logical (or unsigned)
Arithmetic (or signed)

Logical Shift
Shift Left
MSB: Shifted out
LSB: Shifted in with a 0
Examples:
(11001011 << 1) = 10010110
(11001011 << 3) = 01011000

Shift right
MSB: Shifted in with a 0
LSB: Shifted out
Examples: (Some ISA use triple > for logical right
shift)
(11001011 >>> 1) = 01100101
(11001011 >>> 3) = 00011001

Arithmetic Shift
Shift left
MSB: Shifted out, however, be aware of
overflow/underflow
LSB: Shifted in with a 0
Examples:
(1100 << 1) = 1000
(1100 << 3) = 0000 (Incorrect!) Underflow

Shift right
MSB: Retain sign bit
LSB: Shifted out
Examples:
(1100 >> 1) = 1110 (Retain sign bit)
(1100 >> 3) = 1111 ( -4/8 = -1 ) Floor value of -0.5

Examples of Arithmetic Shift


1111 1011

Arithmetic shift right by 1

1111 1101
1111 1011

Arithmetic shift left by 1

1111 0110
1011 1111 (= -65) Arithmetic shift left by 1 (i.e. x2)
0111 1110 (= +126 -130) Underflow !
Overflow/Underflow

0100 0010 (= +66) Arithmetic shift left by 1 (i.e. x2)


1000 0100 (= -124 +132) Overflow !

4-bit Logical Shifter

A3
S/NS

S1

L/R

S0

D3

A2

D2

A1

D1

A0

S1

S0

D3

D2

D1

D0

A3

A2

A1

A0

A3

A2

A1

A2

A1

A0

D0

D3 S1A 3 S1S0 A 2
D 2 S1A 2 S1 S0 A 3 S1S0 A1
D1 S1A1 S1 S0 A 2 S1S0 A 0
D 0 S1A 0 S1 S0 A1

4-bit Logical Shifter using 4-to-1 Mux

A3

A2

00 01 10 11
s1
s0 4-to-1 Mux
D3
S1
S0

S1

S0

D3

D2

D1

D0

A3

A2

A1

A0

Right Shift

A3

A2

A1

Left Shift

A2

A1

A0

A1

00 01 10 11
s1
s0 4-to-1 Mux
D2

A0

00 01 10 11
s1
s0 4-to-1 Mux
D1

00 01 10 11
s1
s0 4-to-1 Mux
D0

4-bit Arithmetic Shifter w/ 4-to-1 Mux

A3

A2

00 01 10 11
s1
s0 4-to-1 Mux
D3
S1
S0

S1

S0

D3

D2

D1

D0

A3

A2

A1

A0

Right Shift

A3

A3

A2

A1

Left Shift

A2

A1

A0

A1

00 01 10 11
s1
s0 4-to-1 Mux
D2

A0

00 01 10 11
s1
s0 4-to-1 Mux
D1

00 01 10 11
s1
s0 4-to-1 Mux
D0

4-bit Arithmetic Shifter w/ 4-to-1 Mux

Overflow/
Underflow

A3

A2

00 01 10 11
s1
s0 4-to-1 Mux
D3
S1
S0

S1

S0

D3

D2

D1

D0

A3

A2

A1

A0

Right Shift

A3

A3

A2

A1

Left Shift

A2

A1

A0

A1

00 01 10 11
s1
s0 4-to-1 Mux
D2

A0

00 01 10 11
s1
s0 4-to-1 Mux
D1

00 01 10 11
s1
s0 4-to-1 Mux
D0

4-bit Arithmetic Shifter w/ 4-to-1 Mux

Overflow
Underflow Detection

A3

A2

00 01 10 11
s1
s0 4-to-1 Mux
D3
S1
S0

Overflow/
Underflow

S1

S0

D3

D2

D1

D0

A3

A2

A1

A0

Right Shift

A3

A3

A2

A1

Left Shift

A2

A1

A0

A1

00 01 10 11
s1
s0 4-to-1 Mux
D2

A0

00 01 10 11
s1
s0 4-to-1 Mux
D1

00 01 10 11
s1
s0 4-to-1 Mux
D0

Rotator

A3

D3

S0

S0

D3

D2

D1

D0

A3

A2

A1

A0

A0

A3

A2

A1

A1

A0

A3

A2

A2

A1

A0

A3

A2

00 01 10 11
s1
s0 4-to-1 Mux

S1

S1

A1

00 01 10 11
s1
s0 4-to-1 Mux
D2

A0

00 01 10 11
s1
s0 4-to-1 Mux
D1

00 01 10 11
s1
s0 4-to-1 Mux
D0

Barrel Shifter

Right Shift

Left Shift

S2

S1

S0

D3

D2

D1

D0

A3

A2

A1

A0

A3

A3

A2

A1

A3

A3

A3

A2

A3

A3

A3

A3

A3

A2

A1

A0

A2

A1

A0

A1

A0

A0

Shift multiple bits at a time

Barrel Shifter Design w/ Mux (D3)

A3
00 01 10 11
s1
s0 4-to-1 Mux

2-to-1 Mux

S0

S2

0
1

S1

D3

S2

S1

S0

D
3

D
2

D
1

D
0

A3

A2

A1

A0

A3

A3

A2

A1

A3

A3

A3

A2

A3

A3

A3

A3

A3

A2

A1

A0

A2

A1

A0

A1

A0

A0

s0
s1 4-to-1 Mux
00 01 10 11

A3 A2 A1 A0

Replicate and change wiring of the two 4-to-1 Muxes for D2, D1 and

Barrel Shifter Design Alternative (16-bit)


(S3 S2 S1 S0) specifies the shift amount in binary

Input Number
16

S3

23 Shifter
16

S2

22 Shifter
16

S1

21 Shifter
16

S0

Left/Right

20 Shifter
16
Output Number

Barrel Shifter Design w/ nMOSFET


A3
D3
S=1
A2
D2
S=2
A1
D1
S=3
A0
D0

S=0
(No Shift)

S=1

S=2

S=3

Barrel Shifter Design w/ nMOSFET


A3

A3
D3

S=1
A2 A2
D2
S=2
A1
D1
S=3
A0
D0

S=0
(No Shift)

S=1

S=2

S=3

Barrel Shifter Design w/ nMOSFET


A3
D3

= A3

D2

= A3

D1

= A2

D0

= A1

S=1
A2

S=2
A1

S=3
A0

S=0
(No Shift)

S=1

S=2

S=3

Unsigned Binary Multiply


101 (5)
X 111 (7)
---------101
101
101
---------100011 (35)

Unsigned Integer Multiplier (2-bit)

b1 a1

b1 a0 b0 a1 b0 a0

2-bit by 2-bit
x

a1

a0

b1

b0

a1 b0
a1 b1
a1 b1

carry out

a0 b1
a1 b0 a0 b1

c H.A.

a0 b0

c H.A.

p2

p1

a0 b0

carry
p3

p0

Unsigned Integer Multiplier (3-bit)


3-bit by 3-bit
a2
a1
a0

a2 b2

b2

b1

b0

a 2 b0

a1 b0

a0 b0

a 2 b1

a1 b1

a 0 b1

a1 b 2

a0 b 2

b1 a2

b1 a1 b0 a2 b1 a0 b0 a1 b0 a0
0

s
b2 a2
c

co F.A. ci
ss

co F.A. ci
ss

b2 a1
c

b2 a0
c

s
s

p5

co F.A. ci
cs

co F.A. ci
cs

p4

p3

co F.A. ci
cs

p2

co F.A. ci

p1

p0

4-bit Unsigned Integer Multiplier


0
a3 b1

a3 b0

a2 b0

a2 b1

a1 b0

a1 b1

a0 b1

a0 b0

a0 b0

a3 b2

a3 b3

a2 b2

a1 b2

a0 b2

a2 b3

a1 b3

a0 b3

b0 a0

A
Cout

Cin

Sum
Full Adder
P7

P6

P5

P4

P3

P2

P1

P0

Propagation Delay
a3 b0

a3 b3

P7

a2 b0

a1 b0

a3 b1

a2 b1

a1 b1

a0 b1

4+

3+

2+

a3 b2

a2 b2

a1 b2

a0 b2

6+

5+

4+

a2 b3

a1 b3

a0 b3

7+

6+

P6

P5

P4

P3

a0 b0

4x4
Delay = 8 adders

8x8
Delay = 20 adders

P2

P1

P0

Carry-Save Multiplier
a3 b0

a2 b0

a2 b1

a2 b2

a3 b3

P7

a1 b1

a3 b1

a1 b2

a0 b2

a3 b2

a1 b3

a0 b3

a2 b3

P6

P5

P4

a1 b0
a0 b1

a0 b0

0
P3

P2

P1

P0

Propagation Delay of Carry-Save Multiplier


a3 b0

a2 b0

a2 b1

1+

a2 b2

P7

1+

a1 b2

a0 b2

2+

2+

a3 b2

a1 b3

a0 b3

3+

3+

5+

4+

P6

P5

P4

a3 b3

a1 b1

a3 b1

a2 b3

a1 b0
a0 b1

1+

a0 b0

4x4
Delay
= 6 adders

8x8
Delay
= 14 adders

0
P3

P2

P1

P0

Signed Binary Multiply


When the Multiplicand is negative
11101 (-3)
01001 (+9)
-------------------11111101
00
11101
-------------------11100101

Maintain the sign bits of the


partial product

Signed Binary Multiply


When the Multiplier is negative
01001 (+9)
11101 (-3)
-------------------01001
01001
-------------------0101101
01001
-------------------01110101
10111
-------------------111100101 (-27)

At the last step, 2s


complement the multiplicand
before adding

Signed Binary Multiply

When both the Multiplicand and Multiplier are negati


10111 (-9)
11101 (-3)
-------------------1110111
10111
-------------------11010011
10111
-------------------110001011
01001
-------------------000011011(+27)

Maintain the sign bits of the


partial product

At the last step, 2s


complement the multiplicand
before adding

More Examples (1)


Assume 8-bit numbers

1111 1010 (-6)


0000 0101 (+5)
-------------------111111 1010
111110 10
-------------------1110 0010 (-30)

More Examples (2)


Assume 4-bit numbers

0011 (+3)
1110 (-2)
-------------------0 0110
00 11
-------------------01 0010
110 1
-------------------1010 (-6)

More Examples (3)


Assume 8-bit numbers

1111 1100 (-4)


1110 0000 (-32)
-------------------11 1111 1000 0000
11 1111 00
-------------------111 1110 1000 0000
000 0010 0
-------------------000 0000 1000 0000 (+128)

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