CISC

(Complex
Instruction Set
Computer)
Kangkan Paul
NITW ECE III/IV
ANDHRA PRADESH

10/29/2008 Computer Architecture & Design 1

What is
CISC….?
 A complex instruction set computer
(CISC, pronounced like "sisk") is a
microprocessor instruction set architecture
(ISA) in which each instruction can execute
several low-level operations, such as a load
from memory, an arithmetic operation, and
a memory store, all in a single instruction.

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 The philosophy behind it is, that hardware
is always faster than software, therefore one
should make a powerful instruction set,
which provides programmers with assembly
instructions to do a lot with short programs.
 So the primary goal of the Cisc is to
complete a task in few lines of assembly
Main Idea of CISC
instruction as possible.

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Memory in those days was expensive
 bigger program->more storage->more money
Hence needed to reduce the number of instructions
per program
Number of instructions are reduced by having
multiple operations
within a single instruction
Multiple operations lead to many different kinds of
instructions that
access memory
 In turn making instruction length variable and
fetch-decodeexecute
time unpredictable – making it more complex
 Thus hardware handles the complexity

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
CISC philosophy
Use microcode
• Used a simplified microcode instruction set to
control the data path logic. This type of implementation
is known as a microprogrammed implementation.
 Build rich instruction sets
• Consequences of using a microprogrammed design
is that designers could build more functionality into
each instruction.
 Build high-level instruction sets
• The logical next step was to build instruction sets
which map directly from high-level languages
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 Register to register, register to memory, and
memory to register commands.
 Uses Multiple addressing modes .
 Variable length instructions where the length
often varies according to the addressing mode
 Instructions which require multiple clock cycles to
execute.
Characteristics of
a CISC design
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 Main memory

Memory (1,1) .. (6,4) = 24 locations

General purpose registers

Registers: A,B,C,D,E,F

CISC Vs. RISC

Arithmetic Logical Unit

Execution unit : arithmetic ( + -* ÷)

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  Let's say we want to
find the product of two
numbers - one stored in
2,3
location 2:3 and
another stored in
5,2 location 5:2 - and then
store the product back
in the location 2:3.
 i.e.,
Consider the M(2,3)<- M(5,2)*M(2,3)

operation of
Multiplication
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For this particular task, a CISC
 processor would come prepared with a specific instruction
(we'll call it "MULT").
MULT A,B
When executed, this instruction
 loads the two values into separate registers,
 multiplies the operands in the execution unit, and then
 stores the product in the appropriate register.
Thus, the entire task of multiplying two numbers can be
completed with one instruction
 MULT is what is known as a "complex instruction."
 It operates directly on the computer's memory banks and
does not require the programmer to explicitly call any
loading or storing functions.

CISC Approach
 It closely resembles a command in a higher level
language,identical to
the C statement "a = a * b."
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 RISC processors only use simple instructions that can
be executed within one clock cycle.
 The "MULT" command described above could be
divided into three separate commands:
LOAD A, 2:3
LOAD B, 5:2 (LOAD, which moves data
PROD A, B from the memory
("PROD,"finds bank to
the product of a
two
operands ) register)
STORE 2:3, A ("STORE,“ moves data from a
register to the memory banks)

RISC Approach
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 Primary goal is to
complete a task in as few
lines of assembly as
possible
 Emphasis on hardware  Primary goal is to
 Includes multi-clock speedup individual
complex instructions instruction
 Memory-to-memory:  Emphasis on software
"LOAD" and "STORE"  Single-clock,
incorporated in reduced instruction only
instructions  Register to register:
 Difficult to apply "LOAD" and "STORE"
pipelining. are independent
 Small code sizes, instructions
high cycles per second  Easy to apply pipelining.
 Low cycles per second,
large code sizes

CISC RISC
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 Thefollowing equation is commonly used for
expressing a computer's performance ability:

cisc
Risc
The CISC approach attempts to minimize the
number of instructions per program, sacrificing
the number of cycles per instruction.
RISC does the opposite, reducing the cycles per
instruction at the cost of the number of
instructions per program.

The Performance
Equation
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There is still considerable controversy among experts
about which architecture is better.
Some say that RISC is cheaper and faster and
therefore the architecture of the future.
Others note that by making the hardware
simpler, RISC puts a greater burden on the software.
Software needs to become more complex. Software
developers need to write more lines for the same
tasks.

Which one is
better...?
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No Big Difference
Now!
RISC and CISC architectures are becoming more and more alike.
 Many of today's RISC chips support just as many instructions as
yesterday's CISC chips. The PowerPC 601, for example, supports
more instructions than the Pentium. Yet the 601 is considered a
RISC chip, while the Pentium is definitely CISC.
 Further more today's CISC chips use many techniques formerly
associated with RISC chips
So simply said: RISC and CISC are growing to each other

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 EPIC :
 The biggest threat for CISC and RISC might not be each
other, but a new technology called EPIC.
 EPIC stands for Explicitly Parallel Instruction
Computing. EPIC can do many instruction executions in
parallel to one another.
 EPIC is a created by Intel and is in a way a combination of

Recent
both CISC and RISC. This will in theory allow the
processing of Windows-based as well as UNIX-based
applications by the same CPU.
Developments &
 Intel is working on it under code-name Merced. Microsoft
is already developing their Win64 standard for it. Like the
name says, Merced will be a 64-bit chip.

Future Scope
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 http://www.pcguide.com/ref/cpu/arch/int/instComplexity-c.htm
 http://www.bookrags.com/research/cisc-complex-instruction-s
 http://www.hitequest.com/Kiss/risc_cisc.htm

 http://en.wikipedia.org/wiki/Complex_instruction_set_compute

 http://en.wikipedia.org/wiki/X86
 http://www.amigau.com/aig/riscisc.html
 http://arstechnica.com/cpu/4q99/risc-cisc/rvc-1.html

References
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Thank you.

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