CS 251 INTRODUCTION TO

COMPTER ENGINEERING

Computer Data representation

and Computer Arithmetic

Data Representations
Most computers support a variety of data types.
Numeric: Integer: - Unsigned, signed
Binary Coded Decimal (BCD)
binary, ternary, octal,
Fractions
Floating point

Non-numeric: Character data

Boolean
String data

Positional Number Systems

Number systems are characterized by a
base or radix. e. g.
Decimal number with base 10 (or radix 10)
Binary numbers with base 2 (or radix 2)

General: radix R or base R:

Base or Radix of a number defines the
range of possible values a digit may have:
- e. g.
0 9 for decimal
0, 1 for binary

Positional Number Systems

The general form of determining the value
of the number is:-

The ds are generally 0, 1, ... R

Common notation: dddR

Base Conversion
Radix R - to - Decimal: Compute the expansion
Given a number with n total number of digits of radix R, and d be any

digit value in a position, then any radix can be converted to decimal by

using
n=dnRn++d0R0
e. g. Convert 2146 to decimal
2146 = [2 62] + [1 61] + [4 60] = 72 + 6 + 4 = 8210 or simply 82.

Decimal - to - Radix R
Successively divide the decimal number by the target radix and note the
remainder until the quotient is 0
The method is called base conversion with the remainder method
Last remainder is considered to be the most significant bit (msb) and the
first remainder to least significant bit (lsb)

Base Conversion
Decimal - to - Radix R (continuing)
e. g. Convert 8210 into radix 6.
Here target radix is 6
Integer
82 6
=
13
13 6
=
2
26
=
0
8210 = 2146

Remainder
4 --------- lsb
1
2 --------- msb

Radix R1 to Radix R2
Convert R1 to decimal first, then obtained decimal to R2:
that is [R1 to decimal to R2]

Base Conversion
Binary fraction to decimal
e. g. Convert 0.10112 to decimal
0.10112
=
[1 21] + [0 22] + [1 23] + [1 24]
=
0.5 + 0 + 0.125 + 0.0625
=
0.687510

Decimal fraction to binary

Multiply the fraction part of the decimal by the target
radix and recover any carriers in the integer position
Multiplication continues until a product of 1 is reached
e. g. Convert 0.687510 to binary ; [ here target radix is 2]
product carrier
0.6875 2
=
1.375 1 ------- msb
0.375 2
=
0.75 0
0.75 2
=
1.5
1
0.5 2
=
1.0
1 -------- lsb
0.687510 = 0.10112

Base Conversion
Non-terminating base 2 fraction
Sometimes 1.00 will not occur. In this case the process is
terminated after a suitable number of decimal places.
e. g. Convert 0.210 to binary; [here target radix is 2]
0.2 2
0.4 2
0.8 2
0.6 2
0.2 2
0.4 2

0.210

=
=
=
=
=
=
=

Product
Carrier
0.4
0 --------- msb
0.8
0
1.6
1
1.2
1
0.4
0 --------- lsb
0.8
repeating, no termination
0.00112

Base Conversion
Binary to Hexadecimal
Hexadecimal numbers are based on the hexadecimal
counting system formed on a base of 16
Consists of 16 different symbols : 0 9,A,B,C,D,E and F;
each corresponding to decimal numbers 0 15
They are used to represent or remember multi-bit binary
numbers
How:
Write down the full binary numbers
Split the number into groups of 4 bit each staring from
lsb
Convert each group into its equivalent decimal number,
and substitute the equivalent Hexadecimal digit for
each group

Base Conversion
Binary to Hexadecimal (continuing)
e. g. Convert 11100011011011012 to base 16
1110 0011 0110 1101
14
3
6
13
E
3
6
D
1110001101101101
=

E36D16

Hexadecimal to decimal convertion

follows the normal procedure of converting any radix
number to decimal number.

Exercise:
Convert 23.37510 to base 2 and prove if it is correct by
converting back the answer in base 2 to decimal

Base 10, 2, 8, 16 Number System

Decimal
(base 10)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Binary
(base 2)
0
1
10
11
100
101
110
111
1000
1001
1010
1011
1100
1101
1110
1111

Octal
(base 8)
0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17

Exercise: Show a column for Ternary (Base 3)

Hexadecimal
(Base 16)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F

Conversion among Power of 2 bases

4 bits are used to represent a hexadecimal number
(base 16); 24 = 16, 4 being number of bits
Similarly: Base 2, 1 bit is used, 21 = 2
Base 4, 2 bits are used, 22 = 4
Base 8, 3 bits are used, 23 = 8
Converting among power of 2 base needs the
grouping of bits as per required base target. Grouping
starting at the lsb. Examples: 10112

= [102][112]

= 234

1010102 =

[1012][0102]

1010102 =

[102][102][102] = 2224

234 = [24][34]

= 528
= [102][112] = 10112

Fixed Point Numbers

A number in a fixed length computer register
that is understood to have its radix point in a
specific position is called a fixed-point
number
Common type is an integer which have the
radix point at far right, and for fractions is at
the far left
A series of N bits binary number can
represent 2N different decimal numbers
(possible bit patterns). Ranging from 0 up to
[2N 1], e. g.
For an 8 bit number, there are 2 8 = 256 possible
bit patterns, from 0 to 255 [that is 2 8 1]

Representation of Negative Integer Numbers

[Signed Numbers]

Four methods used:

Signed Magnitude
Ones Compliment
Twos Compliment
Biased or Excess representation

Sign-Magnitude
N bits can represent values from -(2 N-1 -1) to +(2N1 -1). There are two representations for 0; +0 and
-0.
one bit, usually the leftmost bit, represents the
sign of the number (0 for +, 1 for -), the remaining
bits specify the magnitude of the number. e. g.
+ 25 = 000110012 , msb = 0 showing a +ve number
- 25 = 100110012, msb = 1 showing a -ve

Sign-Magnitude (cont.)
Two representations for zeros:
+ 0 = 000000002
- 0 = 100000002

For an 8-bit representation; largest

number is +12710 and smallest number is
12710.
Arithmetic operations are complex, it is
performed by examining the msb as a sign
bit, hence stripping it off from the number.
e. g. +15 can be taken as 7 in a 4-bit
representation

Radix Complement and Diminished Radix

Complement
Radix complement in base b is called bs
complement
Diminished radix complement in base b is
called [b 1]s complement
In base 2, these number system and the
corresponding operations are familiar
under the names:
2s complement or twos complement in radix
complement and
1s complement or ones complement in
diminished complement

Ones Compliment
N-bits can represent values from; -(2 N-1-1) to +(2N-1
-1)
The negative of a value is obtained by inverting or
complementing each bit [0 to 1 and 1 to 0]
The procedure goes both ways from +ve to ve or
from ve to +ve
The msb is the sign bit [0 for +ve, 1 for ve]
Two representation for zero:
+0 = 000000002
-0 = 111111112

In 1s complement; the number and its negative

adds up to [2N 1].
For an 8-bit representation, the largest number is
+12710 and the smallest number is number -127 10

Twos Complement
N-bits number can represent values from: -2n-1 to
+(2n-1 -1)
The negative of a value is obtained by adding 1
to the ones compliment negative. Perform Ones
complement first the add 1
The procedure goes both ways from +ve to ve or
from ve to +ve
The msb is the sign bit [0 for +ve, 1 for ve]
One representation for zero:
+0 = 000000002
-0 = 000000002

In 2s complement; the number and its negative

adds up to [2N].
For an 8-bit representation, the largest number is
+12710 and the smallest number is number -12810

Twos Complement Cont.

Example: complement + 2510 to 2510
+2510 = 000110012
1s complement = 11100110 2
add 1

00000001 2

Answer

= 11100111 2

Alternative way of finding 2s complement:

Bring down all the trailing zeros
Bring down the first one (1) from right
complement all additional bits
e. g. convert 001100 2 to its twos complement
001100
00
100
110100 = 1101002

Benefits
One representation of zero
Arithmetic works easily (see later)
Negating is fairly easy
3 = 00000011
Boolean complement gives
Add 1 to LSB

11111100
11111101

Negation Special Case 1

0=
00000000
Bitwise not
11111111
Add 1 to LSB
+1
Result
1 00000000
Overflow is ignored, so:
-0=0

Negation Special Case 2

-128 =
10000000
bitwise not
01111111
Add 1 to LSB
+1
Result
10000000
So:
-(-128) = -128 X
Monitor MSB (sign bit)
It should change during negation

Excess (Biased) Representation

Msb is a sign bit; 0 for negative number, 1 for
Positive number
All numbers are represented by
first adding them to the bias [bias (b) = 2 n-1]
and then encoding this sum as an ordinary unsigned
number normally using 2s complement
i.e. [K + bias (b)]

For n-bits number can represent values from -b to +(2 n-1-b)

Since the bias is commonly chosen to be 2 n-1, this is yielding to
a range of -2n-1 to +(2n-1-1)
For example: convert 1210 to its complement using biased
method. Use 8-bits
1210
= 0000 11002
Bias = 28-1 = 27 = 128 = 1000 00002
adding
= 1000 11002
2s complement
= 0111 01002

Excess (Biased) Representation Cont.

Alternatively: positive and negative
representations of a number are obtained by
adding a bias to the twos complement
representation
e. g. +12 = 0000 11002
2s complement = 1111 01002
Add bias = 128 = 1000 00002
Answer

= 1 0111 0100

overflow ignored

One representation for zero: +0 = 100000002 -0

= 100000002
The procedure goes both ways from +ve to ve or
from ve to +ve
For an 8-bit representation, the largest number is
+12710 and the smallest number is number -12810

Floating Point Numbers

Floating point numbers allow very large and
very small numbers to be presented using only
few digits at the expense of precision.
The precision is primarily determined by the
number of digits in the fraction (or significand),
which has integer and fractional parts.
Many application require numbers that are not
integers. To represent this the commonly used
way is to use floating points
Floating point number is divided into two parts:
an exponent
A significand or mantissa
e. g. 1.5 2-3 = 0.1875

Normalization
Normalized representation places the
radix point immediately to the left of the
left most nonzero digit in the fraction
e. g. 254 = 0.254 103

Representation of a floating point number

is as shown: s

Exponent (e)

Significand or Mantissa

Representation of floating Point numbers

The exponent is a signed number
represented using a bias method with a
bias of 127
The fraction represents a number less
than 1, but the significand of the floating
point number is 1 plus the fraction part
If e is the biased exponent (value of the
exponent field), and f is the value of the
fraction field
then; the number is represented as
1.f 2e-127

IEEE 754 Floating Point Standard

In 1985 a standards committee of the Institute of
Electrical and Electronics Engineers (IEEE)
formulated and published a standard format for
binary floating point numbers.
The exponent is represented in "excess" or
"biased" form. This biased representation of the
exponent is called the characteristic.
Normally with an n-bit biased system the bias is
2 n-1, so that the largest exponent corresponds
to a characteristic containing n 1's. For an 8-bit
characteristic the bias would be 128 decimal.

IEEE 754 FORMATS

IEEE 754 FORMATS

However in the IEEE standard, 127 is chosen
as the bias so that the characteristic containing
all 1's can be used as a special case to
represent infinity. That is, + or - infinity are
represented by the appropriate sign bit followed
by all 1's in the characteristic and all 0's in the
mantissa.
32 and 64 bit standards
8 and 11 bit exponent respectively
These formats assume a normalized mantissa
of the form 1.M where M is the 23-bit or 52-bit
mantissa.

Representation of Floating Point Numbers

The exponent is a signed number represented
using the bias method with a bias 127
In radix 2, normalization corresponds to having a
fraction whose first bit (MSB) is 1. This leading bit
in the mantissa is often called the normal bit.
The fraction represents a number less than 1, but
the significand of the floating point number is 1
plus the fraction part
i. e. if e is the biased exponent (value of exponent
field) and f is the value of the fraction field
the number is represented as
1.f 2e-127

Since the leading bit (corresponding to the value 1) is

always present, it is omitted from the representation

Representation of Floating Point

Numbers
To obtaining the floating point representation of a number
requires generating each of the components, the sign bit,
the characteristic (i. e. biased representation of the
exponent) and the mantissa.
The sign bit is 1 for a negative value and 0 for a positive
value.
The mantissa is obtained by converting the decimal
number into a binary fraction.
Once the binary fraction is obtained, the significand is
generated by shifting the radix point to the proper position.
The number of places that the radix point is shifted
determines the exponent.
The excess or biased form of the exponent gives the
characteristic.

Examples of Floating Point Numbers

Example: Represent the following number
0.12510 into a single-precision binary
number.
Soln. Changing into binary
0.12510 = 0.0012
the number is +ve, then 0 for sign bit,
Normalizing = 1.0 2-3: 1.0 is the
significand, and from 1.f 2e-127; e 127 =
-3
then: e = -3+127 = 124 is the
characteristic (i. e. the biased exponent)

Examples of Floating Point Numbers

How would 763.510 be represented as a
single precision IEEE floating point number?
763.510 = 1011111011.12 = 1.0111110111 x 29
Hence the sign bit = 0; bse is a +ve number
the characteristic e = 9+127 = 13610 =
100010002
the 23-bit mantissa is
011 1110 1110 0000 0000 0000
The corresponding IEEE single precision
representation is

Examples of Floating Point Numbers

What single-precision number does the following

32 bit word represent:
1 1000 0001 010 0000 0000 0000 0000 00002
Soln.: msb = 1 indicates ve number
e = 1000 00012 = 27 + 20 = 129
hence 2e-127 = 2129-127 = 22
Fraction Part: Convert .012 into decimal = [0 21] + [1 22]
= 0.2510 making the significand of 1.25
Hence the number is 1.25 22 = - 5

Write in single-precision IEEE-754 format

+1.101 25
Soln. Since the number is +ve then sign bit is 0
From 1.f 2e-127: 1 is hidden
5 = e 127, then e = 132 = 1000 0010 = characteristic
Significand = 101 0000 0000 0000 0000 0000
Representation is: 0 1000 0010 101 0000 0000 0000 0000
0000

Coding
Coding is the representation of characters via a
character code in which each character is assigned
a unique combination of bits
Three most popular codes are:
BCDIC = Binary Coded Decimal Interchange Code
EBCDIC = Extended Binary Coded Decimal
Interchange Code
ASCII
= American Standard Code for Information
Interchange
Unicode

ASCII:

is a 7- bit code (128 characters) stored in 8 bit (byte)

Has an extended 8 bit version
Used on PCs and non IBM mainframes
widely used to transfer data from one computer to
another
Now beind replaced by Unicode

Coding
EBCDIC:
Is an 8 bit code (256 characters)
Used on mainframe IBM machine

Unicode:
is a 16 bit standard
can represent 65 thousand characters of
which 49,000 have been defined
incorporates ASCIII as subnet
Example ASCII coding:

ASCII Coding
CAD = 43414216
= 0100 0011 0100 0001 0100 00102
f1

= 463116
= 0100 0110 0011 00012

3415 = 3334313416
= 0011 0011 0011 0100 0011 0001
01012
Note that this is a text strong and no
arithmetic may be done in it
symbo
l

Code

41

4
2

43

44

55

46

30

31

32

33

34

35

36

37

Conversion Between Lengths

Positive number pack with leading zeros

+18 =
00010010
+18 = 00000000 00010010
Negative numbers pack with leading ones
-18 =
10010010
-18 = 11111111 10010010
i.e. pack with MSB (sign bit)

COMPUTER ARTHMETIC
Four basic arithmetic operations in a computer
Addition, subtraction, multiplication, and division

Significant issues include:

Fixed point arithmetic

Floating point arithmetic
Overflow
Underflow
Handling of signed number
Performance

Overflow occurs when:

Adding two positive numbers produces a negative
number or
Adding two negative numbers produces a positive
numb

Example of an Overflow
Add 8010 + 8010
Using decimal addition: 80 + 80 = 16010
Using binary: 80 = 0101 0000
80 = 0101 0000
160 = 1010 00002 = - 9610
How: Msb = 1 hence a negative number
Taking the twos compliment of 1010 000
= 0110 0000 = - 9610

Half and Full Adder

Half adders and full adders are the natural
components for addition
Half adder takes two bits a and b as input and
produces a sum bit s and a carry bit co as
output
Full adder takes three bits a, b and a carry c i
as an input and produces a sum bit s and and a
Addition Rules Full Adder
carry bit co as an output
A + B + ci

Addition rules Half

Adder
A+B
0
0
1
1

0
1
0
1

Carry

Sum

0
0
0
1

0
1
1
0

0
0
0
1
0
0
0
1
1

0
0
1
1
0

Carry

Sum

0
0
0
1
0
1
1
1

0
1
1
0
1
0
0
1

Ripple Carry Adder

Consists of n full adders
The carry-out of one full adder is
connected to the carry-in of the adder for
the next msb.
Two binary numbers A and B are added
from right to left creating a sum and a
carry at the output of each full adder for
each bit position

Ripple-Borrow Subtractor
A ripple-borrow subtractor can be
composed of a cascade of full
subtractors.
Two binary numbers A and B are
subtracted from right to left, creating
a difference and a borrow at the
Rules Full
outputs of each full Subtraction
subtractor
for
subtractor
each bit position.
a +b +
diff
bor
i

I+1

bori
0
0
0
0
1
1

0
0
1
1
0
0

0
1
0
1
0
1

0
0
0
1
0
1

0
1
1
0
1
0

Ripple-Borrow Subtractor

Combined Adder/Subtractor
A single ripple- carry adder can perform
both addition and subtraction, by forming
the twos complement negative for B when
subtracting. (Note that +1 is added at c0 for
twos complement.)

Addition and Subtraction

Normal binary addition
Monitor sign bit for overflow
Take twos compliment of subtrahend and
add to minuend
i.e. a - b = a + (-b)

So we only need addition and complement

circuits

Ones Complement Addition

An example of ones complement integer addition
with an end-around carry
1 0 0 1 12

(- 12)

0 1 1 0 12

(+13)

100000
+
1 ------------ End-around carry

0001
(+1)

The end-around carry is needed because there are

two representations for 0 in ones complement. Both
representations for 0 are visited when one or both
operands are negative.

Multiplication

Complex
Work out partial product for each digit
Take care with place value (column)
Add partial products
Multiplication of two 4-bits unsigned
binary integers produces an 8-bits result
Multiplication of two 4-bit signed binary
integers produces only a 7-bit result (each
operand reduces to a sign bit and a 3-bit
magnitude for each operand, producing a
sign-bit and a 6-bit result).

Multiplication Example

1011

x 1101

1011

0000

1011
1011
10001111
Note: need

Multiplicand (1110 )
Multiplier

(1310)

Partial product
Partial product
Partial product
Partial product
Product (143 10)
double length result

Unsigned Binary Multiplication (Right

Shift Procedure) using A Serial Multiplier
The unsigned numbers to be multiplied are
placed in registers A and B respectively
Register p is initially set to 0
Each multiply step has two parts:
If the least significant bit (lsb) of A is 1, then register
B is added to P: otherwise 00..00 is added to P. The
sum is placed back to P
Register P and A are shifted right, with the carry-out
of the sum being moved in the high-order bit (msb) of
P, the low-order bit (lsb) of P being moved into
register A, and the rightmost bit of A, which is not
used in rest of the algorithm being shifted out.

After n steps, the product appears in register p

and A, with A holding the lower-order bits.

Simplified Block diagram of a multiplier

Each multiplication step consists of adding
the contents of P to either B or 0
(depending on the low-order bit of A),
replacing P with sum, and shifting both P,
and A one bit right
Carry-out

Shift
C

Execution of Multiplication Example

Multiply 11012 10112
Register B: 1 1 0 1 -------Multiplicand (M), Initial value
C
0
0
0
1
0
0
0
1
0

Register
P
0000
1101
0110
0011
1001
1001
0100
0001
1000

Register
A or Q
1 0 1 1-------- Initial values. Note lsb of A is 1, then
1 0 1 1------- 1(a): add B to P, and sum to P
1 1 0 1 --------1(b): Shift one step right. Note Lsb of A is 1,then
1 1 0 1 --------2(a): Add B to P, and sum to P
1 1 1 0---------2(b): Shift one step right, Note lsb is 0, then
1 1 1 0---------3(a): Add 0000 to P, and sum to P, or skip addition
1 1 1 1---------3(b): Shift one step right, lsb of A is 1, then
1 1 1 1---------4(a): Add B to P, and sum to P
1 1 1 1---------4(b): Shift one step right

After n- steps, the product appear in register P and

A
Answer = 1 0 0 0 1 1 1 12 = 14310

Flow Chart for simplified Serial Multiplier Block

START

C, P = 0
B Multiplicand
A Multiplier
Count n

No

Yes
A0 =
1?

P= B + P

Shift right:
C, P, A.
Count = Count - 1

No

Yes
Count =
0?

End

Product= P, A

Unsigned Binary Multiplication

Flowchart for Unsigned Binary

Multiplication

Serial Divider
Operates the division of an unsigned number and
produces the quotient bits one at a time
From a b (a/b), put a in register A, b in
register B, 0 in register P and then perform n
divide steps
Each divide step consists of four parts:
Shift the register pair (P, A) one bit left
Subtract the content of register B (which has number b)
from register P, putting the result back into P
If the result of step 2 is negative, set the low-order bit
of A to 0, otherwise to 1
If the result of step 2 is negative, restore the old value
of P by adding the contents of register B back into P

Repeat this process n times

The A register will contain the quotient, and the P
register will contain the remainder

Simplified Block diagram of a Serial Divider

Each division step involves first shifting P

and A one bit left,subtracting B from P,
and if the different is nonnegative, putting
it into P. If the difference is nonnegative,
the low-order bit of A is set to 1.
Shift
P

Execution of Division Example

Divide 14/3 11102/00112
Register B: 0 0 0 1 1 -------Divisor (M), Initial value
Register
P
00000
00001
11110
11110
00001
00011
00000
00000
00001
11110
11110
00001
00010
11111
11111
00010

Register
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1

1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0

A
0 -----Initial values.
-----1(i): shift one step left
-----1(ii): subtract P B, result put in P.
0 -----1(iii): msb = 1, result is ve,set Quotient bit A 0 to 0
0 -----1(iv): step 2 is ve, restore the old value of P
------2(i): shift left
------2(ii): subtract P-B, result in P
1 -----2(iii): msb = 0, +ve result, set A 0 to 1
----- 3(i): shift left
------3(ii): subtract P-B result in P
0 -----3(iii): msb = 1, -ve result, A 0 (lsb) = 0
0 -----3(iv): Step 2 ve, restore the old value of P
-----4(i): Shift left
-----4(ii): subtract P-B, result in P
0 -----4(iii): msb = 1, -ve result, A0 (lsb) = 0
0 -----4(iv): restore the old value of P

After n- steps, the Quotient appear in register A and Remainder in

register P Answer = 01002 rem 000102 = 410 rem 210

Division of Unsigned Binary Integers

00001101
Divisor
1011 10010011
1011
001110
Partial
1011
Remainders
001111
1011
100

Quotient
Dividend

Remainder

Flowchart for Unsigned Binary Division

Multiplying Negative Numbers

This does not work!
Solution 1
Convert to positive if required
Multiply as above
If signs were different, negate answer

Solution 2
Booths algorithm

Booths Algorithm
Booths Algorithm forms the basis for a
number of signed multiplication algorithms
It is based upon recording the multiplier,y, to
a recoded, value ,z, leaving the the
multiplicand ,x, unchanged
In booth recoding, each digit of the multiplier
can assume negative as well as positive and
zero
There are especial notation called signed
digit (SD) encoding, to express these signed
digits
In SD encoding; +1 and 0 are expressed as a
1 and 0, but 1 is expressed as 1.

Booths Algorithm
e. g. booth recoding recodes the no 7 as 8-1
7 = 8-1 = 10002 00012 = 1001
Where 1 represents 1 as above
If M is the multiplicand, A the accumulator register, Q the
multiplier and Q-1 the extra appended bit on the right of Q,
then Booth's algorithm may be executed as shown below:

1. Initialization
a. Load A and Q-1 with zeros.
b. Load M with the multiplicand
c. Load Q with the multiplier

2. Repeat n times:
a. If the Q0 = 0 and Q-1 = 0, add 0 to A. else
b. if the Q0 =0 and Q-1 =1, Add M to A. else
c. If the Q0 =1 and Q-1 =0, Subtract M from A. else
d. If the Q0 = 1 and Q-1 = 1 add 0 to A
e. Shift AQQ-1 one bit right using sign extension.

Booths Algorithm

Example of Booths Algorithm

Division
More complex than multiplication
Negative numbers are really bad!
Based on long division

FP Arithmetic +/ To add or subtract two floating point

numbers, their number points must be
aligned. This is the same as making their
exponents equal.
For example: 0.12510 = 0.12 2 -2

1.510 = 0.112 2

+1

Since the numbers will be normalized initially,

the exponents can only be adjusted by
shifting right. Otherwise, significant bits from
the fraction will be lost.
For each bit position that a mantissa is
shifted to the right, the exponent of the
number is increased by 1.

FP Arithmetic +/ Thus, to align the number points, the

value with the smaller exponent is shifted
right until its exponent matches that of
the other value
0.11012 2 +1 = 1.1012 = 1.62510

FP Arithmetic +/- Examples

Operands
Alignment
Normalization
6.144 102
0.06144 104 1.003644 105
+ 9.975 104 + 9.9975 104
10.03644 104
1.076 10-7 1.076 10-7
- 9.987 10-8 - 0.9987 10-7
0.0773 10-7

7.73 10-9

FP Addition & Subtraction Flowchart

FP Arithmetic x/

Check for zero

Add/subtract exponents
Multiply/divide significands (watch sign)
Normalize
All intermediate results should be in
double length storage

FP Arithmetic x/
i. e. The product of two floating point numbers is
computed by multiplying the two mantissas and
using the sum of the two exponents as the
exponent of the product. The product will be
normalized and the exponent adjusted accordingly.
(f1 x 2 e1 ) * (f2 x 2 e2 ) = (f3 x 2e3 )
where f3 = f1 x f2, and e3 = e1+e2.

The quotient of one number divided by another

has a mantissa equal to the quotient of the
dividends mantissa divided by the divisors
mantissa. The exponent of the quotient equals the
exponent of the dividend minus the exponent of
the divisor. Any required normalization is
performed after the division.
(f1 x 2e1 ) / (f2 x 2 e2 ) = (f3 x 2e3 )
where f3 = f1/f2, and e3 = e1-e2.

FP Arithmetic x/ Examples

Sign, Fraction, and Exponent

Normalization

(- 0.1403 10-4)
0.4238463 100
(+0.3021 105)
- 0.04238463 10-4+5

(- 0.9325 102)
109
(- 0.1002 10-6)
+ 9.306387 102-(-6)

+ 0.9306387

Floating Point Multiplication

Floating Point Division

Carry-Lookahead (CLA) Addition

Integer addition is the very important
operation in the computer, hence must be
performed in high-speed.
Carry-Lookahead is one among techniques
to perform high-speed integer addition
From the logic equation of a full Adder to
perform addition operation with ripple
carry, Carries are represented in terms of Gi
generate) and Pi (propagate) expressions.

Carry-Lookahead (CLA) Addition

ci is both the carry-in in the ith adder and
carry-out from the (i-1)th adder

Carry-Lookahead (CLA) Addition