ADVANCED MICROPROCESSOR
PAGING IN 80386
SUBMITTED TO:
[Link] BHULLAR
SUBMITTED BY:
GAGANDEP KAUR
(13105075)
MEMORY MANAGEMENT UNIT
The Memory management unit consists of a Segmentation
unit and a Paging unit.
Segmentation unit allows the use of two address
components, viz. segment and offset for relocability and
sharing of code and data.
Segmentation unit allows segments of size 4Gbytes at max.
The Paging unit organizes the physical memory in terms of
pages of 4kbytes size each.
Paging unit works under the control of the segmentation
unit, i.e. each segment is further divided into pages.
The paging unit is a memory management unit enabled
only in protected mode
The Segmentation unit provides a 4 level protection
mechanism for protecting and isolating the system code
and data from those of the application program.
Paging unit converts linear addresses into physical
addresses.
The control and attribute PLA checks the privileges at the
page level. Each of the pages maintains the paging
information of the task. The limit and attribute PLA checks
segment limits and attributes at segment level to avoid
invalid accesses to code and data in the memory segments.
PAGING OPERATION
Paging is one of the memory management techniques used
for virtual memory multitasking operating system.
The segmentation scheme may divide the physical memory
into a variable size segments but the paging divides the
memory into a fixed size pages.
The segments are supposed to be the logical segments of
the program, but the pages do not have any logical relation
with the program.
The pages are just fixed size portions of the program
module or data.
The advantage of paging scheme is that the complete
segment of a task need not be in the physical memory at
any time.
Only a few pages of the segments, which are required
currently for the execution need to be available in the
physical memory. Thus the memory requirement of the task
is substantially reduced, relinquishing the available
memory for other tasks.
Whenever the other pages of task are required for
execution, they may be fetched from the secondary storage.
The previous page which are executed, need not be
available in the memory, and hence the space occupied by
them may be relinquished for other tasks.
Thus paging mechanism provides an effective technique to
manage the physical memory for multitasking systems.
Paging Unit: The paging unit of 80386 uses a two level
table mechanism to convert a linear address provided by
segmentation unit into physical addresses.
The paging unit converts the complete map of a task into
pages, each of size 4K. The task is further handled in terms
of its page, rather than segments.
The paging unit handles every task in terms of three
components namely page directory, page tables and page
itself.
Paging Descriptor Base Register: The control register CR2
is used to store the 32-bit linear address at which the
previous page fault was detected.
The CR3 is used as page directory physical base address
register, to store the physical starting address of the page
directory.
The lower 12 bit of the CR3 are always zero to ensure the
page size aligned directory. A move operation to CR3
automatically loads the page table entry caches and a task
switch operation, to load CR0 suitably.
Page Directory : This is at the most 4Kbytes in size. Each
directory entry is of 4 bytes, thus a total of 1024 entries are
allowed in a directory.
The upper 10 bits of the linear address are used as an index
to the corresponding page directory entry. The page
directory entries point to page tables.
Page Tables: Each page table is of 4Kbytes in size and
many contain a maximum of 1024 entries. The page table
entries contain the starting address of the page and the
statistical information about the page.
PAGE TABLE ADDRESS
OS
31 .12
RESERVED
U
S
R
W
U
S
R
W
PAGE DIRECTORY ENTRY
PAGE FRAME ADDRESS
OS
31 .12
RESERVED
PAGE TABLE ENTRY
PERMITTED FOR
U
S
R
W
READ ONLY
READ - WRITE
LEVEL 3
NONE
NONE
PERMITTED FOR
LEVEL2 , 1 OR 0
READ / WRITE
READ /
WRITE
READ /
WRITE
READ /
WRITE
The upper 20 bit page frame address is combined with the
lower 12 bit of the linear address. The address bits A12- A21
are used to select the 1024 page table entries. The page
table can be shared between the tasks.
The P bit of the above entries indicate, if the entry can be
used in address translation.
If P=1, the entry can be used in address translation,
otherwise it cannot be used.
The P bit of the currently executed page is always high.
The accessed bit A is set by 80386 before any access to the
page. If A=1, the page is accessed, else unaccessed.
INSIDE
31
22
12
DIRECTORY
10
IN THE MEMORY
80386
TABLE
0
OFFSET
USER
MEMORY
10
12
CR
31 DIRECTORY
CR 1
CR
CR
31
31
2
3
0
+
PAGE TABLE
DBA
CONTROL
REGISTERS
DBA Physical directory base address
