CS504 : Digital Design

Lecture Three
Gate-Level Minimization

Circuit Optimization
Goal: To obtain the simplest
implementation for a given function
Optimization is a more formal approach to
simplification that is performed using a
specific procedure or algorithm
Optimization requires a cost criterion to
measure the simplicity of a circuit
Distinct cost criteria we will use:
Literal cost (L)
Gate input cost (G)
Gate input cost including inverters (GN)
Circuit Optimization 2

Literal Cost
Literal a variable or it complement
Literal cost the number of literal
appearances in a Boolean expression
corresponding to the logic circuit diagram
Example: Boolean expressions for F
F = B D + AB C + AC D

L= 8

F = B D + AB C + AB D + AB C

L = 11

F = (A+B)(A+D)(B+C+D)(B+C+D)

L = 10

Which solution is best?

First solution is best

Circuit Optimization 3

Gate Input Cost

Gate Input Cost: Count of total number of inputs to the
gates in the logic circuit implementation
Two gate input costs are defined:
G = Count of gate inputs without counting Inverters
GN = Count of gate inputs + count of Inverters
For SOP and POS equations, the gate input cost can be
found from the Boolean expression by finding the sum of:
All literal appearances
Number of terms excluding single literal terms (added to G)
Number of distinct complemented single literals (added to GN)

Example:
F= B D + AB C + AC D

L = 8 G = L+3 = 11
GN = G+3 = 14
Circuit Optimization 4

Cost Criteria (continued)

GN = G + 2 = 9
L
=
5
F= A+ B C + BC
G=L+2= 7
Example 1:

B
C
A

L (literal count) counts the AND inputs and the single

literal OR input.
G (gate input count) adds the remaining OR gate inputs
GN(gate input count with NOTs) adds the inverter inputs
Circuit Optimization 5

Cost Criteria (continued)

Example 2:

A
B
C

F = A B C + AB C
L = 6 G = 8 GN = 11
F = (A + C)( B + C)( A + B)
L = 6 G = 9 GN = 12

Same function and same

A
literal cost
B
But first circuit has better C
gate input count and better
gate input count with NOTs
Select first circuit!

Circuit Optimization 6

Cost Criteria Summary

Literal Count:
Simple to evaluate by counting all literals
However, does not represent circuit complexity
accurately in all cases

Gate Input Cost (or Count):

Good measure of logic implementation
Proportional to the number of transistors and
wires used in the implementation
Important when measuring cost of circuits with
more than two levels
Circuit Optimization 7

Boolean Function Optimization

Minimizing the gate input (or literal) cost of a
Boolean equation reduces the circuit cost
We choose gate input cost
Boolean Algebra and graphical techniques are tools
to minimize cost criteria values
Some important questions:
When do we stop trying to reduce the cost?
Do we know when we have a minimum cost?

Treat optimum or near-optimum cost functions

for two-level (SOP and POS) circuits first
Introduce a graphical technique using Karnaugh
maps (K-maps for short)
Circuit Optimization 8

Karnaugh Map (K-map)

A K-map is a collection of squares

Each square represents a minterm

Adjacent squares differ in the value of one variable

The collection of squares is a graphical representation

of a Boolean function

Alternative algebraic expressions for the same function

are derived by recognizing patterns of squares

The K-map can be viewed as

A reorganized version of the truth table
Circuit Optimization 9

Some Uses of K-Maps

Provide a means for:
Finding optimum or near optimum
SOP and POS standard forms
Two-level AND/OR and OR/AND circuits

for functions with small numbers of variables

Visualizing concepts related to manipulating
Boolean expressions, and
Demonstrating concepts used by computeraided design programs to simplify large circuits
Circuit Optimization 10

Two-Variable K-Map
A 2-variable Karnaugh Map:
Minterm m0 and minterm m1 are adjacent

they differ in the value of variable y

Similarly, minterm m0 and minterm m2 are
adjacent and differ in x
Also, m1 and m3 differ in the x variable

Finally, m2 and m3 differ in the y variable

x

y=0

y=1

x = 0 m0 = x y m1 = x y
x = 1 m2 = x y m3 = x y

Circuit Optimization 11

K-Map and Truth Tables

The K-Map is a different form of the truth table
Truth Table
Input
Values
(x,y)

Function
Value
F(x,y)

00
01
10
11

1
0
1
1

K-Map
y

y=0

y=1

x=0

x=1

Circuit Optimization 12

K-Map Function Minimization

F(x,y) = m0 + m2 + m3
F=xy+xy+xy

Two adjacent cells

containing 1s can be
combined using the
Minimization Theorem

K-Map
y

y=0

y=1

x=0

x=1

m0 + m2 = x y + x y = (x + x) y = y
m2 + m3 = x y + x y = x (y + y) = x
Therefore, F can be simplified as F = x + y
Circuit Optimization 13

Three Variable K-Map

yz

yz=00

yz=01

yz=11

yz=10

x=0

m0

m1

m3

m2

x=1

m4

m5

m7

m6

Where each minterm corresponds to the product terms:

yz

yz=01

yz=11

yz=10

x=0 x y z

xyz

xyz

xyz

xyz

xyz
xyz

x=1

yz=00

xyz

Note that if the binary value for an index differs in one bit
position, the minterms are adjacent on the K-Map
Circuit Optimization 14

Alternative K-Map Labeling

K-Map largely involves:
Entering values into the map, and
Reading off product terms from the map

Alternate labelings are useful:

x
x

yz
00

14

00 01 11 10

x
x

z
Circuit Optimization 15

Example Functions
By convention, we represent the minterms of F by a 1
in the map and leave the entries that contain 0 blank
y
Example 1:

F(x, y, z) = (2, 3, 4, 5)

x 41

1
5

Example 2:

G(x, y, z) = (3, 4, 6, 7)
Learn the locations of the 8
indices based on the variable
order shown

y
0

x 41

1
7
1

2
6

z
Circuit Optimization 16

Combining Squares

By combining squares, we reduce number of literals in

a product term, thereby reducing the gate input cost

On a 3-variable K-Map:
One square represents a minterm with 3 variables
Two adjacent squares represent a term with 2 variables
Four adjacent squares represent a term with 1 variable
Eight adjacent square is the function 1 (no variables)
Circuit Optimization 17

Example: Combining Squares

y

Example:

F = (2, 3, 6, 7)

1
7
1

1
6
1

z
Applying the Minimization Theorem 3 times:

F( x , y , z ) x y z x y z x y z x y z
yz y z
y
Thus the four terms that form a 2 2 square
correspond to the term y.
Circuit Optimization 18

Combining Four Squares

Example Shapes of 4-square Rectangles:
x

z
Circuit Optimization 19

Combining Two Squares

Example Shapes of 2-square Rectangles:

xy

xz

z
yz
Circuit Optimization 20

Simplifying 3-Variable Functions

K-Maps can be used to simplify Boolean functions
Example: find an optimum SOP equation for
F(x, y, z) = (0, 1, 2, 4, 6, 7)

xy
1

F=z+xy+xy

z
1
1

2
6

xy
Circuit Optimization 21

Four-Variable K-Map
wx

yz

00

01

11

10

00 m0 = w x y z m1 = w x y z m3 = w x y z m2 = w x y z

01 m4 = w x y z m5 = w x y z m7 = w x y z m6 = w x y z
11 m12 = w x y z m13 = w x y z m15 = w x y z m14 = w x y z

W
10 m8 = w x y z m9 = w x y z m11 = w x y z m10 = w x y z

X
X

Z
Circuit Optimization 22

4-Variable K-map Terms

4-variable K-maps can have rectangles
corresponding to:
Single square = 4-variable minterm
2 combined squares = 3-variable term
4 combined squares = 2-variable term
8 combined squares = 1 variable term
16 (all) combined squares = constant 1
Circuit Optimization 23

Combining Eight Squares

Examples of 8-square Rectangles:
Y

Z
W

12

13

15

14

11

10

Z
Circuit Optimization 24

Combining Four Squares

Examples of 4-square Rectangles:

XZ

XZ
0

12

13

15

14

11

10

WY

Z
Circuit Optimization 25

Combining Two Squares

Examples of 2-square Rectangles:
XYZ

WXZ
0
1

12

13

15

14

11

10

WYZ

WXZ
Z
Circuit Optimization 26

Simplifying 4-Variable Functions

F(W, X, Y, Z) = (0, 2, 4, 5, 6, 7, 8, 12)
YZ
0

12

13

15

14

11

10

1
WX
W

1
F=WX +YZ +WZ

WZ

Z
Circuit Optimization 27

Product-of-Sum (POS) Simplification

F (W, X, Y, Z) = (1, 2, 3, 9, 10, 11, 13, 14, 15)
F = W Z + W Y + X Z + X Y (G = 8+4 = 12)
F (W, X, Y, Z) = (0, 4, 5, 6, 7, 8, 12) = Y Z + W X
F = Y Z + W X = (Y + Z) (W + X) (G = 4+2 = 6)
F
Y
Y
0

12

13

15

14

1
1

11

1
1

10

X
W

12

13

15

14

11

10

1
1

Circuit Optimization 28

Product-of-Sum Simplification
Step 1: Draw the K-map for F, replacing the 0s of
F with 1s in F and vice versa
Step 2: Obtain a minimal Sum-of-Product (SOP)
expression for F
Step 3: Use DeMorgans Theorem to obtain F = F
The result is a minimal Product-of-Sum (POS)
expression for F
Step 4: Compare the cost of the minimal SOP and
POS expressions to find which one is better
Circuit Optimization 29

Five-Variable K-Maps
For five variable problems, we use two adjacent 4-variable
K-maps that can be visualized to be on top of each other
Each square in the A=0 map is adjacent to the
corresponding square in the A=1 map (e.g. m4 and m20)
A=0
D

A=1
D

16

17

19

18

20

21

23

22

12

13

15

14

28

29

31

30

11

10

24

25

27

26

C
B

Circuit Optimization 30

Example of a Five-Variable K-map

F(A, B, C, D, E) = (0, 1, 8, 9, 16, 17, 22, 23, 24, 25)
F= C D + AB C D
A=0
D
1

12

13

15

14

11

10

A=1
D

16

17

19

18

20

21

23

22

28

29

31

30

24

25

27

26

1
C
B

E
Circuit Optimization 31

Don't Cares in K-Maps

Sometimes a function table or K-map contains entries for
which it is known:
The input values for the minterm will never occur, or
The output value for the minterm is not used

In these cases, the output value need not be defined

Instead, the output value is defined as a don't care
By placing don't cares ( an x entry) in the function table
or map, the cost of the logic circuit may be lowered.
Example: A logic function having the binary codes for the
BCD digits as its inputs. Only the codes for 0 through 9 are
used. The six codes, 1010 through 1111 never occur, so the
output values for these codes are x = dont cares.
Circuit Optimization 32

Example: BCD 5 or More

The map below gives a function F(w,x,y,z) which is
defined as "5 or more" over BCD inputs. With the
don't cares used for the 6 non-BCD combinations:
If the dont cares were treated as 0s we get:
F1 = w x z + w x y + w x y (G = 12)
y
If the dont cares were 1s we get:
00 01 03 02
F2 = w + x z + x y (G = 7 better)
0 1 1 1
The selection of dont cares
depends on which combination
gives the simplest expression

X12 X13 X15 X14

1 8 1 9 X11 X10
z
Circuit Optimization 33

Product-of-Sums Example
Find the optimum POS expression for :
F(A, B, C, D) = (3,9,11,12,13,14,15) + d (1,4,6)
Where d indicates the dont care minterms
Solution: Find F = (0, 2, 5, 7, 8, 10) + d (1,4,6)
F= B D + AB

Optimum POS expression:

1 0 X1

12

X4 1 5 1 7 X6

F = (B + D) (A + B)
Gate input cost (G = 6)

12

13

15

14

18

11

1 10

Circuit Optimization 34

Systematic Simplification
A Prime Implicant is a product term obtained by combining the
maximum possible number of adjacent squares in the map into
a rectangle, with the number of squares equal to a power of 2

A prime implicant is called an Essential Prime Implicant if it is

the only prime implicant that covers one or more minterms

Prime Implicants and Essential Prime Implicants can be

determined by inspection of a K-Map

A set of prime implicants covers all minterms if, for each

minterm of the function, at least one prime implicant in the set
of prime implicants includes the minterm
Circuit Optimization 35

Example of Prime Implicants

Find ALL Prime Implicants
CD
C

BD

1
BD
A

AB

D
AD

BD
1

1
B

BD
A

1
B
1

BC

Only 2 Essential Prime Implicants

Circuit Optimization 36

Prime Implicant Practice

Find all prime implicants for
F(A, B, C, D) = (0,2,3,8,9,10,11,12,13,14,15)
BD
3 prime implicants:

A, B C, B D
All 3 prime
implicants are
A
essential
A

1
1

C
0

12

13

15

14

1
1

1
1

11

1
1

BC
B

10

Circuit Optimization 37

Optimization Algorithm
Find all prime implicants
Include all essential prime implicants in the solution
Select a minimum cost set of non-essential prime
implicants to cover all minterms not yet covered
Prime implicant selection rule:
Minimize the overlap among prime implicants
In particular, in the final solution, make sure that each
prime implicant selected includes at least one minterm not
included in any other prime implicant selected
Circuit Optimization 38

Selection Rule Example

Simplify F(A, B, C, D) given on the K-map
C
1

1
1

A
1

Essential

Selected

1
D

1
D

Minterms covered by essential prime implicants

Circuit Optimization 39

Selection Rule Example with Don't Cares

Simplify F(A, B, C, D) given on the K-map.
C

1
A

x
1

1
D

Essential

Selected

B
A

x
1

D
Minterms covered by essential prime implicants
Circuit Optimization 40

Other Gate Types

Why?
Low cost implementation
Useful in implementing Boolean functions
Convenient conceptual representation

Gate classifications
Primitive gate - a gate that can be described using a
single primitive operation type (AND or OR) plus
optional inversion(s).
Complex gate - a gate that requires more than one
primitive operation type for its description

Primitive gates will be covered first

Additional Gates and

NAND Gate
The basic NAND gate has the following symbol and
truth table:
X Y NAND
AND-Invert (NAND) Symbol:
X
Y

XY

0
0
1
1

0
1
0
1

1
1
1
0

NAND represents NOT AND. The small bubble

circle represents the invert function
The NAND gate is implemented efficiently in CMOS
technology in terms of chip area and speed
Additional Gates and

NAND Gate: Invert-OR Symbol

Applying DeMorgan's Law: Invert-OR = NAND
X
Y

X + Y = X Y = NAND

This NAND symbol is called Invert-OR

Since inputs are inverted and then ORed together

AND-Invert & Invert-OR both represent NAND gate

Having both makes visualization of circuit function easier

Unlike AND, the NAND operation is NOT associative

(X NAND Y) NAND Z X NAND (Y NAND Z)
Additional Gates and

The NAND Gate is Universal

NAND gates can implement any Boolean function
NAND gates can be used as inverters, or to
implement AND / OR operations
A NAND gate with one input is an inverter
AND is equivalent to NAND with inverted output
X
Y

XY

XY

X
Y

XY

OR is equivalent to NAND with inverted inputs

X
Y

X+Y

X
Y

X
Y

X Y= X+Y
Additional Gates and

NOR Gate
The basic NOR gate has the following symbol and
truth table:
X Y NOR
OR-Invert (NOR) Symbol:
0 0 1
0 1 0
X
1 0 0
X+Y
1 1 0
Y
NOR represents NOT OR. The small bubble circle
represents the invert function.
The NOR gate is also implemented efficiently in
CMOS technology in terms of chip area and speed
Additional Gates and

NOR Gate: Invert-AND Symbol

The Invert-AND symbol is also used for NOR
X
Y

X Y = X + Y = NOR

This NOR symbol is called Invert-AND, since inputs are

inverted and then ANDed together
OR-Invert & Invert-AND both represent NOR gate
Having both makes visualization of circuit function easier

Unlike OR, the NOR operation is NOT associative

(X NOR Y) NOR Z X NOR (Y NOR Z)

Additional Gates and

The NOR Gate is also Universal

NOR gates can implement any Boolean function
NOR gates can be used as inverters, or to implement
AND / OR operations
A NOR gate with one input is an inverter
OR is equivalent to NOR with inverted output
X
Y

X+Y

X+Y

X
Y

X+Y

AND is equivalent to NOR with inverted inputs

X
Y

XY

X
Y

X + Y= X Y

Y
Additional Gates and

NANDNAND Implementation
Consider the Following SOP Expression:

F XZ WY Z
A 2-level AND-OR circuit can be converted easily
to a NAND-NAND implementation
X
Z
W
Y
Z

X
Z
W
Y
Z

X
Z

W
Y
Z
F

Two successive bubbles

on the same line cancel
each other

Additional Gates and

NORNOR Implementation
Consider the Following POS Expression:

F ( X Z )(W Y Z )
A 2-level OR-AND circuit can be converted easily
to a NOR-NOR implementation
X
Z

W
Y
Z
X
Z
W
Y
Z

X
Z

W
Y
Z

Two successive bubbles

on the same line cancel
each other

F
Additional Gates and

Other Types of 2-Level Circuits

Other useful types of 2-level circuits:
AND-OR-INVERT = AND-NOR = NAND-AND
OR-AND-INVERT = OR-NAND = NOR-OR

AND-NOR Function:

F XY W X Z

AND-NOR
X
Y
W
X
Z

NAND-AND
F

X
Y
W
X
Z

X
Y

W
X
Z

Similarly, OR-NAND circuits can be converted to NOR-OR

Additional Gates and
Circuits 50

Other Types of 2-Level Circuits (2)

Other useful types of 2-level circuits:
AND-OR-INVERT = AND-NOR = NAND-AND
OR-AND-INVERT = OR-NAND = NOR-OR

OR-NAND Function:

F ( X Y )(W X Z )

OR-NAND
X
Y
W
X
Z

NOR-OR
F

X
Y
W
X
Z

X
Y
W
X
Z

Additional Gates and

Circuits 51

Other Types of 2-Level Circuits (3)

Circuit Optimization 52

Other Types of 2-Level Circuits (4)

Circuit Optimization 53

Exclusive OR / Exclusive NOR

The eXclusive-OR (XOR) function is an important
Boolean function used extensively in logic circuits
The XOR function may be:
Implemented directly as an electronic circuit (true gate)
Implemented by interconnecting other gate types (XOR is
used as a convenient representation)

The eXclusive-NOR (XNOR) function is the

complement of the XOR function
XOR and XNOR gates are complex gates
Additional Gates and

XOR / XNOR Tables and Symbols

XOR

XNOR
X Y

0 0

XY
0

0 0

XY
1

0 1

0 1

1 0

1 0

1 1

1 1

X Y

XOR Symbol

XNOR Symbol

The XNOR is also denoted as equivalence

Additional Gates and

Uses for XOR / XNOR

SOP Expressions for XOR/XNOR:
The XOR function is:
XY XYXY
The eXclusive NOR (XNOR) function, know also as
equivalence is:
XY XYXY

Uses for the XOR and XNORs gate include:

Adders/subtractors/multipliers
Counters/incrementers/decrementers
Parity generators/checkers

Strictly speaking, XOR and XNOR gates do no

exist for more that two inputs. Instead, they are
replaced by odd and even functions.
Additional Gates and

XOR Implementations
SOP implementation

NAND only

for XOR:

implementation

X Y= XY+ XY

for XOR:

X Y

X Y

Additional Gates and

XOR / XNOR Identities

X0 X

X 1 X

XX 0

XX 1

XY YX
XY XY= X Y
( X Y) Z X ( Y Z ) = X Y Z
( X Y) Z X ( Y Z ) = X Y Z

XOR and XNOR are associative operations

Additional Gates and

Odd Function
The XOR function can be extended to 3 or more variables
For 3 or more variables, XOR is called an odd function
The function is 1 if the total number of 1s in the inputs is odd

X Y Z XYZ XYZ XYZ XYZ

YZ
X

00

11

0
1

01

10

1
1

X Y Z

YZ

00

WX

1
1

10

1
1

11
10

11

00
01

01

1
1

W X Y Z

Additional Gates and

Odd and Even Functions

The 1s of an odd function correspond to inputs
with an odd number of 1s
The complement of an odd function is called an
even function
The 1s of an even function correspond to inputs
with an even number of 1s
Implementation of odd and even functions use trees
made up of 2-input XOR or XNOR gates
Additional Gates and

Odd/Even Function Implementation

Design a 3-input odd function with 2-input XOR:
3-input odd function:
F = (X Y) Z

X
Y
Z

Design a 4-input even function with 2-input XOR and

XNOR gates:
W
4-input even function:
X
F
Y
F = (W X) (Y Z)
Z
Additional Gates and

Parity Generators and Checkers

A parity bit added to n-bit code produces (n+1)-bit
code with an odd (or even) count of 1s
Odd Parity bit: count of 1s in (n+1)-bit code is odd
So use an even function to generate the odd parity bit

Even Parity bit: count of 1s in (n+1)-bit code is even

So use an odd function to generate the even parity bit

To check for odd parity

Use an even function to check the (n+1)-bit code

To check for even parity

Use an odd function to check the (n+1)-bit code
Additional Gates and

Parity Generator & Checkers

n-bit code Parity

Sender

Generator

(n+1)-bit
code

Parity
Checker

Error

Receiver

Design an even parity generator and checker for 3-bit codes

Solution: Use 3-bit odd function
X
Y
to generate even parity bit
Use 4-bit odd function to check
Z
X
for errors in even parity codes
Operation: (X,Y,Z) = (0,0,1) gives Y
(X,Y,Z,P) = (0,0,1,1) and E = 0
Z
If Y changes from 0 to 1 between
P
generator and checker, then E = 1 indicates an error
Additional Gates and