MOS fundamentals

Metal-oxide-semiconductor FET is the most important device

in modern microelectronics.
In this chapter, we will study:
Ideal MOS structure electrostatics
MOS band diagram under applied bias
Gate voltage relationship
I-V characteristics, transfer characteristics
Enhancement and depletion MOS
Channel length modulation, body effect
Biasing of MOSFETs, capacitances in MOS .
1

MOS Transistor
An MOS structure is created by superimposing several
layers of conducting, insulating, and transistor forming
materials to create sandwich like structure shown in fig 1.
A MOS transistor can be modeled as a 3-terminal device
that acts like a voltage controlled resistance. As suggested
by Figure 2 an input voltage applied to one terminal
controls the resistance between the remaining two
terminals.
In digital logic applications, a MOS transistor is operated
so its resistance is always either very high (and the
transistor is off) or very low (and the transistor is on).

Fig. 1
3

MOS Transistor

Figure 1 The MOS transistor as a voltage-controlled

resistance.

MOS Transistor
The basic electrical properties of the semiconductor (Si), the
equilibrium concentration of mobile carriers in Si ,always obeys the
Mass Action Law given by,

Assuming that the substrate is uniformly doped with an accepter

concentration NA, the Equilibrium electron and hole concentration
in the P type substrate.

Energy Band Diagram For P-Type Silicon

Energy Band Diagram For P-Type Silicon

Fermi Potential

For P-type Fermi Potential

For n-type Fermi Potential

Energy Band Diagram For P-Type Silicon

Electron affinity: It is the potential difference between

conduction band level and vacuum (free space) level.
It is denoted by qX.
Work Function: The energy required for an electron to move
from Fermi level into free space.

Energy Band Diagram of the components of MOS

Energy Band Diagram of the Combined MOS

System

10

MOS Transistor
Compared to the bipolar junction transistor (BJT), the MOS
transistor occupies a relatively smaller silicon area, and its
fabrication used to involve fewer processing steps.
There are two types of MOS transistors, n-channel and pchannel; the names refer to the type of semiconductor material
used for the resistance-controlled terminals. The circuit symbol
for an n-channel MOS (NMOS) transistor is shown in Figure 2.

Figure 2 Circuit symbol for an n-channel MOS (NMOS) transistor.

11

MOS Transistor
The terminals are called gate, source, and drain. The
voltage from gate to source (Vgs) in an NMOS transistor is
normally zero or positive. If Vgs = 0, then the resistance
from drain to source (Rds) is very high, in the order of a
megohm (106 ohms) or more. As we increase Vgs (i.e.,
increase the voltage on the gate), Rds decreases to a very
low value, 10 ohms or less in some devices.
In an n-MOS transistor the majority carriers are electrons.
A positive voltage applied on the gate with respect to the
substrate enhances the number of electrons in the channel
and hence increases the conductivity of the channel.

12

MOS system under External Bias

Accumulation Region:

13

MOS system under External Bias

Depletion Region:

14

Energy band diagrams and charge density diagrams

describing MOS capacitor in p-type Si

15

MOS system under External Bias

The thickness xd of Depletion Region:
Assume mobile hole charge in thin horizontal layer parallel to
the surface is
The change in surface potential

Integrating along with vertical dimension

16

MOS system under External Bias

Thus depth of depletion region

And the depletion region charge density,

17

MOS system under External Bias

Inversion Region:

18

MOS system under External Bias

The maximum depletion depth xdm

19

Structure and Operation of MOSFET

20

Circuit symbol of n-type MOSFET

21

Circuit symbol of p-type MOSFET

22

Formation of depletion region in n-type

enhancement MOSFET

23

Band diagram for MOS underneath gate

24

Formation of inversion region in n-type

enhancement MOSFET

25

Threshold Voltage
Work function difference is

26

Threshold Voltage

27

Threshold Voltage

28

MOSFET Operation

29

MOSFET Operation

30

MOSFET Operation

31

MOSFET Current-Voltage Characteristics

32

MOSFET Current-Voltage Characteristics

Gradual Channel Approximation

33

MOSFET Current-Voltage Characteristics

Boundary Conditions for channel voltage Vc(y) are:

Now assume that the entire channel region between the source and
The drain is inverted,

34

MOSFET Current-Voltage Characteristics

Let QI(y) be the total mobile electron charge in the surface inversion
layer then,

Now consider the incremental resistance dR of the differential

channel segment shown in fig (a) then,

35

MOSFET Current-Voltage Characteristics

Fig (a)
36

MOSFET Current-Voltage Characteristics

Applying Ohms law for this segment yields the voltage drop
along the incremental segment dy, in the y direction.

This equation can be integrated along the channel,

37

MOSFET Current-Voltage Characteristics

Now put the value of QI(y), we get

Assume that the channel voltage Vc is the only variable, the

Drain current is found as follows.

38

MOSFET Current-Voltage Characteristics

This current equation can be rewritten as

Eq. -1

Where the parameters k and k are defined as

39

MOSFET Current-Voltage Characteristics

The drain current equation-1 has been derived under following
assumptions,

Which guarantee that entire channel region between source and

drain is inverted. This condition is corresponds to the linear
operating region for the MOSFET.
Beyond the linear region boundary MOS transistor is assumed
To be in saturation.
40

MOSFET Current-Voltage Characteristics

Boundary for Saturation are

In Saturation region VDS = VDSAT , the saturation current can be found

by substituting in eq. -1

41

MOSFET ID-VGS Transfer Characteristics

42

Channel Length Modulation

Consider the inversion layer charge QI (y), that represents the total
electron charge on the surface, the inversion layer charge at the
source end of the channel,

the inversion layer charge at the drain end of the channel,

Now at the edge of the saturation,

43

Channel Length Modulation

In saturation region inversion layer charge at drain end becomes
Zero,

This condition is called pinched-off at the drain end at y=L.

If VDS > VDSAT , the large portion of the channel becomespinched-off .
This is called channel length modulation. Under this condition length
of the channel is called effective channel length.
Where L is the length of the channel segment with QI = 0
shown in fig (b)

44

Channel Length Modulation

Fig (b)

45

Channel Length Modulation

Hence the pinch-off point moves from drain end of the channel
towards source with increase in VDS the remaining portion is in
depletion mode. The channel voltage at L<y<L ,

The drain current under this condition

46

Channel Length Modulation

Put L = L - L, then saturation current can be rewrite

But
To simplify the analysis even further, we will use following
Empirical relation between L and VDS

47

Channel Length Modulation

Here is an empirical model parameter and is called channel

length modulation coefficient .
Assume . VDS << 1, the saturation current can be written

48

Channel Length Modulation

49

Body Effect
The threshold voltage is not constant with respect to the VSB .
This is known as substrate bias effect or body effect.

Where is called substrate bias or body effect coefficient.

50

Terminal Voltages and Currents for N,P Channel

MOSFET

51

Current Voltages Equation for N- Channel MOSFET

52

Current Voltages Equation for P- Channel MOSFET

53

MOSFET Capacitances

54

MOSFET Capacitances

55

MOSFET Capacitances
Oxide Related Capacitances:

56

MOSFET Capacitances

57

MOSFET Capacitances
Cut Off Mode: Cgs = Cgd = 0 and

58

MOSFET Capacitances
Linear Mode: Cgb = 0 and

59

MOSFET Capacitances
Saturation Mode: Cgd = Cgb = 0 and

60

MOSFET Capacitances

61

MOSFET Capacitances

62

MOSFET Capacitances
Junction Capacitances (Csb and Cdb):

Fig-1

63

MOSFET Capacitances

64

MOSFET Capacitances
The depletion region thickness (xd):

Where 0 is built in potential

The depletion region charge Qj

Eq. 1
Here A is the junction area.

65

MOSFET Capacitances
The junction capacitances associated with the depletion region
is defined as

Differentiating eq.-1 with respect to V we get expression for

Junction capacitance
Eq-2
In general form
Eq-3

66

MOSFET Capacitances
The parameter m in eq-3 is called grading coefficient and
Cj0 is the zero bias junction capacitance per unit area.

The equivalent large signal capacitance can be defined as

Eq-4
Bu substituting eq-3 into eq-4, we obtain

Eq-5
67

MOSFET Capacitances
For a special case of abrupt p-n junction eq-5 becomes
Eq-6

This equation can be written in a simpler form

Where Keq is the dimension less coefficient is called voltage

equivalence factor (0 < Keq < 1)

68

MOSFET Capacitances
Assuming that NA (sw) is the sidewall doping density, the
zero bias junction capacitance per unit area Cj0 (sw).

Where 0sw is built in potential. Since all the sidewalls have a same
depth xj , the zero bias junction capacitance per unit length

69

MOSFET Capacitances
The voltage equivalence factor Keq (sw)

The equivalent large signal junction capacitance Ceq (sw) for a

sidewall of length ( perimeter) P can be calculated as

70

MOSFET Capacitances

71

MOSFET Capacitances

72

MOS Transistor

73

nMOS Enhancement transistor

N-channel
MOSFET
(NMOS)
uses p-type
substrate
electrons
P-Si
74

MOSFET operation
ID

Pinch-off

VG3
VG2
VG1

VG3 > VG2 > VG1

VD

When a positive voltage VG is applied to the gate relative to the

substrate, mobile negative charges (electrons) gets attracted to Sioxide interface. These induced electrons form the channel.
For a given value of VG, the current ID increases with VD, and
finally saturates.

75

Ideal MOS capacitor

Let us consider a simple MOS capacitor and call it ideal
Oxide has zero charge, and no current can pass through it.
No charge centers are present in the oxide or at the oxidesemiconductor interface.
Semiconductor is uniformly doped
M = S
= + (EC EF)FB

76

Equilibrium energy band diagram for an ideal MOS

structure

77

Effect of an applied bias

Let us ground the semiconductor and start applying different
voltages, VG, to the gate
VG can be positive, negative or zero with respect to the
semiconductor
EF, metal EF, semiconductor = q VG
(Since electron energy = q V, when V < 0, electron energy
increases)
Since oxide has no charge, d Eoxide / dx = / = 0; i.e. the Efield inside the oxide is constant.

78

Consider p-type Si, apply VG < 0

' m

Accumulation
of holes
EC

qVG

Ei
EV EFs

E oxide
0
x

Negative voltage
attracts holes to
the Si-oxide interface.
This is called
accumulation condition.
Ei EF should
increases near the
surface of Si.

1 Ei
E oxide const.
q x

The oxide energy band has constant slope as shown. No current

flows in Si EF in Si is constant.

79

Accumulation condition, VG < 0, p-type Si

VG < 0

p-type Si

O
E

charge density

small
+

Sheet of
electrons

Sheet of
holes

Accumulation of holes near

silicon surface, and electrons
near the metal surface.
Similar to a parallel plate
capacitor structure.

80

Consider p-type Si, apply VG > 0 (Depletion condition)

Finite
depletion layer
width

positive

Depletion

+
+

EC
Ei
EFs
EV

EFM
M

----

----

negative

81

Consider p-Si, apply VG >> 0 (Inversion condition)

E

Immobile
acceptors

+
+

EC

+
+

Ei
EFS

-------------

EV

EFM E

Mobile
electrons

FM

x
82

Inversion condition
If we continue to increase the positive gate voltage, the bands at
the semiconductor bends more strongly. At sufficiently high
voltage, Ei can be below EF indicating large concentration of
electrons in the conduction band.
We say the material near the surface is inverted. The inverted
layer is not gotten by doping, but by applying E-field. Where did
we get the electrons from?

When Ei(surface) Ei(bulk) = 2 [EF Ei(bulk)], the condition is

start of inversion, and the voltage VG applied to gate is called VT
(threshold voltage). For VG > VT, the Si surface is inverted.
83

Energy band
diagrams and
charge density
diagrams
describing MOS
capacitor in n-type
Si

84

Energy band diagrams and charge density diagrams

describing MOS capacitor in p-type Si

85

Example 1
Construct line plots that visually identify the voltage ranges
corresponding to accumulation, depletion and inversion in ideal ntype Si (i.e. p-channel) and p-type Si (i.e. n-channel) MOS devices.
Answer:

86