Lecture 1-1

Design Abstraction
Pradondet Nilagupta
[email protected]
Department of Computer Engineering
Kasetsart University

Acknowledgement
This

lecture note has been summarized from

lecture note on Introduction to VLSI Design,
VLSI Circuit Design all over the world. I cant
remember where those slide come from.
However, Id like to thank all professors who
create such a good work on those lecture
notes. Without those lectures, this slide cant
be finished.

The VLSI design process

May

be part of larger product design.

Major levels of abstraction:
specification;
architecture;
logic

design;
circuit design;
layout.

Dealing with complexity

Divide-and-conquer:

limit the number of

components you deal with at any one time.
Group several components into larger
components:
transistors

form gates;
gates form functional units;
functional units form processing elements;
etc.

Hierarchical name
Interior

view of a component:

components

Exterior

and wires that make it up.

view of a component = type:

body;
pins.

cout
a
b

Full
adder

sum

cin
5

Instantiating component types

Each

instance has its own name:

add1

(type full adder)

add2 (type full adder).
Each

instance is a separate copy of the type:

cout

Add1.a

a Add1(Full
adder)
b

Add2.a
sum

a Add2(Full
adder)
b

cin

sum

cin
6

A hierarchical logic design

box1

box2

z
7

Net lists and component lists

Net list:
net1: top.in1 in1.in
net2: i1.out xxx.B
topin1: top.n1 xxx.xin1
topin2: top.n2 xxx.xin2
botin1: top.n3 xxx.xin3
net3: xxx.out i2.in
outnet: i2.out top.out

Component list:
top: in1=net1 n1=topin1
n2=topin2 n3=topine
out=outnet
i1: in=net1 out=net2
xxx: xin1=topin1
xin2=topin2 xin3=botin1
B=net2 out=net3
i2: in=net3 out=outnet

Component hierarchy

top

i1

xxx

i2

Hierarchical names
Typical

hierarchical name:

top/i1.foo

component

pin

10

Layout and its abstractions

Layout

for dynamic latch:

11

Stick diagram

12

Transistor schematic

13

Mixed schematic

inverter

14

Levels of abstraction
Specification:

function, cost, etc.

Architecture: large blocks.
Logic: gates + registers.
Circuits: transistor sizes for speed, power.
Layout: determines parasitics.

15

Circuit abstraction
Continuous

voltages and time:

16

Digital abstraction
Discrete

levels, discrete time:

17

Register-transfer abstraction
Abstract

components, abstract data types:

0010

+
0001

0011

0100

18

Top-down vs. bottom-up design

Top-down
Create

design adds functional detail.

lower levels of abstraction from upper

levels.
Bottom-up

design creates abstractions from

low-level behavior.
Good design needs both top-down and
bottom-up efforts.

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Design abstractions
English
Executable
program

function

Sequential
machines
Logic gates

specification
behavior

Throughput,
design time

registertransfer

Function units,
clock cycles

logic

cost

Literals,
logic depth

transistors

circuit

nanoseconds

rectangles

layout

microns
20

Design validation
Must

check at every step that errors havent

been introduced-the longer an error remains,
the more expensive it becomes to remove it.
Forward checking: compare results of lessand more-abstract stages.
Back annotation: copy performance numbers
to earlier stages.

21

Manufacturing test
Not

the same as design validation: just

because the design is right doesnt mean that
every chip coming off the line will be right.
Must quickly check whether manufacturing
defects destroy function of chip.
Must also speed-grade.

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VLSI Design Cycle

VLSI Design Cycle (1/9)

System Specification

Circuit Design

Architectural Design

Physical Design

Functional Design

Fabrication

Logic Design

Packaging

24

VLSI Design Cycle (2/9)

System Specification Specification of the
size, speed, power and functionality of the
VLSI system.
Architectural Design Decisions on the
architecture, e.g., RISC/CISC, # of ALUs,
pipeline structure, cache size, etc. Such
decisions can provide an accurate estimation
of the system performance, die size, power
consumption, etc.
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VLSI Design Cycle (3/9)

Functional Design Identify main functional
units and their interconnections. No details of
implementation.

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VLSI Design Cycle (4/9)

Logic Design Design the logic, e.g.,
boolean expressions, control flow, word
width, register allocation, etc. The outcome is
called an RTL (Register Transfer Level)
description. RTL is expressed in a HDL
(Hardware Description Language), e.g.,
VHDL and Verilog.

X = (AB+CD)(E+F)
Y= (A(B+C) + Z + D)
27

VLSI Design Cycle (5/9)

Circuit Design Design the circuit including
gates, transistors, interconnections, etc. The
outcome is called a netlist.

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VLSI Design Cycle (6/9)

Net list:
net1: top.in1 in1.in
net2: i1.out xxx.B
topin1: top.n1 xxx.xin1
topin2: top.n2 xxx.xin2
botin1: top.n3 xxx.xin3
net3: xxx.out i2.in
outnet: i2.out top.out

Component list:
top: in1=net1 n1=topin1
n2=topin2 n3=topine
out=outnet
i1: in=net1 out=net2
xxx: xin1=topin1
xin2=topin2 xin3=botin1
B=net2 out=net3
i2: in=net3 out=outnet

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VLSI Design Cycle (7/9)

Component hierarchy
top

i1

xxx

i2

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VLSI Design Cycle (8/9)

Physical Design Convert the netlist into a
geometric representation. The outcome is
called a layout.

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VLSI Design Cycle (9/9)

Fabrication Process includes lithography,
polishing, deposition, diffusion, etc., to
produce a chip.
Packaging Put together the chips on a PCB
(Printed Circuit Board) or an MCM (Multi-Chip
Module)

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VLSI Design Cycle

Netlist

System Specification

Physical
Design

Architectural
Design

Architectural
Specification
Functional
Design

Timing & relationship

between functional units
Logic
Design

RTL in HDL

Layout
Circuit Design
or
Logic Synthesis

Fabrication

Chips
Packaging

Packaged and
tested chips

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Physical Design Cycle (1/6)

Circuit Partitioning
Floorplanning & Placement
Routing
Layout Compaction
Extraction and Verification
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Physical Design Cycle (2/6)

Circuit Partitioning Partition a large circuit
into sub-circuits (called blocks). Factors like
#blocks, block sizes, interconnection between
blocks, etc., are considered.

35

Physical Design Cycle (3/6)

Floorplanning Set up a plan for a good
layout. Place the modules (modules can be
blocks, functional units, etc.) at an early stage
when details like shape, area, I/O pin
positions of the modules, , are not yet
fixed.

Deadspace
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Physical Design Cycle (4/6)

Placement Exact placement of the
modules (modules can be gates, standard
cells, etc.) when details of the module design
are known. The goal is to minimize the delay,
total area and interconnect cost.

Feedthrough
Standard cell type 1
Standard cell type 2
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Physical Design Cycle (5/6)

Routing Complete the interconnections
between modules. Factors like critical path,
clock skew, wire spacing, etc., are
considered. Include global routing and
detailed routing.

Feedthrough

Type 1 standard cel1

Type 2 standard cell
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Physical Design Cycle (6/6)

Compaction Compress the layout from all
directions to minimize the total chip area.
Verification Check the correctness of the
layout. Include DRC (Design Rule Checking),
circuit extraction (generate a circuit from the
layout to compare with the original netlist),
performance verification (extract geometric
information to compute resistance,
capacitance, delay, etc.)
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Design Styles (1/2)

Full-Custom
Some

ASICs

(possibly all) logic cells are customized

and
all mask layers are customized

Semicustom

ASICs

All

logic cells are predesigned (defined in cell

library) and some (possibly all) of the mask layers
are customized
Types:
Standard-cell based and Gate-array-based ASICs

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Design Styles (2/2)

Programmable

ASICs

All logic cells are predesigned and

none of the mask layers are customized
Types: PLD (Programmable Logic Device) and
FPGA (Field Programmable Gate Array)

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Full-custom ASICs (1/3)

Engineers

design some or all of the logic

cells, circuits, or layout specifically for one
ASIC
Full-custom

ICs are the most expensive

to manufacture and to design
Manufacturing lead time (the time it takes just to
make an IC not including design time) is
typically 8 weeks

42

Full-custom ASICs (2/3)

When

does it make sense?

there are no suitable existing cell libraries available

existing logic cells are not fast enough
logic cells are not small enough
logic cells consume too much power
ASIC is so specialized that
some circuits must be custom designed

Trends:

fewer and fewer full-custom ICs are

being designed (excluding mixed analog/digital
ASICs)
43

Full Custom Design (3/3)

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Standard-Cell-Based ASICs (1/5)

Cell-Based ASIC (CBIC) uses predesigned cells

(AND, OR gates, multiplexers, flip-flops, ...)
Standard-cell areas are built of rows of standard cells
Standard-cell areas can be used in combination with larger
predesigned cells (microcontrollers, or even
microprocessors), known as megacells
A cell-based
ASIC (CBIC) die
with a single
standard-cell
area combined
with 4 fixed
blocks
45

Standard-Cell-Based ASICs(2/5)
Characteristics
custom

blocks can be embedded;

ASIC designer defines only the placement of the
standard cells and the interconnect in a CBIC
standard cells can be placed anywhere on a
silicon =>
all mask layers of a CBIC are customized
manufacturing lead time is 8 weeks

46

Standard-Cell-Based ASICs (3/5)

Advantages

designers save time, money, and reduce risks using a

predesigned, pretested, and precharacterized standard-cell
library
standard cells in the library are constructed using fullcustom;
each standard cell can be optimized individually
(for example, to maximize speed, minimize area, etc);

Disadvantages

time or expense of designing or buying the standard-cell

library
time needed to fabricate all layers of the ASIC for each new
design
47

Standard-Cell-Based ASICs(4/5)

Standard-cells are designed

to fit horizontally together to form rows
Internal construction of a cell

- 25 microns wide (lambda is 0.25)

- AB: abutment box
- BB: bounding box
- Power supplies: VDD, GND
- Each different shaded and
labeled pattern represents a
different layer
- Connections: A1, B1, Z
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Standard-Cell-Based ASICs (5/5)

Routing

the CBIC

- Interconnections

between cells use

spaces (called
channels) between rows
- 2 separate layers of
metal interconnect
(metal1 and metal2)
running at right angles
to each other
- Feedthrough: refers
either to the piece of
metal that is used to
pass a signal through a
cell or to a space in a
cell waiting to be used
as a feedthrough
49

Gate-Array-Based ASICs

In gate-array-based ASIC
transistors are predefined on the silicon wafer
Base cell the smallest element that is replicated
Base array the predefined pattern of transistors
Masked Gate Array (MGA): only layers which define
the interconnect between transistors are defined by
the designer using custom masks
Designer chooses from a gate-array library
predesigned and precharacterized logic cells (often
called macros)

50

Gate-Array-Based ASICs (1/4)

Since only metal interconnections are unique for MGA,

we can use prefabricated wafers
(with completed transistor layers)
the turnaround time is reduced to a few days or at
most a couple of weeks
the costs for all the initial prefabrication steps for MGA
are shared for each consumer => the cost of an MGA
is reduced compared to FC and CBIC
Types: Channeled, Channelless, and Structured Gate
Array
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Gate-Array-Based ASICs (2/4)

Channeled gate array

we leave space between the rows of transistors for wiring

Characteristics

only interconnect is customized

the interconnect uses predefined spaces between rows
manufacturing lead time is between 2 days and 2 weeks

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Gate-Array-Based ASICs (3/4)

Channelless gate array (sea-of-gates or SOG)

there are no predefined areas set aside

for routing between cells
we customize the contact layer that
defines the connections between metal1 and transistors
when use area of transistor for routing,
do not make any contacts to the device underneath

Characteristics

only some (the top few) mask layers

are customized the interconnect
manufacturing lead time is
between 2 days and 2 weeks

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Gate-Array-Based ASICs (4/4)

Structured gate array or embedded gate array

combines features of CBIC and MGA

motivation: MGA has only fixed gate-array base cell;
difficult and inefficient implementation of memory
we set aside some IC area and dedicate it to a specific function
(contain different cells, more suitable for building memory cells,
for example, or complete block, such as a microcontroller)
Characteristics
only some (the top few) mask layers
are customized the interconnect
custom blocks can be embedded
manufacturing lead time is
between 2 days and 2 weeks
problem: embedded function is fixed

54

Programmable Logic Devices(1/2)

PLDs

standard ICs, available in standard configurations

sold in high volume to many different customers
PLDs may be configured or programmed to create
a part customized to specific application

Characteristics

no customized mask layers or logic cells

fast design turnaround
a single large block of programmable interconnect
a matrix of logic macrocells that usually consists of
programmable array logic followed by a flip-flop or latch

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Programmable Logic Devices(2/2)

Types of PLDs

PROM: uses metal fuse that can be blown permanently)

EPROM: used programmable MOS transistors whose
characteristics are altering by applying a high voltage
PAL Programmable Array Logic
programmable AND logic array or AND plane,
and fixed OR plane
PLA Programmable Logic Array
programmable AND plane
followed by programmable OR plane

Depending on how
the PLD is programmed
erasable PLD (EPLD)
mask-programmed PLD
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Field-Programmable Gate
Arrays (FPGA)

FPGA

a step above the PLD in complexity;

it is usually larger and more complex than a PLD
rapidly growing in importance

Characteristics

none of mask layers are customized

a method for programming basic cells
and the interconnect
the core is regular array
of programmable basic logic cells
(combinational + sequential)
a matrix of programmable interconnect
that surrounds the basic cells
programmable I/O cells around the core
design turnaround is a few hours
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Economics of ASICs

Goal

Warning!

discuss the economics of using ASICs in a product and

compare the most popular types of ASICs:
an FPGA, an MGA, and a CBIC
costs change rapidly and IC industry is notorious for
keeping its costs, prices, and pricing strategy closely
guarded secrets, so the numbers we will use to illustrate
the different components of cost are approximate

Part cost

vary enormously: from a few dollars to several hundreds

FPGAs are more expensive per gate than MGAs
MGAs are more expensive per gate than CBICs
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