AXI_ASSERTIONS
Madhusudhana Reddy
Mindlance Technologies
Agenda
Protocol with assertions
Assertions points with protocol
AXI Protocol with Assertions
Protocol with Assertions
Specifications
Normal functionality
Features
Relation bw Inputs
Relation bw Outputs
Input & Output Relations
Legal & Illegal scenarios
Combination of one to all
Warnings
Error Scenarios
3
Assertions development areas
Global signals
Reset of DUT
Default values
Range of values ( Input & Output)
Signal transitions
State transitions
Reserved values
Assertion usage in DV
Part of assertions
Valid signal assertion
Continue
Property dut_on(
@(posedge ACLK ) ARESETn |=> VALID );
Endproperty
Reset
The AXI protocol includes a single active LOW reset
signal, ARESETn. The reset signal can be asserted
asynchronously, but deassertion must be synchronous
after the rising edge of ACLK.
Property reset_sig(clk,ARESETn);
@(posedge clk) !ARESETn|=>ARESETn[*1:$] ##1 !
ARESETn;
endproperty
10
Reset with READY AND VALID SIGNALS
During reset the following interface requirements apply:
A master interface must drive ARVALID, AWVALID,
and WVALID LOW
A slave interface must drive RVALID and BVALID LOW.
11
Property Rst_rv(
@(posedge ACLK) !ARESETn |-> (
AWVALID==0 &&
WVALID==0 &&
ARVALID==0 &&
BVALID== 0
)
)
Assert_Rst_rv: assert property( Rst_rv)
12
VALID CONTROL & ADDRESS DATA
13
VALID Control information
Property valid_data(
@(posedge ACLK) AWVALID |-> (
$stable(AWID) &&
$stable(AWLEN) &&
$stable(AWPROT)
)
)
14
15
16
17
18
Default value checking
assert property ( disable iff( !ARESETn )
a==x &&
b==y &&
c==$past(c)
);
19
Data bus width
Data bus(Read,write), that can be 8, 16, 32, 64, 128,
256, 512, or 1024 bits wide
Assert property (
@(posedge ACLK) ($countones(DATABUS_WIDTH)==1 ||
$countones(DATABUS_WIDTH)==1)
)
20
AWLENGTH min and max values
property xxx_range(int min,int max);
@(posedge ACLK)
AWVALID->( AWLEN>=min && AWLEN <=max);
Endproperty
Range_assert:assert property(xxx_range(0,15));
21
Valid transaction
property valid_trans(valid,ready);
@(posedge ACLK)
(valid && ready) ;
Endproperty
22
Inside
Property range_inside;
@(posedge ACLK) arlen inside{1,16};
Endproperty
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ERROR
Except (@(posedge ACLK) WID=AWID ) $error(IDs
are mismatch)
24
Property valid_check(
@(posedge ACLK)
ARVALID|->$stable(ARADDR)
Endpropoerty
Assert_valid_check:assert property ( valid_check);
25
Property valid_check(
@(posedge ACLK) (ARVALID==1 && ARREADY==1) |>$stable(ARADDR)
Endpropoerty
Assert_valid_check:assert property ( valid_check);
26
Property Rdata_check(
@(posedge ACLK) (RVALID==1 && RREADY==1)
|->$stable(RDATA)
Endpropoerty
Assert_rdata_check:assert property
( Rdata_check);
27
Burst_Completion_check
Property last_tr_check(
@(posedge ACLK) (RVALID==1 && RREADY==1
&& RLAST==1) |->$stable(RDATA)
Endpropoerty
Assert_rdata_check:assert property
( last_tr_check);
28
Property total_tr(
@(posedge ACLK)
(ARADDR && ARVALID) |=> ##3 (ARVALID && RREADY) ##3
( ARVALID && RREADY && $stable(RDATA) ##1 ( ARVALID
&& RREADY && $stable(RDATA) ( ARVALID && RREADY &&
RLAST && $stable(RDATA) )
29
Out of transaction
Sequence s;
(ARVALID ##1 ARREADY)[*2] ;
End sequence
Property out_tr( @(posedge ACLK)
ARVALID|->s; Endproperty
30
Property xxx
@(posedge ACLK) ( RLAST && RVALID && RREADY ) |
=>##[1:4](RVALID && RREADY)
endproperty
31
WRITE BURST
Property xyz
@(posedge ACLK)
(AWVALID && AWREADY)|=>[*1:$] ($stable(WDATA))[->1:4];
endproperty
32
WRITE BURST
Sequence s;
(AWVALID && AWREADY);
Endsequence
Propert wr_burst(
@(posedgeACLK) AWVALID|=>[*1:$] (WVALID ==1 &&
WREADY==1 &&$stable(WDATA))[->1:4]
endproperty
33
WRITE BURST
Sequence s;
(AWVALID && AWREADY)
Endsequence
Propert wr_burst(
@(posedgeACLK) AWVALID=>[*1:$] (WVALID ==1 &&
WREADY==1 &&$stable(WDATA))[->1:$]##1 (BRESP==OKAY)
endproperty
34
WRITE BURST
Sequence s;
(AWVALID && AWREADY)
Endsequence
Propert wr_burst(
@(posedgeACLK) AWVALID->|=>[*1:$] (BRESP==OKAY &&
BVALID && BREADY);
endproperty
35
BURST TYPE checking
BURST_TYPE_CHECK:assert ( AWBURST<3 ||
ARBURST<3 ) else $warning ( This is reserved
burst type)
36
BURST TYPE checking
BURST_TYPE_CHECK:assert ( AWBURST<3 ||
ARBURST<3 ) else $error ( This burst type is not
implemented)
37
Cover property and cover group
assert: if you want scenario to be hold true then you write
an assertion.
cover : Whether scenario ever happened in your simulation
or not.
The difference is that covering a property ignores the
failures, and asserting a property ignores the passes.
Actually, you have a choice with an assert, You may want to
know that it passed at least once, and never fails.
An assertion that fails usually invalidates the entire test and
all associated coverage you have collected for that test.
38
Sequence s
@(posedge clk) a ##1 b;
Endsequence
Propert p;
a->s;
Endproperty
Assert property(p);
Cover property(p)
39
SLAVE RESPONSE
Property Rsp
( @(posedge ACLK) (RSESP==OAKY ||
BRESP==OKAY )
Endproperty
Assert_Rsp: assert property ( Rsp) $display( Normal
operation Completed) else $display ( Normal
operation is not completed)
40
Property Rsp1( @(posedge ACLK) ( RRESP==1 ||
BRESP==1 )
Endproperty
Assert_Rsp: assert property ( Rsp)
$display( EXOKAY feature is completed
successfully ) else $display ( EXOKAY feature is
not completed successfully)
41
Property Rsp1( @(posedge ACLK) ( RRESP==2 ||
BRESP==3)
Endproperty
Assert_Rsp: assert property ( Rsp) $display( Given
test is passed ) else $display ( Given test case
is failed due to slave error or decoder error )
42
