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A CMOS PWM Transceiver Using Self-Referenced Edge Detection

This document describes a CMOS PWM transceiver that uses self-referenced edge detection to reduce the power requirements of conventional PWM transceivers. It proposes a system where the receiver uses a self-referenced edge detector instead of an Rx-PLL in the PWM transmitter-receiver architecture. The transceiver compares the timing between a rising edge delayed by 0.5T and the data-modulated carrier edge within one carrier clock cycle to decode the signal, reducing the need for power-hungry PLLs. CMOS technology is suitable for this application as it requires a lower power supply voltage.

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48 views

A CMOS PWM Transceiver Using Self-Referenced Edge Detection

This document describes a CMOS PWM transceiver that uses self-referenced edge detection to reduce the power requirements of conventional PWM transceivers. It proposes a system where the receiver uses a self-referenced edge detector instead of an Rx-PLL in the PWM transmitter-receiver architecture. The transceiver compares the timing between a rising edge delayed by 0.5T and the data-modulated carrier edge within one carrier clock cycle to decode the signal, reducing the need for power-hungry PLLs. CMOS technology is suitable for this application as it requires a lower power supply voltage.

Uploaded by

unnidigi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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A CMOS PWM Transceiver Using

Self-Referenced Edge Detection

By
ANISHA SURENDRAN
Mtech 1st Year
VLSI &EMBEDDED SYSTEMS

Conventional PWM Transceiver have a lot of requirements


(large-area,power-hungry PLL).
The TRANSMITTER:-parallelizer,divide by-two-circuit,PWM
modulator,interface circuit,TxPLL.
The RECEIVER:-serializer,PWM demodulator,interface
circuit,Rx-PLL.
Proposed system:- Rx-PLLSelf-Referenced Edge detector in
PWM Tx-Rx architecture to reduse power hungry.
In proposed PWM transceiver:-timing comparison between
rising edge(self delayed about 0.5T) and the data modulated
carrier edge in one carrier clock cycle.
Why CMOS?
requires less power supply voltage.

REFERENCE
[1] W.-H. Chen, G.-K. Dehang, J.-W. Chen, and S.-I. Liu, A CMOS
400-Mb/s serial link for AS-memory systems using a PWMscheme,
IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 14981505,Oct. 2001
[2] C.-Y. Yang and Y. Lee, A PWM and PAM signaling hybrid
technology for serial-link transceivers, IEEE Trans. Instrum. Meas.,
vol.57, no. 5,pp. 10581070, May 2008.
[3] M.-T. Chung and C.-C. Hsieh, A 0.5 V 4.95 W 11.8 fps PWM
CMOS imager with 82 dB dynamic range and 0.055 % fixed-pattern
noise, in Proc. IEEE ISSCC, Feb. 2012, pp. 114116.
[4] K. Niitsu, M. Sakurai, N. Harigai, T. J.Yamaguchi, and H.
Kobayashi,CMOS circuits to measure timing jitter using a selfreferenced clock and a cascaded time difference amplifier with dutycycle compensation,IEEE J. Solid-State Circuits, vol. 47, no. 11, pp.
27012710, Nov. 2012

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