Input/Output Organization

Overview
Peripheral Devices
Input-Output Interface
Asynchronous Data Transfer
Modes of Transfer
Priority Interrupt
Direct Memory Access
Input-Output Processor
Serial Communication

Input/Output Organization

Input Output Organization

I/O Subsystem
Provides an efficient mode of communication between the
central system and the outside environment
Programs and data must be entered into computer memory for
processing and results obtained from computer must be
recorded and displayed to user.
When input transferred via slow keyboard processor will be idle
most of the time waiting for information to arrive
Magnetic tapes, disks

Input/Output Organization

Peripheral Devices

Devices that are under direct control of computer are said to be

connected on-line.

Input or output devices attached to the computer are also called

peripherals.

There are three types of peripherals :

Input peripherals
Output peripherals
Input-output peripherals
Peripheral (or I/O Device)
Monitor (Visual Output Device) : CRT, LCD
KeyBoard (Input Device) : light pen, mouse, touch screen, joy stick, digitizer
Printer (Hard Copy Device) : Daisy wheel, dot matrix and laser printer
Storage Device : Magnetic tape, magnetic disk, optical disk

Input/Output Organization

Peripheral Devices
Input Devices
Keyboard
Optical input devices
- Card Reader
- Paper Tape Reader
- Bar code reader
- Optical Mark Reader
Magnetic Input Devices
- Magnetic Stripe Reader
Screen Input Devices
- Touch Screen
- Light Pen
- Mouse

Output Devices
Card Puncher, Paper Tape Puncher
CRT
Printer (Daisy Wheel, Dot Matrix, Laser)
Plotter

Input/Output Organization

Input Output Organization

ASCII (American Standard Code for Information Interchange)
I/O communications usually involves transfer of alphanumeric
information from the device and the computer.
Standard binary code for alphanumeric character is ASCII
ASCII Code :
It uses 7 bits to code 128 characters (94 printable and 34 non printing)
7 bit 00 - 7F ( 0 - 127 )
ASCII is 7 bits but most computers manipulate 8 bit quantity as a
single unit called byte.
80 - FF ( 128 - 255 ) : Greek, Italic type font
Three types of control characters: Format effectors, Information
separators and communication control

 Format Effectors: control the layout of

printing. They include familiar typewriter
controls, such as backspace (BS), horizontal
tabulation(HT), carriage return(CR).
Information separators: used to separate
data into divisions like paragraphs and
pages. They include characters such as
record separator (RS) and file separator(FS).
Communication Control characters: these
are useful during the transmission of text
between remote terminals. These include
STX(Start of text) and ETX(end of text)

Input/Output Organization

I/O Interface

Provides a method for transferring information between internal

storage (such as memory and CPU registers) and external I/O
devices
Resolves the differences between the computer and peripheral
devices
(1). Peripherals Electromechanical or Electromagnetic Devices
CPU or Memory - Electronic Device

Conversion of signal values required

(2). Data Transfer Rate

Peripherals - Usually slower
CPU or Memory - Usually faster than peripherals

Some kinds of Synchronization mechanism may be needed

(3). Data formats or Unit of Information

Peripherals Byte, Block,
CPU or Memory Word
(4). Operating modes of peripherals may differ
must be controlled so that not to disturbed other peripherals connected to CPU

Input/Output Organization

10

I/O Bus and Interface

I/O bus

Data
Address
Control

Processor

Interface

Interface

Interface

Interface

Keyboard
and
display
terminal

Printer

Magnetic
disk

Magnetic
tape

Interface :
- Decodes the device address (device code)
- Decodes the commands (operation)
- Provides signals for the peripheral controller
- Synchronizes the data flow and supervises
the transfer rate between peripheral and CPU or Memory

4 types of command interface can receive : control, status, data o/p and data i/p

Input/Output Organization

11

I/O Bus and Interface

Control command : is issued to activate peripheral and to inform what to do
Status command : used to test various status condition in the interface and
the peripherals
data o/p command : causes the interface to respond by transferring data from
the bus into one of its registers
data i/p command : interface receives an item of data from the peripheral and
places it in its buffer register.

Input/Output Organization

12

I/O Bus and Memory Bus

Functions of Buses
MEMORY BUS is for information transfers between CPU and the MM
I/O BUS is for information transfers between CPUand I/O devices through
their I/O interface
3 ways to bus can communicate with memory and I/O :
(1). use two separate buses, one to communicate with memory and the
other with I/O interfaces
- Computer has independent set of data, address and control bus one for
accessing memory and another I/O.
- done in computers that have separate IOP other than CPU.

(2). Use one common bus for memory and I/O but separate control lines
for each
(3). Use one common bus for memory and I/O with common control
lines for both

Input/Output Organization

13

Isolated vs. Memory Mapped I/O

Isolated I/O
- Many computers use common bus to transfer information between
memory or I/O.
- The distinction between memory transfer and I/O transfer is made
through separate read and write line.
-In the isolated I/O configuration , the CPU has distinct input and output
instructions and each of these instruction is associated with the
address of an interface register.
- Distinct input and output instructions - each associated with address of interface
register

Memory-mapped I/O
- A single set of read/write control lines
(no distinction between memory and I/O transfer)
- Memory and I/O addresses share the common address space
-> reduces memory address range available
- No specific input or output instruction
-> The same memory reference instructions can
be used for I/O transfers
- Considerable flexibility in handling I/O operations

Input/Output Organization

14

I/O Interface
Bidirectional

Register select
Register select
I/O read
I/O write

Programmable Interface

CS
RS1
RS0
RD

Timing
and
Control

Internal bus

Chip select

I/O data

Port B
register

I/O data

Bus
buffers

data bus

CPU

Port A
register

Control
register
Status
register

WR
CS RS1 RS0
0
x
x
1
0
0
1
0
1
1
1
0
1
1
1

Control

I/O
Device

Status

Register selected
None - data bus in high-impedence
Port A register
Port B register
Control register
Status register

- Information in each port can be assigned a meaning depending on the mode of operation of the
I/O device Port A = Data; Port B = Command;
- CPU initializes(loads) each port by transferring a byte to the Control Register
Allows CPU can define the mode of operation of each port
Programmable Port: By changing the bits in the control register, it is possible to change the
interface characteristics

Input/Output Organization
Lecture 36

15

Peripheral Devices
Input-Output Interface
Asynchronous Data Transfer
Modes of Transfer
Priority Interrupt
Direct Memory Access
Input-Output Processor

11-3. Asynchronous Data Transfer

Synchronous Data Transfer: Clock pulses are applied to all
registers within a unit and all data transfer among internal
registers occur simultaneously during the occurrence of a clock
pulse. Two units such as CPU and I/O Interface are designed
independently of each other. If the registers in the interface
share a common clock with CPU registers, the transfer
between the two is said to be synchronous.
Asynchronous Data Transfer: Internal timing in each unit
(CPU and Interface) is independent. Each unit uses its own
private clock for internal registers. Asynchronous data transfer
between two independent units requires that control signals be
transmitted between the communicating units to indicate the
time at which data is being transmitted. One way of achieving
this is by means of STROBE(Control signal to indicate the time
at which data is being transmitted) pulse and other method is
HANDSHAKING(Agreement between two independent units).

Timeout : If the return handshake signal does not respond within a given time period,
the unit assumes that an error has occurred.

 Asynchronous Serial Transfer

Synchronous transmission :
The two unit share a common clock frequency
Bits are transmitted continuously at the rate dictated
by the clock pulses

Asynchronous transmission :
Binary information sent only when it is available and
line remain idle otherwise
Special bits are inserted at both ends of the character
code
Each character consists of three parts :
1) start bit : always 0, indicate the beginning of
a character
2) character bits : data
3) stop bit : always 1
1

S ta rt
b it

C h a r a c te r b its

S to p
b it

 Asynchronous transmission rules :

When

a character is not being sent, the line is kept

in the 1-state
The initiation of a character transmission is
detected from the start bit, which is always 0
The character bits always follow the start bit
After the last bit of the character is transmitted, a
stop bit is detected when the line returns to the 1state for at least one bit time

Baud Rate : Data transfer rate in bits per

second
10 character per second with 11 bit format = 110 bit
per second

Input/Output Organization

24

Universal Asynchronous Receiver

Transmitter
A typical asynchronous communication interface available as an IC
Bidirectional
data bus

Bus
buffers

CS
RS

I/O read
I/O write

RD
WR

Timing
and
Control

Internal Bus

Chip select

Transmitter
register

Control
register

Shift
register

Transmit
data

Transmitter Transmitter
clock
control
and clock

Status
register

Receiver
control
and clock

Receiver
register

Shift
register

Receiver
clock
Receive
data

CS
0
1
1
1
1

RS
x
0
1
0
1

Oper.
x
WR
WR
RD
RD

Register selected
None
Transmitter registe
Control register
Receiver register
Status register

Transmitter Register
- Accepts a data byte(from CPU) through the data bus
- Transferred to a shift register for serial transmission
Receiver Register
- Receives serial information into another shift register
- Complete data byte is sent to the receiver register
Status Register Bits
- Used for I/O flags and for recording errors
Control Register Bits
- Define baud rate, no. of bits in each character, whether to generate and
check parity, and no. of stop bits

Overview
Peripheral Devices
Input-Output Interface
Asynchronous Data Transfer
Modes of Transfer
Priority Interrupt
Direct Memory Access
Input-Output Processor

Modes of Transfer
Binary information received from external device is usually
stored in memory.
Information transferred from central computer into an external
device originates in the memory unit.
The CPU merely execute I/O instructions and may accept data
temporarily but ultimate source or destination is the Memory Unit.
Data transfer between central computer and I/O devices may be
handled in a variety of modes. Some modes use CPU as
intermediate path and others transfer data directly to and from
memory unit.
Data Transfer to or from peripheral can be handled in one of
three possible modes :
Programmed I/O
Interrupt-Initiated I/O
Direct Memory Access (DMA)

Input/output Organization

27

Modes of Transfer Programmed I/O

- Programmed I/O operations are the result of I/O Instructions written in computer program. Each
data item transfer is initiated by an instruction in the program.
- Usually, transfer is to and from a CPU register to peripheral
Other instructions are needed
to transfer
data
to and from CPU and Memory
Program-Controlled
I/O(Input
Dev to
CPU)
Interface

Data bus
Address bus
CPU

Data register

I/O read
I/O write

Status
register F

I/O bus
Data valid

I/O
device

Data accepted

Read status register

Check flag bit

flag

=0

=1
Read data register
Transfer data to memory

no

Operation
complete?
yes
Continue with
program

Polling or Status Checking

Continuous CPU involvement

CPU slowed down to I/O speed
Simple
Least hardware
useful in small low-speed comput

Programmed I/O
- Programmed I/O operations are the result of I/O
Instructions written in computer program. Each data item
transfer is initiated by an instruction in the program.
- Usually, transfer is to and from a CPU register to
peripheral. Other instructions are needed to transfer data
to and from CPU and Memory
- Transferring data under program control requires
constant monitoring of the peripheral by CPU.

 In programmed I/O method, CPU stays

in a program loop until the I/O unit
indicated that it is ready for data
transfer. This is a time consuming
process since it keeps the processor
busy needlessly. It can be avoided by
using Interrupt facility and special
commands to inform the interface to
issue an interrupt request signal when
data are available for the device.

Interrupted I/O

DMA

Priority Interrupts
Priority
- Determines which interrupt is to be served first when two or more requests
are made simultaneously
- Also determines which interrupts are permitted to interrupt the computer while
another is being serviced
- Higher priority interrupts can make requests while servicing a lower priority
interrupt

A priority interrupt is a system that establishes priority over the

various sources to determine
- which condition is to serviced first when two or more requests
arrive simultaneously
-which conditions are permitted to interrupt the computer while
another request is being serviced

Priority Interrupts
Priority Interrupt by Software (Polling)
Polling procedure is used to identify highest priority source by software
means
- common branch address for all the interrupts
- Priority is established by the order of polling the devices(interrupt sources)
- highest priority device is tested first and if interrupt is on , control
branches to service routine for this source otherwise next lower priority
source is tested
- Flexible since it is established by software
- Low cost since it needs a very little hardware
- Very slow
- if there are many interrupt time required to poll may exceed time available to
service IO device

Priority Interrupts

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts all the interrupt requests
to determine the highest priority request
- Fast since identification of the highest priority interrupt request is identified by
the hardware
- Fast since each interrupt source has its own interrupt vector to access
directly to its own service routine
- Can be addressed using serial or parallel connection of interrupt lines.
Example of serial is Daisy chaining Priority

Hardware Priority Interrupts Daisy

Chain
VAD 2

VAD 1
Device 1
PI

PO

Device 2
PI

PO

VAD 3
Device 3
PI

PO

Interrupt request

To next
device

* Serial hardware priority functi

* Interrupt Request Line
- Single common line
* Interrupt Acknowledge Line
- Daisy-Chain

INT

CPU
Interrupt acknowledge

INTACK

-Serial connection of all device that request an interrupt

-Device with highest priority placed in first position followed by devices with lower
priority and so on.
-Interrupt generated by any device signals low state interrupt line
-CPU responds by enabling interrupt acknowledgement (INTACK) line.
- device receives PI=1 and passes to next only when not requesting else PI=0
-Thus device with PI=1 and PO=0 is one with highest priority requesting interrupt

Hardware Priority Interrupts Daisy

Chain
Example: Daisy chain working

Hardware Priority Interrupts Daisy

Chain

Parallel Priority Interrupts

Bus
Buffer

Interrupt register
Disk

I0

Printer

I1

Reader

Keyboard

0
Mask
register

1
2
3

Priority
I 2 encoder

I3

IEN

VAD
to CPU

0
IST

0
0
Enable
Interrupt
to CPU
INTACK
from CPU

IEN:
Set or Clear by instructions ION or IOF
IST:
Represents an unmasked interrupt has occurred. INTACK enables tristate
Bus Buffer to load VAD generated by the Priority Logic
Interrupt Register:
- Each bit is associated with an Interrupt Request from different Interrupt
Source - different priority level
- Each bit can be cleared by a program instruction
Mask Register:
- Mask Register is associated with Interrupt Register
- Each bit can be set or cleared by an Instruction

Priority Encoder
Determines the highest priority interrupt when
more than one interrupts take place
Priority Encoder Truth table
Inputs
I0 I1 I2
1 d
0 1
0 0
0 0
0 0

I3
d
d
1
0
0

Outputs
d
d
d
1
0

IST

Boolean functions

0
0
1
1
d

0
1
0
1
d

1
1
1
1
0

x = I0' I1'
y = I0' I1 + I0 I2
(IST) = I0 + I1 + I2 + I3

Interrupt Cycle
At the end of each Instruction cycle
- CPU checks IEN and IST
- If IEN IST = 1, CPU -> Interrupt Cycle
SP SP - 1
M[SP] PC
INTACK 1
PC VAD
IEN 0
Go To Fetch

Decrement stack pointer

Push PC into stack
Enable interrupt acknowledge
Transfer vector address to PC
Disable further interrupts
to execute the first instruction
in the interrupt service routine

Initial and Final Operations

3

VAD=00000011

KBD
interrupt

JMP DISK

JMP PTR

JMP RDR

JMP KBD
Main program

1
749
750
11
2

DISK
PTR

Program to service
line printer

RDR

Program to service
character reader

current instr.
Stack

KBD
5

256
750

Program to service
magnetic disk

Disk
interrupt

Program to service
keyboard
255
256
6

10

9
Initial and Final Operations
Each interrupt service routine must have an initial and final set of
operations for controlling the registers in the hardware interrupt system

Initial Sequence
Final Sequence
[1] Clear lower level Mask reg. bits [1] IEN <- 0
[2] IST <- 0
[2] Restore CPU registers
[3] Save contents of CPU registers
[3] Clear the bit in the Interrupt Reg
[4] IEN <- 1
[4] Set lower level Mask reg. bits
[5] Go to Interrupt Service Routine [5] Restore return address, IEN <- 1

Input/Output Organization

42

Overview
Peripheral Devices
Input-Output Interface
Asynchronous Data Transfer
Modes of Transfer
Priority Interrupt
Direct Memory Access
Input-Output Processor

Input/Output Organization

44

Direct Memory Access

* Block of data transfer between high speed devices like Disk and Memory
* DMA controller - Interface which takes over the buses to manage the transfer directly between
Memory and I/O Device, freeing CPU for other tasks
* CPU initializes DMA Controller by sending memory address and the block size (number of
words)

Fig 1: CPU bus signals for DMA transfer

BR

Bus granted

BG

CPU

Address bus
Data bus
Read
Write

Data bus

Address register:
Contains an address to specify
Desired location in memory DMA select
Word count register
Read
Holds no. of words to be transferred
Write
Control register
Bus request
Specifies the mode of transfer
Bus grant

Interrupt

Fig 2: Block diagram of DMA controll

Data bus
buffers

DS
RS
RD

WR Control
logic
BR

Address bus
buffers
Internal Bus

Bus request

ABUS
DBUS
RD
WR

Address register
Word count register
Control register

BG
Interrupt

DMA request
DMA acknowledge

to I/O device

Input/Output Organization

45

Direct Memory Access

RD and WR is bidirectional
When BG=0 CPU can communicate with DMA Register
When BG=1 CPU left the buses and DMA can communicate directly with memory
DMA Transfer can be made in several ways
(1)Burst Transfer : a block sequence consisting of memory words is transferred
in continuous burst while the DMA controller is master of memory
bus
- This mode of transfer is needed for fast devices such as magnetic
disk where data transmission cannot be stopped or slowed down
until an entire block is transferred
(2) Cycle stealing : Alternative technique called cycle stealing allows DMA controller to
transfer one data word at time after which it must return control of
the buses to the CPU.
- CPU merely delays its operation for one memory cycle to allow the
direct memory I/O transfer to steal one memory cycle

Input/Output Organization

46

DMA I/O Operation

DMA is first initialized by CPU. After that DMA starts and continues to transfer data
between memory and peripheral unit until an entire block is transferred.

CPU initializes the DMA by sending following information through data bus:
(1) Starting address of the memory block (for read/write)
(2) Word Count (no. of words in memory block)
(3) Control to specify mode of transfer (E.g. read/write)
(4) A control to start DMA Transfer

Input/Output Organization

48

DMA Transfer
Interrupt
BG

Random-access
memory unit (RAM)

CPU

BR
RD

WR

Addr

Data

RD

WR

Addr

Data

Read control
Write control
Data bus
Address bus
Address
select
RD

WR

Addr

DMA ack.

DS
RS
BR
BG
Interrupt

Data

I/O
Peripheral
device

DMA
Controller
DMA request

Input/Output Organization

49

I/O Processor - Channel

Channel
- Processor with direct memory access capability that
communicates with I/O devices
- Channel accesses memory by cycle stealing
- Unlike DMA Controller, IOP can fetch and execute its own
instruction
- IOP Instructions (Commands) specially designed to facilitate
I/O transfer.

Memory Bus

- Data gathered in IOP at device rate and bit capacity while

CPU executing own program
- Transfer between IOP and Device similar to Programmed I/O
and
Central
transfer between IOPprocessing
and Memory similar to DMA
- CPU is master while IOP
slave processor
unitis
(CPU)
- CPU initiates the channel by executing aPeripheral
channeldevices
I/O class
Memory
instruction unit
and once initiated, channel PD
operates
independent
of
PD
PD
PD
the CPU
Input-output
processor
(IOP)

I/O bus

Input/Output Organization

50

Channel CPU Communication

CPU operations
Send instruction
to test IOP.path
If status OK, then send
start I/O instruction
to IOP.
CPU continues with
another program

Request IOP status

Check status word

for correct transfer.
Continue

IOP operations

Transfer status word

to memory

Access memory
for IOP program
Conduct I/O transfers
using DMA;
Prepare status report.
I/O transfer completed;
Interrupt CPU

Transfer status word

to memory location