VLSI Design

Introduction to VLSI Design Lec01. 1

 References

Texts
- Rabaey. J. Digital Integrated Circuits, 2002
- Uyemura J. P. Physical Design of CMOS Integrated
Circuits Using L-Edit (optional reference)

Course Expectations - Thorough Understanding of IC Design phases

Introduction to VLSI Design Lec01. 2

 COURSE OBJECTIVES

1. This presentation provides an introduction to the fundamental

principles of VLSI circuit design.

2. Design Styles/Methodologies of Design

Introduction to VLSI Design Lec01. 3

 TOPICS TO BE COVERED

Overview of VLSI, MOS Transistor

Design Styles and Methodologies

Introduction to VLSI Design Lec01. 4

 VLSI:Very Large Scale Integration

Integration: Integrated Circuits

multiple devices on one substrate
How large is Very Large?
SSI (small scale integration)
7400 series, 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1,000-10,000 transistors
VLSI > 10,000 transistors
ULSI/SLSI (some disagreement)

Introduction to VLSI Design Lec01. 5

 WHY VLSI?
Integration Improves the Design
Lower parasitics, higher clocking speed
Lower power
Physically small

Integration Reduces Manufacturing Costs

(almost) no manual assembly
About $1-5billion/fab
Typical Fab 1 city block, a few hundred
people
Packaging is largest cost
Testing is second largest cost
For low volume ICs, Design Cost may swamp
all manufacturing cost
Introduction to VLSI Design Lec01. 6
 Levels of Design
Specifications
IO, Goals and Objectives, Function, Costs

Architectural Description
VHDL, Verilog, Behavioral, Large Blocks

Logic Design
Gates plus Registers

Circuit Design
Transistors sized for power and speed
Discrete Logic, Technology Mapping

Layout
Size, Interconnect, Parasitics
Introduction to VLSI Design Lec01. 7
 SYSTEM

+ MODULE

GATE

CIRCUIT

G
S D DEVICE
n+ n+

Introduction to VLSI Design Lec01. 8

 What is CMOS VLSI?

MOS = Metal Oxide Semiconductor (This used to

mean a Metal gate over Oxide insulation)

Now we use polycrystalline silicon which is

deposited on the surface of the chip as a gate. We
call this poly or just red stuff to distinguish it
from the body of the chip, the substrate, which is a
single crystal of silicon.

We do use metal (aluminum) for interconnection

wires on the surface of the chip.
Introduction to VLSI Design Lec01. 9
 D

S G D G

Poly crossed over Diffusion Field effect transistor (FET)

Insulated Gate Metal Oxide Semiconductor FET

Source and Drain are Interchangeable

Introduction to VLSI Design Lec01. 10

 N-Channel Enhancement mode MOS FET

FourTerminalDevicesubstratebias

TheselfalignedgatekeytoCMOS

Introduction to VLSI Design Lec01. 11

 CMOS:Complementary MOS

Means we are using both N-channel and P-channel

type enhancement mode Field Effect Transistors
(FETs).
Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
N/P Channel - doping of the substrate for increased
carriers (electrons or holes)

Introduction to VLSI Design Lec01. 12

 Complementary Metal Oxide
Semiconductor
VDD

PMOS

X X
NMOS

VSS

Introduction to VLSI Design Lec01. 13

 Four Views

Logic Transistor Layout

Physical

Introduction to VLSI Design Lec01. 14

 VLSI Design
The real issue inVLSI is about designing systems on
chips.
The designs are complex, and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the design.
We also accept the fact that any technology we learn
the details of will be out of date soon.
We are trying to develop and use techniques that
will transcend the technology, but still respect it.

Introduction to VLSI Design Lec01. 15

 Help from Computer Aided Design tools

Tools Experts
Editors Logic design
Simulators Electronic/circuit
Libraries design
Module Synthesis Device physics
Place/Route Artwork
Chip Assemblers Applications - system
Silicon Compilers design
Architectures

Introduction to VLSI Design Lec01. 16

 Design Styles

Full custom
Standard cell
Gate-array
Macro-cell
FPGA
Combinations

Introduction to VLSI Design Lec01. 17

 Full Custom

Hand drawn geometry

All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
Introduction to VLSI Design Lec01. 18
 Full Custom

Vdd

IN Out

Gnd

Introduction to VLSI Design Lec01. 19

 Standard cells

Standard cells organized in rows (and, or, flip-

flops,etc.)
Cells made as full custom by vendor (not user).
All layers customized
Digital with possibility of special analog cells.
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
Introduction to VLSI Design Lec01. 20
 Standard cells

Routing

Cell

IO cell

Introduction to VLSI Design Lec01. 21

 Gate-array

Predefined transistors connected via metal

Two types: Channel based
Channel less (sea of gates)
Only metallization layers customized
Fixed array sizes (normally 5-10 different)
Digital cells in library (and, or, flip-flops,etc.)
Simulation at gate level (digital)
Medium density
Medium performance
Reasonable design time
Introduction to VLSI Design Lec01. 22
 Gate-array
Sea of gates Channel based
Vdd
NAND gate using gate isolation

Vdd
A

B
PMOS

Oxide isolation B
Out A
Out

NMOS

Gate isolation
Gnd

Can in principle be used by adjacent cell

Gnd

Introduction to VLSI Design Lec01. 23

 Gate-array

Sea of gates
RAM

Introduction to VLSI Design Lec01. 24

 Macro cell
Predefined macro blocks (Processors, RAM,etc)
Macro blocks made as full custom by vendor
All layers customized
Digital and some analog (ADC)
Simulation at behavioral or gate level (digital)
High density DSP processor

High performance
Short design time
LCD
cont.
RAM

Use standard on-chip busses ADC ROM

System on a chip
Introduction to VLSI Design Lec01. 25
 FPGA = Field Programmable Gate Array

Programmable logic blocks

Programmable connections between logic blocks
No layers customized (standard devices)
Digital only
Low - medium performance (<50 - 100MHz)
Low - medium density (up to ~100k gates)
Programmable by: SRAM, EEROM, Anti_fuse, etc
Cheap design tools on PCs
Low development cost
High device cost
Introduction to VLSI Design Lec01. 26
 FPGA

Introduction to VLSI Design Lec01. 27

 Comparison

FPGA Gate array Standard cell Full custom Macro cell

Density Low Medium Medium High High
Flexibility Low (high) Low Medium High Medium
Analog No No No Yes Yes
Performance Low Medium High Very high Very high
Design time Low Medium Medium High Medium
Design costs Low Medium Medium High High
Tools Simple Complex Complex Very complex Complex
Volume Low Medium High High High

Introduction to VLSI Design Lec01. 28

 High performance devices

Mixture of full custom, standard cells and macros

Full custom for special blocks: Adder (data path),
etc.
Macros for standard blocks: RAM, ROM, etc.
Standard cells for non critical digital blocks

Introduction to VLSI Design Lec01. 29

 ASIC with mixture of full custom,RAM and standard cells

Single port RAM

Dual port RAM

Full custom

Standard cell

FIFO

Introduction to VLSI Design Lec01. 30

 Pentium

Introduction to VLSI Design Lec01. 31

 ALPHA & MOTOROLA POWER PC
Alpha

Introduction to VLSI Design Lec01. 32

 New combinations
FPGAs with RAM, PCI interface, Processor, ADC, etc.
Gate arrays with RAM, Processor, ADC, etc

Processor

FPGA or Gate-array logic

RAM

Introduction to VLSI Design Lec01. 33