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Outline
Verilog Expressions
Primitives Gates

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Continuous Assignments

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What is Verilog?
Verilog is a HDL (Hardware Description Language) use to design a digital
system.
VHDL is another hardware description language used.

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Virtually every chip (FPGA, ASIC, etc.) is designed in part using one of these
two languages.
Verilog was introduced in 1985 by Gateway Design System Corporation.

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What is Verilog?
IEEE 1364-2001 is the latest Verilog HDL standard.
Verilog is case sensitive (Keywords are in lowercase).

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The Verilog is both a behavioral and a structure language.

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Differences between Verilog and VHDL
Verilog is similar to C- language.
VHDL is similar to ADA (a structured, statically typed, imperative, wide-
spectrum, and object-oriented high-level computer programming language,

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extended from Pascal )
Many feel that Verilog is easier to learn and use than VHDL.

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Verilog-logic Values
0 zero, logic low, false, ground

1 one, logic high, power

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X unknown, dont care

Z high impedance, unconnected, tri-state

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Types Verilog Coding
Behavioral
Procedural code, similar to C programming
Little structural detail (except module interconnect)

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Dataflow
Specifies transfer of data between registers
Some structural information is available (RTL)
Sometimes similar to behavior
Structural (gate, switch)
Interconnection of simple components
Purely structural

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Verilog Keywords
Note : All keywords are defined in lower case
Examples :
module, endmodule

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input, output, inout
reg, integer, real, time
not, and, nand, or, nor, xor
parameter
begin, end
fork, join
specify, endspecify
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Starting Verilog
To start a verilog coding:

module fundamental building block for Verilog designs

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Used to construct design hierarchy
Cannot be nested

endmodule ends a module, not a statement

No semicolon ;

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Module Declaration
Module Declaration:

module <module_name> (module_port,module_port,);

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[content]

endmodule

test
in1 out1
out2 module test(out1, .., inN);
in2
.. // declarations
f
endmodule
inN outM

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Exercise #1
Consider a full adder block below:
A B

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Full Adder
Circuit Cin

CO S
module full_adder(A,B,Cin,Co,S);
[content]
endmodule
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Input Declaration
Two types of representation:
A B

Scalar
Full Adder
input list of input identifiers;

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Circuit Cin

Example: input A,B,Cin;

CO S
EN
S2
S1
S0
D7
Vector D6 8-to-1
Y
input[MSB:LSB] list of input identifiers; D5
D4
MUX

Example: input[7:0]D,[3:0]S,EN; D3
D2
D1
D0
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Exercise #2
Include the inputs for the full adder:
A B

Full Adder

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Circuit Cin

CO S

module full_adder(A,B,Cin,Co,S);
input A,B,Cin;

[content] Do not forget the

semicolon!
endmodule
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Output Declaration
Two types of representation: A B
Scalar Example: output S,Co;
Full Adder

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Circuit Cin

CO S

Vector Example: output[7:0]REG_IN;

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Exercise #3
Now, include the output declaration for the full adder:
A B

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Full Adder
Circuit Cin

CO S

module full_adder(A,B,Cin,Co,S);
input A,B,Cin;
output Co,S;
Do not forget the
[content] semicolon!
endmodule
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Elements in Verilog
Nets
Nets are physical connections between devices
Many types of nets, but all we care about is wire.

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Declaring a net
wire [range]<net_name>;

Example

wire [2:1]w;
or
wire w1,w2;
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Elements in Verilog
Registers
Implicit storage-holds its value until a new value available.
Usually registers are also the circuits output.
Register type is denoted by reg.

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Declaring a register
reg [range]<reg_name>;
sel[1:0]
Example:
input [3:0]a,b,c,d; a[3:0]
output [3:0]y; b[3:0]
y[3:0]
c[3:0]
reg [3:0]y; d[3:0]
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Comment Lines in Verilog
There are two kinds of comments:
Single line
Multiple line.

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A single line:
// This is a single line

Multiple line:
/* This is a multiple line
Nest multi-line
*/
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Numbers Declaration in Verilog
Numbers (all number systems) can be declared by using the following
command:
<size><radix><value>

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No of bits Binary b or B Consecutive chars
Octal o or O 0-f, x, z
Decimal d or D
Example: Hexadecimal h or H
8hax = 1010xxxx
4b0110 = 0110

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Verilog Primitives
Basic logic gates only:
and
or

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not
buf
xor
nand
nor
xnor
bufif1, bufif0
notif1, notif0

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Primitive Gates
Let say we have an AND gate:

g1

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module and_gate(A,B,x);
input A,B;
output x; (outputs, inputs)

and g1(x,A,B);
endmodule
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Continuous Assignments
We still defining AND gate but with equation type of approach:

g1

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module and_gate(A,B,x);
input A,B;
Logical AND in
output x;
Verilog
assign x = A & B;
endmodule
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Continuous Assignments for all Gates
module gates(a, b, y1, y2, y3, y4, y5, y6, y7);
input a, b;
output y1, y2, y3, y4, y5, y6, y7;

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/* Seven different logic gates programmed together in one single file*/

assign y1= ~a; // NOT gate

assign y2= a & b; // AND gate
assign y3= a | b; // OR gate
assign y4= ~(a & b); // NAND gate
assign y5= ~(a | b); // NOR gate
assign y6= a ^ b; // XOR gate
assign y7= ~(a ^ b); // XNOR gate

endmodule

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 Verilog Operators

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 Verilog Operators

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Bitwise Operations
Given: c = ~a;

a = 4b1010;
b = 4b1100;

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c = a & b;

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 Given:

b = 2b11;
a = 4b1010;
Bitwise Operations

c = a ^ b;

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Exercise #4
Lets consider a half adder circuit:

A
S

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B

Co

Write a Verilog code for the circuit in primitives gate as well as in continuous
assignment.

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Exercise #4: Primitives Gate

module half_adder(A,B,S,Co);
A

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S input A,B;
B
output S,Co;

Co
xor g1(S,A,B);
and g2(Co,A,B);

endmodule

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Exercise #4: Continuous Assignment

module half_adder(A,B,S,Co);

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A
B S input A,B;
output S,Co;

Co
assign S = A ^ B;
assign Co = A & B;

endmodule

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Exercise #5
Lets consider the following circuit:

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Write a Verilog code for the circuit in primitives gate as well as in continuous
assignment.

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Exercise #5: Primitives Gate

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module circuit1(A,B,C,x,y);
input A,B,C;
output x,y;
wire e;

and g1(e,A,B);
not g2(y,C);
or g3(x,e,y);

endmodule
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Exercise #5: Continuous Assignment

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module circuit1(A,B,C,x,y);
input A,B,C;
output x,y;
wire e;

assign x = (A&B)|(~C);
assign y = ~C;

endmodule
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Exercise #6
Lets consider the full adder circuit below, which is made from 2 half adders.

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Write a Verilog code for the circuit in primitives gate as well as in continuous assignment.

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 g2
g1

w2
Exercise #6: Primitives Gate

w1

g4
g3
w3
g5

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Exercise #6: Primitives Gate

w1
module full-adder(A,B,Cin,Cout,Sum);
g1
g5 input A,B,Cin;
output Cout, Sum;

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g2 w3
g3
w2
wire w1,w2,w3;
g4

and g1(w1,A,B);
xor g2(w2,A,B);
and g3(w3,Cin,w2);
xor g4(Sum,w2,Cin);
or g5(Cout,w1,w3);

endmodule

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Exercise #6: Primitives Gate
But it is also made out of 2 half adder (we already have half-adder module
previously).

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w1

w3

HA1 w2

HA2

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Exercise #6: Primitives Gate

module full-
w1 adder(A,B,Cin,Cout,Sum);

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input A,B,Cin;
w3 output Cout, Sum;
HA1 w2 wire w1,w2,w3;

HA2 half_adder HA1(w2,w1,A,B);

half_adder HA2(Sum,w3,w2,Cin);
A S or or1(Cout,w1,w3);
B
Co endmodule

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Exercise #6: Continuous Assignment

module full-adder(A,B,Cin,Cout,Sum);
g1
w1
g5
input A,B,Cin;

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output Cout, Sum;
g2 w3
g3 wire w1,w2,w3;
w2
g4
assign Sum = A ^ B ^ Cin;
assign Cout = (A & B)|(Cin &(A^B))

endmodule

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Exercise #7
Now, lets try a little bit complicated circuit. 4-bit adders.

A3 B3 A2 B2 A1 B1 A0 B0

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C2 C1 C0
Cin
Cout

S3 S2 S1 S0

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Exercise #7: Solution (i)
module add4 (S,Cout,A,B,Cin);
input [3:0]A, B; A3 B3 A2 B2 A1 B1 A0 B0
input Cin ;
output [3:0] S : C2 C1 C0 Cin
output Cout ;

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wire C0,C1,C2; Cout

full-adder FA0 (C0, S[0], A[0], B[0], Cin) ; S3 S2 S1 S0

full-adder FA1 (C1, S[1], A[1], B[1], C0) ;

full-adder FA2 (C2, S[2], A[2], B[2], C1) ;
full-adder FA3 (Cout, S[3], A[3], B[3], C2) ;

endmodule

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Exercise #7: Solution (ii)
module add4 (S,Cout,A,B,Cin);
input [3:0]A,B; A3 B3 A2 B2 A1 B1 A0 B0
input Cin;
output [3:0]S; C2 C1 C0 Cin
output Cout;

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Cout

assign {Cout,S} = A + B + Cin;

S3 S2 S1 S0

endmodule

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Exercise #8
Simulate the add4 module according to the sequence of binary values
shown in the table below, and then stop simulation.

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time A[3:0] B[3:0] Cin
0 ns 1000 0111 1
10 ns 1111 0000 1
20 ns 1010 0101 0
30 ns 0011 0100 0
40 ns Stop simulation

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Exercise #8: solution
timescale 1ns/1ns
A = 4b1010;
module test_add4; B = 4b0101;
reg [3:0]A,B; Cin = 1b0;
reg Cin; #10;

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wire [3:0]S; A = 4b0011;
wire Cout; B = 4b0100;
Cin = 1b0;
initial begin #10;
A = 4b1000; $stop;
B = 4b0111; end
Cin = 1b1;
#10; add4 mut (.A(A), .B(B), .Cin(Cin), .S(S),
A = 4b1111; .Cout(Cout));
B = 4b0000;
Cin = 1b1; endmodule
#10;

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if-else Statement
Format
if (conditional_expression) statement;
else statement;

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Behavior
If the conditional_expression is true, then the first statement is executed;
Or else the second statement is executed.

Used inside an always block, the statements are procedural.

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Exercise #9: 2-to-1 Mux
The same 2-to-1 multiplexer:
s f
0 w0
w1

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1
module mux2to1 (w0, w1, s, f);
input w0, w1, s;
output f;
Include all input signals
always @(w0 or w1 or s)
if (s == 0)
f = w0;
else
f = w1;

endmodule

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Exercise #10: 4-to-1 Mux
module mux4to1 (w0, w1, w2, w3, S, f);
input w0, w1, w2, w3; s1 s0 f
input [1:0]S;
output f; 0 0 w0

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0 1 w1
always @(w0 or w1 or w2 or w3 or S) 1 0 w2
1 1 w3
if (S == 2'b00)
f = w0;
else if (S == 2'b01)
f = w1;
else if (S == 2'b10)
f = w2;
else if (S == 2'b11)
f = w3;

endmodule
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Case Statement
Format
case(expression)
1) Many possible alternatives
alternative1: statement;

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2) Expression and each alternative are compared
alternative2: statement;
bit by bit.

3) If there is a match, the statement is executed
alternativen: statement;
[default: statement;]
4) If the alternatives do not cover all possibilities,
default should be included. Otherwise, a
endcase
sequential circuit will be generated.

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Exercise #11: 4-to-1 Mux
module mux4to1 (W, S, f);
input [0:3] W; s1 s0 f
input [1:0] S;
output f; 0 0 w0

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0 1 w1
reg f; w2
1 0
1 1 w3
always @(W or S)
case (S)
0: f = W[0];
1: f = W[1];
2: f = W[2];
3: f = W[3];
endcase

endmodule

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Exercise #12: 2-to-4 Decoder
module dec2to4 (W, Y, En);
input [1:0]W;
input En; En w1 w0 y0 y1 y2 y3
output [0:3]Y;
1 0 0 1 0 0 0

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reg [0:3]Y;
1 0 1 0 1 0 0
1 1 0 0 0 1 0
always @(W or En)
1 1 1 0 0 0 1
case ({En, W})
0 x x 0 0 0 0
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000; Default for En=0
endcase

endmodule
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Exercise #13: 2-to-4 Decoder
module dec2to4 (W, Y, En);
input [1:0] W;
input En;
output [0:3] Y; En w1 w0 y0 y1 y2 y3
reg [0:3] Y;
1 0 0 1 0 0 0

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always @(W or En) 1 0 1 0 1 0 0
begin 1 1 0 0 0 1 0
if (En == 0) 1 1 1 0 0 0 1
Y = 4'b0000; 0 x x 0 0 0 0
else
case (W)
0: Y = 4'b1000;
1: Y = 4'b0100;
2: Y = 4'b0010;
3: Y = 4'b0001;
endcase
end

endmodule 51
Exercise #14: 7-Segment Decoder
module seg7 (bcd, leds);
input [3:0] bcd;
output [1:7] leds;
reg [1:7] leds;

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always @(bcd)
case (bcd) //abcdefg
0: leds = 7'b1111110;
1: leds = 7'b0110000;
2: leds = 7'b1101101;
3: leds = 7'b1111001;
4: leds = 7'b0110011;
5: leds = 7'b1011011;
6: leds = 7'b1011111;
7: leds = 7'b1110000;
8: leds = 7'b1111111; X dont-care
9: leds = 7'b1111011;
default: leds = 7'bx;
endcase
endmodule

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