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Lect 10

This document discusses CMOS inverter analysis and design. It covers the voltage transfer curve of an inverter and how its switching threshold depends on the ratio of PMOS to NMOS sizes. It also examines the transient behavior of an inverter and how to reduce propagation delays. Noise margin and its calculation using a piecewise linear approximation of the voltage transfer curve is described. The document discusses the effects of device variations and supply voltage scaling on inverter design and performance.

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Yash Gupta
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26 views

Lect 10

This document discusses CMOS inverter analysis and design. It covers the voltage transfer curve of an inverter and how its switching threshold depends on the ratio of PMOS to NMOS sizes. It also examines the transient behavior of an inverter and how to reduce propagation delays. Noise margin and its calculation using a piecewise linear approximation of the voltage transfer curve is described. The document discusses the effects of device variations and supply voltage scaling on inverter design and performance.

Uploaded by

Yash Gupta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Analog and Digital VLSI Design

EEE F313/INSTR F313

Lecture 10: Inverter Analysis 2


CMOS Inverter VTC
NMOS of
PMOS res
2.5 NMOS sat
PMOS res
2

1.5 NMOS sat


Vout (V)

PMOS sat
1

0.5 NMOS res


PMOS sat NMOS res
PMOS of
0
0 0.5 1 1.5 2 2.5

Vin (V)
Transient Behavior
VDD

Vin Vout
CL

Drain difusion cap


Connecting wires cap
Why tplh, tphl ???? Input cap of fanout gates
CKV

Transient Behaviour
VDD VDD

Rp

Vout Vout
CL CL
Rn

Vin = 0 Vin = V DD

Low to high Transition High to low Transition

Propagation delay RpCL Propagation delay RnCL


CKV

Transient Behaviour
How can faster gate be built ?

Keeping output capacitance small

Decreasing ON Resistance of the transistor

Increasing the W/L ratio

ON resistance not constant and is non linear function


of voltage across transistor
CKV

Static Behaviour
NMOS of
PMOS res
2.5 NMOS sat
VOL = 0 PMOS res
VOH = VDD 2

VM = f(Rn, Rp) 1.5 NMOS sat


Vm
Vout (V)
PMOS sat
1

0.5 NMOS res


PMOS sat NMOS res
PMOS of
0
0 0.5 1 1.5 2 2.5

Vin (V)
CKV

Switching Threshold
When both NMOS and PMOS are symmetrical then VM
= VDD/2
VM r VDD/(r+1)
Symmetrical when p / n = 1
r p / n

If p / n 1

Then its called skewed


inverter

HI-Skewed p / n > 1
LO-Skewed p / n < 1
CKV

Switching Threshold

VM (V)

.1 ~3.4

(W/L)p/(W/L)n
CKV

Noise Margin
We have assumed VOH = VDD and VOL = 0 V

We need VIH, VIL for calculating Noise Margin

VIH, VIL are operational points of inverter where

dVout/dvin = -1

A simpler approach is to use piece-wise linear


approximation for VTC
CKV

Noise Margin
dVout/dvin = -1

VOH = VDD
NMH = VDD - VIH
NML = VIL - GND
Vout

VM

Assuming gain g in
transition region
VOL = GND
Find VIH and VIL
Vin
CKV

Noise Margin
dVout/dvin = -1

VOH = VDD
NMH = VDD - VIH
NML = VIL - GND
Vout

VM
VIH = VM - VM /g
VIL = VM + (VDD - VM )/g
VOL = GND As g ,
Vin NMH=VDD-VM
NML=VM-GND
Device variations
We design gates for nominal conditions and typical device
parameters

But the actual operating conditions might vary over large


range

Device parameters will deviate from nominal values after


fabrication
Device variations

Good PMOS
Bad NMOS
Vout (V)

Nominal
Bad PMOS
Good NMOS

Vin (V)
Process variations (mostly) cause a shift in the switching threshold
Supply Voltage scaling
Continuing technology scaling forces the supply voltages
to reduce at rates similar to device dimensions

For example 180 nm 1.8 V and for 90 nm 1.1 V

Reducing VDD improves transition region gain

But gain degrades for very low supply voltages


CKV

Thank You

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