Power Diode, BJTs, Power MOSFETs

-Dr. AKM Ahsan

 Power Diodes
 Power diodes have some modification to make it compatible to high
voltage and currents.
 A heavily doped n type substrate, a lightly doped n- epitaxial layer and a
heavily doped p type region (diffused).
 Cross sectional area will vary according to the current that the diode is
designed to carry
 The area can be as large as 4 inch diameter (a whole wafer), can
carry several thousand amperes.
 The lightly doped n- layer (drift region) is to absorb the depletion layer
of reverse biased diode.
 Defines the breakdown voltage
 Leads to significant resistive drop at forward conduction (will
discuss more)

BVB
D
1V v
 Breakdown Voltage

BVBD=(EBD2)/(2qNd)

Wd>W(BVBD)=(2BVBD)/EBD

• To get 1000V breakdown voltage

Nd~1014 cm-3
Wd~100 um
 Depletion Layer Boundary Control

 The fringing electric field(e field

leakage) at or near the surface will
degrade the device performance.

 It is often necessary to shape the

topological contours of the device to
minimize the surface electric fields.

 Coating material is used (Si or other

insulators) to control the electric field
at surface.
Power BJT
 Physics of BJT Operation
 The emitter current IE consists of holes 1+2+3+4 (IE = IC +
IB)
 The collector current IC consists of holes 1 and 5
 The base current IB consists of electrons 2+3+4-5
 Leakage current 5 is usually negligible

E B C
IE 1 1 IC
p 2 2 n p
3 3
VEB 4 4 5 VCB
Generation
Recombination
Rin Rout
IB
 Physics of BJT Operation
Typically Emitter region is highly doped (P+). With Forward bias E-B junction Hole Injection
into the base region.
If the base is wide, most of the holes will be recombined with electrons in the base region. To
get most of the holes survived and injected into the collector region base needs to be narrow
(compared to minority carrier diffusion length).

The injected holes into the collector region are collected by the accelerated electric filed in
collector base depletion layer

So, we need (a) heavily doped emitter, (b) short base thickness, (c) long minority carrier
lifetimes in base to achieve large values of gain/beta.

E B C
IE 1 1 IC
2
p 3 2 n p
3
VEB 4 4 5 VCB p
Generation
Recombination
Rin Rout
IB
P+

n
IE=IEp(hole current)+IEn(electron current)
Ic=Icp(hole current)+Icn(electron current)
 BJT I-V Characteristics
 Base current is the control current
 When VCE = 0, E-B and C-B junctions
are forward biased
IC
 Base width modulation.

IC
VCE

Rout
IB2 VEB
IB1 Rin
ICEO (IB = 0)
IE
-VCE
 Vertical Power BJT Structure
 Power BJT: Four layer structure.
 Most power BJTs are CE.
 Base input, collector output.
 Vertical structure is preferred.
 It maximizes the x-sectional area for
current flow.
 Minimizes electrical and thermal
resistances; necessary for power
applications.
 Low doping density (n-) collector drift
region.
 Thickness determines the reverse
breakdown voltage. (tens-hundreds
micron)
 Base region should be thin to get more
amplification. However Power BJT has
relatively thicker base region, so less
amplification.
 Use Darlington pair.
 Breakdown Voltage vs. Beta
 When C-B depletion layer increases significantly and penetrates
in the base so that effective base width is zero
 Punch through occurs and enormous number of holes (for PNP) are
collected from emitter.
 Very high collector current causes a huge power drop, breakdown.
 If base is narrow, beta is high. If base is thick beta is low.
 If base is narrow, more susceptible to breakdown. If base is
thick more probability of breakdown
 ON State Losses
 On state resistances are
Emitter,collector,base and
drift region resistances.
 Most significant is drift
region resistance.
 However, due to
conductivity modulation
the scenario is not that
bad.
 MOSFET
 First understand basic MOSFET concept, then
move to power MOSFET
source gate drain

Gate
source
•
gate
•
drain
• • • •
oxide

N+ P+

Device
Structure N+ N+ P+ P+

Bulk
Si/Substrate P N

N-Channel MOSFET P-Channel MOSFET

gate
gate

Circuit
Symbol source drain source drain
Power MOSFET
 MOSFET ON and OFF Condition
•V GS =0 • +VDS

Scenario#1
No Applied Gate Voltage reverse-biased PN junction:
depletion region widens,
MOSFET is “OFF”
N+ N+ only leakage current

VGS < VT +VDS

• •
Scenario#2

Subthreshold
MOS capacitor is
MOSFET is “OFF” biased into depletion,
N+ N+
only leakage current

P
 MOSFET-ON and OFF Conditions
ramp VDS
constant VGS > VT •
• ID
Scenario#3

•••••••••••••••••
N+ N+

ID

For a constant gate voltage ID(SAT) constant VGS

(above threshold), ramp VDS Saturation
Linear
and measure ID.

0 VDS(SAT) VDS
 MOSFET ID-VG
ID Linear-Linear Log-Linear

VG
.7V

Constant VDS
Ramp VG •
• ID

Lets understand ID-VG

•••••••••••••••••
N+ N+ plot using band diagram.
(Next Slide)
P
 MOSFET Band Diagram and ID-VD
VG = 0; VD = 0

EC
EF

EV
VG > VT; VD = 0
EC
EF

EV
ID- VD Characteristics.
VG > VT; VD > 0
EC
VD1 ID
EV
VG > VT; VD >> 0

ID(SAT)
Saturation
Linear

EC
VD2
EV
VD3 0 VDS(SAT) VDS
Energy

Space
 MOSFET I-V Characteristics Summary
ID-VG ID-VD
VDS(SAT) = VGS - VT
ID
VGS = +3 V

Saturation
Linear

VGS = +2 V

VGS = +1 V

0 VDS
aside
VT (Threshold Voltage)

Subthreshold Swing:
dVGS dVGS
S  ln( 10)
d (log 1 0 ID ) d (ln ID )

Typically 60-100mV/dec
 MOSFET - Saturation Analogy
Linear
ID
water in
water out

channel
source
drain

ID(SAT)
water in

Saturation

channel
source water out

drain
 MOSFET - I-V Model

Drain Current - Linear Region


ZeffC ' OX  VDS 
 GS  VT  
L = channel length
ID   V VDS Z = channel width (perpendicular to L)
L 2 eff = surface mobility [~ 500 cm2/V·s for electrons in Si at 300K, ~ 150 cm2/V·s for holes]
C’OX = gate capacitance per unit area = OX/tOX
 = gain / transconductance factor
for VGS  VT, VDS < VDS(SAT)

Drain Current - Saturation Region (Drive Current)

substituting VDS ( SAT )  VGS  VT Tox=oxide thickness.

ID ( SAT ) 
ZeffC ' OX
2L
VGS VT  
2

for VGS  VT, VDS  VDS(SAT)

 Parasitic BJT in Power MOSFET

 Parasitic npn BJT

between source and
drain contacts.
 To minimize the
possibility that this
transistor is ever
turned on , the p type
body region is
shorted to the source
region.
 Power MOSFET
 Power MOSFET has two goals
 Should carry high current (IDS)
 Should have high blocking
voltage (VDS)
 Power MOSFETs are called
VDMOSFET
 Vertical diffused MOSFET

 The starting substrate is n+ drain.

The n- drift region is grown
epitaxially on top of it.
 The p type body region is diffused.
 Then the n+ source is diffused.
 Source and substrate are
connected together and connected
to ground.
 N+ region doping is in the 1019
range. Substrate 1016, n- drift 1014.
 Power MOSFET I-V Characteristics
 Id-VGS plot is more linear for
power MOSFET.
 At high Id, mobility
decreases due to
scattering.
 So Ids does not
increase
exponentially,
increases linearly in
power MOSFET

Regular MOSFET

Power MOSFET
 Voltage Breakdown
 Power MOSFETs have two key breakdown voltage
ratings:
 VGS max and BVDSS
 VGS max depends on gate oxide thickness, quality of gate
ox. Typically 20-30V rating.
 BVDSS depends on the length and doping density of the
lightly doped drain drift region.
 ON State Conduction Losses
 ON state resistance has the following components
 Drain region resistance, Drift region resistance, Accumulation layer resistance,
Channel resistance, Source region resistance.
 On state resistance increases with temperature increase (temp increase
due to high power dissipation). Mobility of carrier also decreases with
high temperature.
 On state resistance should be minimized by using high doping where
applicable without affecting breakdown voltage much.