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Harvard Architecture

The document discusses the Harvard architecture, which originated from the Harvard Mark I computer that stored instructions on punched tape and data in electro-mechanical counters. The key aspects of the Harvard architecture are that it has physically separate storage and signal pathways for instructions and data. This allows instructions and data to be accessed simultaneously. Modern CPUs often use a modified Harvard architecture internally by dividing cache memory into separate instruction and data caches to improve performance. Devices that still commonly use the Harvard architecture include digital signal processors and microcontrollers.

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166 views11 pages

Harvard Architecture

The document discusses the Harvard architecture, which originated from the Harvard Mark I computer that stored instructions on punched tape and data in electro-mechanical counters. The key aspects of the Harvard architecture are that it has physically separate storage and signal pathways for instructions and data. This allows instructions and data to be accessed simultaneously. Modern CPUs often use a modified Harvard architecture internally by dividing cache memory into separate instruction and data caches to improve performance. Devices that still commonly use the Harvard architecture include digital signal processors and microcontrollers.

Uploaded by

pratham gunj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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HARVARD

ARCHITECTURE
Harvard Architecture

HARVARDARCHITECTURE
Harvard Architecture
 A computer architecture with physically separate storage and signal
pathways for instructions and data.

 The term originated from the Harvard Mark I relay-based computer,


which stored instructions on punched tape (24 bits wide) and data
in electro-mechanical counters.

HARVARDARCHITECTURE
 the IBM Automatic Sequence Controlled Calculator (ASCC) --
also known as the Harvard Mark I -- the largest
electromechanical calculator ever built and the first
automatic digital calculator in the United States
HARVARDARCHITECTURE
Harvard Architecture
There is no need to make the two memories
share characteristics. In particular,
the word width, timing, implementation
technology, and memory address structure can
differ.

In some systems, instructions can be stored


in read-only memory while data memory
generally requires read-write memory.

In some systems, there is much more instruction


memory than data memory so instruction
addresses are wider than data addresses.

HARVARDARCHITECTURE
Speed

 The speed of the CPU has grown many times in comparison


to the access speed of the main memory.

 If, for instance, every instruction run in the CPU requires an


access to memory, the computer gains nothing for increased
CPU speed—a problem referred to as being "memory bound".

 It is possible to make extremely fast memory but this is only


practical for small amounts of memory for cost, power and
signal routing reasons. The solution is to provide a small
amount of very fast memory known as a CPU cache which
holds recently accessed data.

HARVARDARCHITECTURE
Internal vs. external design

 Modern high performance CPU chip designs incorporate


aspects of both Harvard and von Neumann architecture. In
particular, the Modified Harvard architecture is very
common.

 CPU cache memory is divided into an instruction cache and


a data cache. Harvard architecture is used as the CPU
accesses the cache.

HARVARDARCHITECTURE
Modern uses of the Harvard Architecture

 The principal advantage of the pure Harvard


architecture—simultaneous access to more than
one memory system—has been reduced by
modified Harvard processors using modern CPU
cache systems.
 Digital signal processors

Texas Instruments TMS320 C55x processors, as one example,


have multiple parallel data buses (two write, three read) and
one instruction bus.

HARVARDARCHITECTURE
Microcontrollers

Examples include, the AVR by Atmel Corp, the PIC by Microchip


Technology, Inc. and the ARM Cortex-M3 processor (not all
ARM chips have Harvard architecture).

AVR PIC Cortex-M3 processor

HARVARDARCHITECTURE
1-3) FILL (1 & 3 PWEDE MAGKABALIGTAD)

#1

#2

#3

4) The IBM Automatic Sequence Controlled Calculator (ASCC) –


also known as the .

5) TRUE/FALSE:
CPU cache memory is divided into an instruction cache
and a data cache.
HARVARDARCHITECTURE

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