TIMING DIAGRAM OF 8085

INSTRUCTION CYCLE
• The time required to execute an instruction is
called instruction cycle.
 MACHINE CYCLE
• The time required to access the memory or
input/output devices is called machine cycle.
 T-STATE
• The machine cycle and instruction cycle takes
multiple clock periods.
• A portion of an operation carried out in one
system clock period is called as T-state.
 MACHINE CYCLES OF 8085
The 8085 microprocessor has 5 basic machine cycles.
They are
1. Opcode fetch cycle (4T/6T)
2. Memory read cycle (3 T)
3. Memory write cycle (3 T)
4. I/O read cycle (3 T)
5. I/O write cycle (3 T)
 MACHINE CYCLES OF 8085
• The processor takes a definite time to execute
the machine cycles. The time taken by the
processor to execute a machine cycle is
expressed in T-states.
• One T-state is equal to the time period of the
internal clock signal of the processor.
• The T-state starts at the falling edge of a clock.
 TIMING DIAGRAM
• Timing Diagram is a graphical representation.
• It represents the execution time taken by each
instruction in a graphical format.
• The execution time is represented in
T-states.
 Timing Diagram
Representation of Various Control signals generated during
Execution of an Instruction.
Following Buses and Control Signals must be shown in a
Timing Diagram:
•Higher Order Address Bus.
•Lower Address/Data bus
•ALE
•RD
•WR
•IO/M
CONTROL SIGNALS
OPCODE FETCH MACHINE CYCLE OF
8085
 OPCODE FETCH MACHINE CYCLE OF
8085
• Each instruction of the processor has one byte
opcode.
• The opcodes are stored in memory. So, the processor
executes the opcode fetch machine cycle to fetch the
opcode from memory.
• Hence, every instruction starts with opcode fetch
machine cycle.
• The time taken by the processor to execute the
opcode fetch cycle is 4T.
• In this time, the first, 3 T-states are used for fetching
the opcode from memory and the remaining T-states
are used for internal operations by the processor.
MEMORY READ MACHINE CYCLE OF
8085
 MEMORY READ MACHINE CYCLE OF
8085
• The memory read machine cycle is executed
by the processor to read a data byte from
memory.
• The processor takes 3T states to execute this
cycle
• The instructions which have more than one
byte word size will use the machine cycle after
the opcode fetch machine cycle.
MEMORY WRITE MACHINE CYCLE OF
8085
 MEMORY WRITE MACHINE CYCLE OF
8085
• The memory write machine cycle is
executed by the processor to write a data
byte in a memory location.
• The processor takes, 3T states to execute
this machine cycle
 Timing Diagram
Instruction: T1 T2 T3 T4

A000h MOV A,B A0h

A15- A8 (Higher
(H Order Address bus)
Corresponding Coding: 00h 78h

A000h 78

ALE

RD

OFC WR

I O/M
8085 Memory
Op-code fetch Cycle
 Timing Diagram
Instruction:
A000h MVI A,45h
Corresponding Coding:
A000h 3E
A001h 45
 Timing Diagram
Instruction:
A000h MVI A,45h
Corresponding Coding:
OFC
A000h 3E
MEMR

A001h 45
8085 Memory
 Timing Diagram
T5 T6 T7
T1 T2 T4

A0h A0h
A15- A8 (Higher Order Address bus)
00h 3Eh 01h 45h
DA7-DA0 (Lower ord er address/data Bus)
Instruction:
ALE
A000h MVI A,45h
Corresponding Coding:
RD
A000h 3E
A001h 45
WR

I O/M

Op-Code Fetch Cycle Memory Read Cycle

 Timing Diagram
Instruction:
A000h LXI A,FO45h
Corresponding Coding:
A000h 21
A001h 45
A002h F0
 Timing Diagram

Instruction:
A000h LXI A,FO45h
Corresponding Coding: OFC

A000h 21 MEMR

MEMR
A001h 45
A002h F0 8085 Memory
 Timing Diagram

Op-Code Fetch Cycle Memory Read Cycle Memory Read Cycle

T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

A0h
A A0h A0h
A15- A8 (Higher
(H Order Address bus)
00h 21h 01h 45h 02h F0h
F
DA7-DA0 ( Lower order
er address/data
address Bus)

ALE

RD

WR

IO/M
 Timing Diagram
Instruction:
A000h MOV A,M
Corresponding Coding:
A000h 7E
 Timing Diagram

Instruction:
A000h MOV A,M
OFC

Corresponding Coding: MEMR

A000h 7E
8085 Memory
 Timing Diagram

T1 T2 T3 T4 T5 T6 T7
A0h C
Content Of Reg H
A15- A8 (Higher
(H Order Address bus)
00h 77Eh L Reg Content
Conte Of M
Instruction: DA7-DA0 ( Lower order address/data
address Bus)
A000h MOVA,M
Corresponding Coding: ALE
A000h 7E
RD

WR

I O/M

Op-Code Fetch Cycle Memory Read Cycle

 Timing Diagram

Instruction:
A000h MOV M,A
Corresponding Coding:
A000h 77
 Timing Diagram

Instruction:
A000h MOV M,A
OFC
Corresponding Coding: MEMW

A000h 77
8085 Memory
 Timing Diagram

T1 T2 T3 T4 T5 T6 T7
A 0h C
Content Of Reg H
A15- A8 (Higher
(H Order Address bus)
00h 77Eh L Reg Content of Reg A
Instruction: DA7-DA0 ( Lower order address/data
address Bus)
A000h MOV M,A
Corresponding Coding: ALE
A000h 77
RD

WR

IO/M
I

Op-Code Fetch Cycle Memory Write Cycle

 I/O READ CYCLE OF 8085
• The I/O Read cycle is executed by the
processor to read a data byte from I/O port or
from the peripheral.
• The processor takes 3T states to execute this
machine cycle.
• The IN instruction uses this machine cycle
during the execution.
I/O READ CYCLE OF 8085
 I/O WRITE CYCLE OF 8085
• The I/O write machine cycle is executed by the
processor to write a data byte in the I/O port
or to a peripheral, which is I/O, mapped in the
system.
• The processor takes, 3T states to execute this
machine cycle.
I/O WRITE CYCLE OF 8085
EXAMPLE INSTRUCTION :
MVI B, 43
EXAMPLE INSTRUCTION :
STA 526A