What’s New in Quartus Prime v15.1?

Anisha Nanda
Agenda

Quartus Prime Design Suite – Product Details

Customer Beta Registration Process
Stratix 10 Early Access software
Arria 10 Timing Model Update
MAX 10 Update
Quartus Hierarchical Design
Timing Closure & TimeQuest
BluePrint
SoC Embedded Features
IP Cores
Highlights

First release of Quartus Prime Software – Pro Edition

– Public Beta in v15.1

Full speed grade performance improvement in both editions

– Arria 10 Default Flow: 7%
– Arria 10 High Effort Flow & Physical Synthesis: 13%

Public release of BluePrint Platform Designer

– Available in Pro Edition only

New Synthesis Engine

– Expanded language (VHDL 2008 and SystemVerilog)
 Quartus Software Gets a Refresh

Web Edition Lite Edition (LE)

Subscription Edition Standard Edition (SE)

Pro Edition (PE)

4
 Do customers need to buy Pro Edition?

In v15.1, Free of charge since Pro Edition is a public beta

In v16.0, Pro Edition pricing will be effective (May 2016)

List Price
Software
Products Quartus II Quartus Prime
Subscription Standard Pro
New $2,995 $2,995 $3,995
Fixed
Renewal $2,495 $2,495 $3,395
Effective
New $3,995 $3,995 $4,995
with
Float
Renewal $2,495 $3,295 v16.0
$4,295
Release
New $945 $1,995 $1,995
ModelSim
Renewal $945 $1,695 $1,695

5
 Quartus Prime Licensing & Availability

What license do I need?

– Lite: No license file required
– Standard: Requires a Standard license (quartus feature line)
– Pro: Requires a Pro & Standard license (quartus_pro & quartus feature
line)
How do I obtain a Pro Edition license?
– Employee license via MOLSON
How can I provide my customer a Pro Edition license?
– 60-day Customer evaluation license via MOLSON
– Zero dollar order
More details coming soon

6
 Which Edition Do I Need? (LE vs SE vs PE)
Lite Standard Pro
Feature Support
Edition Edition ($) Edition ($)
1. Targeted CV, CIV, SV, SIV, A10
M10, MV, MII A10, AV, AII, (S10 coming
Device Support
Device CV, CIV,
M10, MV, MII
soon)

New Hybrid Placer  

New Global Router  

New TimeQuest  

New Physical Synthesis  

FastForward Compile EA 16.0

BluePrint 
2. Spectra-Q New Synthesis 

Productivity Rapid Recompile Only 28nm 

SignalTap Postfit 
Features OpenCL (A10) Only 28nm 

Incremental Optimization EA

Partial Reconfiguration EA

Hierarchical Design Flow 2016

Distributed Compile 2016

7
Which Edition Do I Need?

Pick the edition that supports the device you are using
– Lite Edition - CV, CIV, M10, MV, MII, AII*
– Standard Edition - SV, SIV, A10, AV, AII, CV, CIV, M10, MV, MII
– Pro Edition - A10 (S10 coming soon)

Use Standard Edition if you have:

– an existing A10 design using Subscription Edition
– an active A10 design going to production in the next 6 months

Use the Pro Edition if you have :

– A new A10 design
– A design that requires features only available in Pro Edition, for example
Partial Reconfiguration, OpenCL, and BluePrint
 Quartus Prime Software v15.1:
Higher Design Performance  Faster Timing Closure

7% Higher Fmax
Arria 10 v15.1 vs v15.0

Out of the Box

1 Speed Grade Faster

with Quartus Prime Software v15.1
10
 Quartus Prime Software v15.1:
Higher Design Performance  Faster Timing Closure

7% Higher
13% HigherFmax
Fmax
Arriav15.1 vs v15.0
10 v15.1 vs v15.0

Out of the Box

High Effort & Physical Synthesis

1 Speed Grade Faster

with Quartus Prime Software v15.1
11
 Quartus Prime v15.1 OS Support Plan
Windows Windows 7 Windows Red Hat Red Hat Windows
7 SP1 SP1 (32bit) 8.1 5.10 6.5 Server 2008 R2
(64bit) (64bit) (64bit) (64bit) SP1
(64bit)
Quartus Prime (All Editions) Standard
NIOS II EDS, DSP Builder and Lite
Editions
Only
Stand-Alone Programmer NEW in 15.1

ModelSim-Altera Windows
(requires 32-bit libraries) 8.0 Only
SoC Embedded Design Suite
Altera SDK for OpenCL
JNEye 32 and 64
bit

Pro Edition is not supported on RedHat 5.10

NEW support for a 32-bit stand-alone programmer in Windows 7
ModelSim-Altera officially supports Windows 8.0 only

For more information contact Michael Wenzler in ACDS Central

12
 Quartus Prime Documentation

Public Documents 15.1

– Quartus Prime Handbook (Standard Edition)
GUI enhancements, PR changes, Qsys walkthrough, new reports, RTL viewer
changes, Auto periphery/core optimization, BSYN, assignments
– Quartus Prime Handbook (Pro Edition)
All applicable Standard content, plus: Intro, migration, Spectra-Q engine, new
GUI, new flows, new assignments, new reports, new scripting, SignalTap post-
fit routing preservation
– Altera Software Installation and Licensing
Reflect changes to website and licensing for Pro Edition
– Quartus Prime Help
Updated to document all new GUI
Early Access Documents 15.1+
– Stratix 10 Fast Forward Compile User Guide
HyperRetiming, HyperPipelining, Fast Forward Compilation, RTL Guidelines,
Design Examples, GUI reference, Glossary

13
Customer Beta Registration

Anisha Nanda
Request Beta Software

Log in to myAltera with your myAltera user name and password

Click on ‘Beta Software Request’
Register Your Customer

Enter your customer’s email address

– Must be the same as their myAltera account email address
Click on the Email

Click on the link in the email to download the software

Download the Customer Beta Software

Log in to myAltera with your myAltera user name and password

Click on Beta Software Download
Download the Customer Beta Software
Accept the ‘Terms &
Conditions’
– Only need to do it once for
each Quartus version
Download the required
edition and device files of
the Quartus Prime software
You’re Done!
Stratix 10 Early Access Software

Joe DeLaere
 What’s Available for Stratix 10 Early Access in 15.1

Quartus Prime Standard 15.1 Supports Fast Forward Compile

– Stratix 10 FMAX Performance exploration tool using HyperFlex
Hyper-Retiming
Hyper-Pipelining
Hyper-Optimization

15.1 improvements over 15.0

– New Hyper-Optimization Advisor with step-by-step instructions and
optimization help
– New performance increases through register chain & DSP, RAM block
register placement
– New GUI and tooltips for ease of use

Not a full release for Stratix 10 support

– No IP (e.g. EMIF, transceiver) Support
– No Device selection, utilization, or pin assignments

21
 15.1 Stratix 10 Early Access Software Flow

Report
Predicted
Stratix 10
Design Standard Fast Fmax
Entry Arria 10 Forward
(RTL) Compile Compile
Report how to
increase
performance
further

Same flow as 15.0 Fast Forward Compile

22
 Stratix 10 Hyper-Optimization Advisor

Advisor walks through Stratix 10 Fast Forward Compile tools

Connects users to training & documentation
Teach users how to Hyper-Optimize their own designs

23
 Fast Forward Compile Support

Access requires additional free license on top of valid Quartus

Prime Standard license
– Request via [email protected] for your customers
– Please ensure they have a valid subscription or evaluation license first

Documentation
– New Fast Forward Compile User Guide
Integrates AN 714,715,716 and RTL design
guide/cookbook
– New Fast Forward Compile Help Documentation
– Walk through video and training on altera.com

Future releases of Fast Forward Compile

post-15.1 will be built on Quartus Prime Pro
Edition

24
Arria 10 Timing Model Updates

Rama Venkata
 Timing Model Usage
Timing Model
Description Usage
Maturity
Initial estimate of timing
Advance Pre-Layout performance, utilization and
pipelining needs
Initial timing closure
Preliminary Post-Layout Beta board prototypes (see next
slide for derivative devices)

Silicon correlated Begin final timing closure

Preliminary+
Pending volume silicon testing Complete final board design

Final All testing complete Ready for production

26
 Arria 10 Timing Model v15.1 Update
 Derivative devices (480, 320/270, 220/160) reuse architectural elements from
primary devices (1150/ 900 & and 660/ 570)
 Timing models of derivative devices inherit two key benefits from reuse of
architectural elements that are silicon correlated in primary devices
1) Derivative devices are technically labelled as P, but are much closer to F.
Because, results from silicon correlation of primary devices are built into
derivative devices timing models.
2) Skip P+ & directly move from Preliminary to Final. Or, benefit from much
shorter P+ phase.

All devices transitioned to Preliminary in 15.1

Device LE Count 15.0 15.1 16.0 16.1
1150/ 900 P P+ F F
660/ 570 P P+ P+ F
480 A P P+ F
Derivative
Devices 320/ 270 A P P F
220/ 160 A P P F
Note: Military grade devices are “P” status in v15,1 & v16.0, and go directly to “F” in v16.1.

27
 MAX 10 Update

Rich Howell

28
 What’s new for MAX 10 in 15.1?
General:
– OPN updates:
C8 temp / speed grade OPNs added for device support consistency
F variants removed
– Final Timing Models:
v15.1: 10M04, 10M08
v15.1 U1: 10M40 and 10M50
– Final Power Model support (PPPA and EPE)
v15.1: 10M02, 10M04, 10M08, 10M16, 10M40, and 10M50
v15.1 U1: 10M25
SEU: Heart-beat indicator for EDCRC

IP Support: Advanced DDR3 feature support

– ECC (DDR3/2), Advanced Bank Management, Data Reordering, Self Refresh, Auto Power
Down, Dynamic Input Buffer disable
Embedded IP and Software driver support
– NIOS: Flash accelerator for operating from UFM (was beta in v15.0)
– 16550 UART Max 10 support
– I2C Master/Slave peripheral
– QSPI x1 support in Max 10 (Linux drivers)

29
 Quartus Hierarchical Design

Rama Venkata

30
 Quartus Prime with Spectra-Q

1. New design database infrastructure

– Foundation laid for new hierarchical flows in
v16.0 and beyond
– New database + hierarchical infrastructure
– Fundamental infrastructure for Quartus Pro

2. Significant upgrade to back-end

tools and algorithms

3. Unified high level design compiler

31
 NEW
LogicLock Plus Regions (in Pro Edition only)

LogicLock Plus improves traditional LogicLock

– Includes new Routing Region constraints in 16.0
– Hierarchical flow use models in 2016

LogicLock Plus LogicLock

Quartus Prime Edition Quartus Pro Edition only Standard only

Assign Partitions to Regions No

Yes (using Quartus
Export & Import partition into a (Yes - using Spectra-Q -in
Incremental Compile)
Region 16.0/ 16.1)

Constrain Placement to a Region Yes Yes

Constrain Routing to a Region No (Yes in 16.0) No

Edit, Delete, Modify Region Yes Yes

32
 Arria10 Rapid Recompile
Quartus Prime now supports Rapid Recompile for Arria 10
– Only in Pro Edition
Up to 75% reduction in compile time with Rapid Recompile

Speedup
(Rapid Recompile versus Full Compile)
Flow
Synthesis Fit Total

HDL Change 2.2x 2.7x ~2x

SignalTap: Changing Post-

Not Applicable 3.6x ~3.6x
Fit tap points

33
 Targeted hold time optimization

Early access support in v15.1 Pro Edition. No INI variable

needed, but does not include:
– Complete GUI support,
– Documentation support
Targeted hold time optimization for Post-Route Hold Fixup
– Run after ‘Implement’, or after ‘Finalize’
– Previously: Apply over-constraints and recompile

Post Route
Map/Syn Floorplan Place Route (Hold Fix)
Finalize

“quartus_sh --implement” “quartus_fit --post-route=hold_fixup”

34
 Beta Feature in Pro Edition: Post Implement Hold Fix-Up
0

-5

-10

-15
Hold TNS (ns)

-20
Hold Total Negative Slack (TNS) measured across 50+ designs over
broad end-application segments
-25

-30

Algorithm capable of fixing a lot of violations

-35

Before
Series1 Fixup After
Series2 Fixup
35
 Beta support in v15.1 Pro Edition.
Check Pointing
 Check pointing in Quartus Pro
1) Saves compile time by ~20% with “Inner loop” compilation flow
a) First, iterate with 3-corner STA
b) Next, run finalize for HS/LP optimization and 4-corner STA/ASM
2) Faster timing closure with intermediate Post-plan & Post-place timing analysis
 Planned  estimated clock delays (no data delays)
 Placed  uses placer’s estimated data delays

TimeQuest menu:
“Netlist”  ”Create Timing Netlist”

Command line:
quartus_sta --snapshot=[planned|placed]

36
 More Check Pointing Features in Pro Edition

Per-stage reports available

– Stages: Map, Plan, Place, Route,
Finalize

‘Plan’ data available

before P&R

37
Timing Closure & TimeQuest

Rama Venkata
 Periphery-Core Optimization – Standard and Pro Editions

Early place & route for paths

between periphery & core
– Previous releases required
detailed wire or delay
window constraints
– Determines delay window
automatically
– Prioritizes, and commits
routing for these paths over
others
– Optimizations summarized
in Fitter Report

QSF:PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION
Can be applied globally (Advanced Fitter setting) or to particular entities
Auto: Will pre-place & route P2C/C2P paths with tight windows
On: Optimizes all identified paths,
Off: Prevents any optimization

39
 Multi-corner Visualization (Q15.1)

Easy switch between timing

corners
Generate reports across all
corners
– Not just in GUI, in scripts too
Summary reports available
– One list of worst-case paths
from all corners

40
 Hierarchical Reports Visualization tool (Q15.1)

Click to run report_timing

to see details of paths

The worst-case slack and

the number of paths from/to
that point of the hierarchy

Click +/- to drill down

the hierarchies Click a link to rerun the
report to/from that hierarchy
41
 Clock-Domain-Crossings Verification

Quickly verify paths that are deemed asynchronous

transfers/clocks

Validate paths affected by set_clock_groups SDC

command.

Run “report_exceptions -report_clock_groups”

– Adds a section of the report for each set_clock_groups
– Summary and detailed-paths-list views are available

42
BluePrint

Rama Venkata
 What’s New in BluePrint in Quartus Prime v15.1?

Accessing BluePrint
– Quartus Pro
BluePrint publicly visible from the Quartus Tools menu
No license or INI required to run BluePrint
– Quartus Standard
INI hidden version of BluePrint available for use in Quartus Standard
INI will be provided only to existing A10 customers unable to migrate
BluePrint will not be available in Quartus Standard after 15.1

Major user interface improvements

44
 15.1 BluePrint Features - Package View Improvements

Package view updated based on user/field feedback

– Styled to look like PinPlanner, pin special functions added as tool tips,
option to enable bank colors, flip between package top/bottom

45
 15.1 BluePrint Features - Reports Improvements

Improve user experience using BluePrint reports

– Updates to BluePrint backend and GUI report widget (RPWQ)
– Several new reports have been added to BluePrint including Clocks Report
– Reports are hyperlinked to allow integrated selection with floorplans

46
 Blueprint flow now directly accessible from the home screen
– Flow steps are buttons, and design/progress info updated dynamically during planning
More integrated selection
– Selection of design element in design tree will
Select associated location graphical views
Show information in info property view—for both design element and location
– Selection of location in graphical view will
Select associated design element in design tree
Show information in info property view—for both design element and location
Double-click “Placement” column to “zoom-to”
Selection history
– Available via forward / back buttons on info property view
Mouse rollover
– Rollover in design tree highlights locations, associated design elements (and
descendants) in graphical views
– Rollover in info properties view highlights locations, associated design
elements (and descendants) in graphical views

47
SoC Embedded Software
 SoC EDS

SoC EDS 15.1 has incremental improvements and bug fixes.

Improved productivity with A10 SoC FPGAS

– Supports A10 SoC FPGA Quartus Prime workflows
– HW Libs available
– Baremetal example for A10 SoC FPGAs
– Golden Hardware Reference Design for Quartus Prime

Improvements to DS-5 AE:

– Install multiple DS-5 AE on same host

Other updates
– Cygwin Embedded Command Shell upgraded to version 2.0.1
– Angstrom RootFS upgraded to v2014.12
– ARM baremetal gcc toolchain upgraded to gcc version 4.9.2

49
 Hardware Libraries HWLIBs

QSPI modified to enable alternate QSPI Flash

devices for all SoC devices

Full Arria 10 SoC HWLIB in 15.1 SoCEDS

– New: FPGA Mgr, ECC Mgr, Clock Mgr, Reset Mgr
– All fully tested on Arria 10 SoC
– Customer beta available September 21

UEFI Bootloader now provided for non-GPL

option instead of Minimal Preloader (MPL) due
to larger OCRAM
– Also makes use of Arria 10 SoC HWLIBs
50
 Linux and U-Boot
Latest stable kernel v 4.2

LTSI (Long Term Support) kernel v3.10 until the end of the year.
LTSI v 4.1 starting Q1 2016

U-Boot v2014.10

Yocto Project v1.7 /Angstrom Distribution 2014.12 until the end

of the year

Yocto Project v1.9 /Angstrom 2015.12 starting Q1 2016

51
 SoC Software Virtual Platform Schedule At-a-Glance

2015 2016
Jun Jul Aug Sept Oct Nov Dec Jan Feb Mar Apr May

S-10 SoC VP w/Linux

Additional Production Releases every 2 Months

S-10 SoC VP w/ Linux

Initial Production Release

S-10 SoC VP w/ Linux

Beta Release (Limited features)

A-10 SoC VP w/ Linux

Production Release (Dual Core, USB, I2C, QSPI Linux Host)

A-10 SoC VP w/ Linux

Beta Release (Limited features)

52
New IP Features

Juwayriyah Hussain
 Agenda

General IP productivity improvements

– Completed/validated out of the box IP evaluation
New Example Design GUI
Dynamically generated out-of-the-box evaluation
– IP infrastructure updates
New synthesis engine
New IP upgrade status bar in Project Navigator
– EMIF Debug Toolkit features upgrade

Individual IP Updates
– EMIF, PCIe, Ethernet, etc.

54
 Example Design Productivity Improvements

Dynamically generated and configurable hardware example

designs embedded in IP Parameter Editor GUI
– Available for EMIF, 40G-100G Ethernet, PCIe, 10G Ethernet, and
JESD204B
Can be targeted to predefined devKits
Altera Debug Master Endpoint (ADME) GUI Update

55
 IP Infrastructure Improvements

Quartus Prime Pro uses new synthesis engine Spectra-Q

– This new engine uses industry standard Verilog configurations
– A new library scheme for standalone IP has been introduced to avoid
ambiguous entity definitions

IP licenses are forward and backward compatible

– Pro license will mirror standard version license

IP Upgrade will block the compilation of IP generated using

Quartus II or Quartus Prime Standard
– Users will be able to automatically regenerate their IP

56
 IP Integration Improvements

IP upgrade notification – added visual

indication in Project Navigator to notify
users of required and recommended
upgrades
– Required IP upgrades: Red
– Recommended: Yellow

57
 Individual IP Upgrades

EMIF
– PHYLite
Hybrid Memory Cube Controller (HMCC)
PCI Express
Interlaken
SerialLite III
Ethernet
JESD204B
New DSP FEC Cores
VIDEO IP

58
 EMIF Debug Toolkit Enhancements

 Improved Debug and Diagnostics

 2D Eye Diagram for EMIF Debug Toolkit
 DDR4 and QDRIV
 Improved API for On-Chip Debug Toolkit
 Automated memory ODT sweep
 Driver-margining

 Configurable Traffic Generator 2.0 –

New GUI options
 Flexibility to enable broader traffic
patterns
 Dynamic configuration to adjust patterns
without regeneration or recompilation
 Configuration via EMIF Debug Toolkit
(GUI or Tcl interface)

59
 EMIF Upgrades
New features and protocols
– Hardware verified
DDR x4 LRDIMM – Added backside DB buffer calibration
QDR II & QDR+Xtreme
QDRIV – Pushed performance from 800 MHz to 1066 MHz

Abstract PHY – new GUI option

– Targets 3-5x improvement in simulation time (w/ existing driver traffic)
– Maintain latency & efficiency of existing skip cal simulation
External bus will not have visible activity
– Note: Only subsequent simulations will see speedup
First simulation runs skip cal sim to cache calibration settings (and ends after calibration)
Subsequent simulations will read calibration cache and invoke faster Abstract PHY sim

Non-destructive Calibration – require INI

– Adds refreshes during calibration to maintain DRAM contents
– Not currently supported for HPS EMIF

60
 Hybrid Memory Cube Controller (HMCC) Upgrades
XCVR ADME and new out-of-the-box hardware example
designs
Arria 10 timing closure
– 12.5G @ E1 with 10% margin (with seed sweep)
– 10G @ E2 with 15% margin (with seed sweep)
Support MTAPS (Multi Transaction All Packet Size)
– Up to 4 port access to HMC IP interface
– Enables full bandwidth utilization
– Full width core only
1 link (16 Lanes)

61
 Dynamic Reconfiguration of PHYLite

Timing analysis of dynamic reconfiguration of PHYLite

– User selects algorithm type and TimeQuest analyzes accordingly
– Hybrid timing analysis approach of SV and A10 EMIF
– Easy for us to document, and for customer to understand and use
Explanation of
Algorithm types

Custom Slack Dropdown box to

Recoverable choose

62
 PHYLite Debug Kit Example Design
APIs for customers to tweak PHYLite dynamic configurations
– Provide customers a design that works on HW
– NIOS-II connected to PHYLite design
NIOS controls the reconfiguration knobs
Easier for customers to debug and control PHYLite reconfigurability feature
– Include C functions or APIs to modify PHYLite configurations
C code running on the NIOS-II
– Main program that tests modifying the delay chains

63
 LVDS Dynamic Phase Shift (DPS) Example Design
Allows customers live control over the PLL clock shifts in an
LVDS design through a flexible TCL script interface
Applications
– RX Non-DPA capture debugging
Repeatedly shift the capture clock until best operational phase is found
– C2P/P2C timing debug
Try different core clock phase shifts to debug suspected timing failure
Example TCL script is provided
– Applies a phase shift to a demo clock every 5 seconds
– Demo clock can be scoped to see that the script is functional
– Code Sample:

64
 PCI Express – Performance & Productivity Unleashed

New PCI Express IP features for Arria 10

– Data Mover (aka DMA) enhancements
Now 8-bit tag field available: up to 256 tags available
– Higher # of tags yields higher throughput
Added RX buffer completion monitor capability
– Rootport use extended to 256-bit AVMM interface (preliminary)
– PCIe Link Inspector tool available to simplify debug (preliminary)
– SR-IOV PF / VF support bumped up to 4 PF / 4K VF
Early access: enabled via hidden parameter – file Service Request (SR).

Hardware example design support (push-button generation!)

– Numerous configurations covered (user interface, generation, lane width)
– Hardware platform: Arria 10 FPGA Development Kit

New easy-to-use PCI Express GUI

65
 PCI Express IP GUI Snapshot
Panels for simplified
flow & navigation

Easy configuration

66
 Interlaken / Interlaken Look-Aside – Expanded Simplicity

Interlaken MegaCores (50G and 100G)

– Altera Debug Master Endpoint (ADME) support added to Interlaken
Arria 10 devices: access to Native PHY, XCVR and other PLLs
User now has additional access points to perform test and debug
– Hardware example design support (push-button generation!)
All 4 configurations covered
– 8 x 6.25 Gbps, 24 x 6.25 Gbps, 12 x 10.3125 Gbps, 12 x 12.5 Gbps
Hardware platform: Arria 10 Transceiver Signal Integrity Development Kit
Customizations continue to roll in for Arria 10
– Interlaken / Interlaken Look-Aside customizations for Arria 10 available
through Non-Device PEP process
– Simply file a Non-Device PEP Submission Form
Located on Molson
– https://go.altera.com/extranet2001/products/ip/ipep/ipep-index.html

67
 SerialLite III Streaming

Two separate cores now available in the IP Catalog

– One supports Stratix V / Arria V GZ, other supports Arria 10
Throughput optimization by reducing to one cycle between
bursts
– Helps improve throughput & reduces overhead
Reset scheme changed to synchronous
– Enhanced implementations improve the elimination of potential
indeterminate behaviors
– Entering and exiting of reset is synchronous
– Transparent to existing and new customers
Demonstration designs on Altera Molson
– Link to Arria 10 (ES2) SerialLite III Streaming configurations
24 x 12.5 Gbps (Arria 10 FPGA Development Kit)
12 x 12.5 Gbps (Arria 10 Transceiver Signal Integrity Development Kit)

68
 Ethernet

1 / 2.5 / 10G MAC + PHY

– New IP demonstrated 46% area improvement and 54% latency
improvement over legacy 2.5G IP.
– 2.5G Ethernet offers 2.5x bandwidth performance over 1G with dynamic
reconfiguration. No changes to physical system i.e. wires, devices, etc.

Unified 1588 features for 10/40/100 G MAC IP

Timing closure
– 10% margin on A10 mid speed production

Low Latency 10G and 40G/100G new out-of-the-box hardware

example designs

69
 JESD204B

Support up to 13.5 Gbps for Arria 10

Arria V SoC new out-of-the box example design

– ARM based control plane

Dynamically generated example design

– Includes NIOS-based control plan design

70
 New Altera FEC IP Cores - Overview

New HSRS (High-Speed Reed-Solomon)

– 10Gb/s – 400Gb/s
– High-throughput and compact, for example 100Gb/s @ <9K ALM
New LDPC (Low Density Parity Check)
– DVB-S2 encoder
– WiMedia 1.5 encoder/decoder
– DOCSIS 3.1 decoder
– GSFC-STD-9100 decoder
New BCH (Bose, Chaudhuri and Hocquenghem)
– NAND Flash
– Up to ~25 Gb/s throughput
New TURBO
– Supports UMTS & LTE

71
 Forward Error Correction Applications

RSII+Viterbi LDPC,
Turbo HSRS
Viterbi Turbo

10-6 UMTS
LTE Wifi,
WiMAX 802.11n/ac
BER 10-9 DVB-S 802.16e
(target) 10-400G
DVB-S2 Ethernet
10-12 NAND
Flash

100Mb/s 1Gb/s 10Gb/s 100Gb/s 1Tb/s

BCH Throughput
RSII LDPC+BCH
LDPC+BCH

72
 Video IP Interfaces

SDI
– RX_format for 6G/12G-SDI redefined to have each stream reports its own
detected rx_format.
For example, when receiving 2160p60 in 12G-SDI, all 4 streams are expected
to report 1080p60
– Improved jitter tolerance when receiving SD-SDI
– New out-of-the-box hardware example design for multi-rate
DisplayPort
– Resolution up to 4Kp60
– MST. 1, 2, 3 and 4 streams on Stratix V and Arria 10. MST 2 streams on
Arria V
HDMI
– Resolution up to 4Kp60
– Both progressive and interlace
– HDMI mode and DVI mode

73
 Video and Image Processing Suite

End of life IPs (reminder)

– Clipper IP (replaced by Clipper II)
– Test Pattern Generator IP (replaced by Test Pattern Generator II)

Pushed out 3-release plan 4K/UHD IP updates

Quartus Prime support

– Standard version supported
– Pro version is not supported (POR for 16.0)
Altera video and image
processing suite 4K/UHD
Device support support to be demonstrated at
IBC 2015 (Stand 2.A50)
– Arria 10 support continues on limited IP subset only
See user guide for details

74
Additional Resources
Looking for More Information?

What’s New in 15.1 Training – coming soon on MOLSON

Migrating to Quartus Prime Software - Pro Edition Training
Spectra-Q Training (ASU)
BluePrint Training (ASU)
Customer: BluePrint online training (Link)
Please visit the Spectra-Q page on MOLSON for more
information on:
– Spectra-Q
– Partial Reconfiguration
– BluePrint
– Spectra-Q Synthesis
Thank You