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8085 Interrupts

The document discusses 8085 interrupts including maskable interrupts triggered by the INTR line, non-maskable interrupts triggered by the TRAP line, and vectored interrupts triggered by RST5.5, RST6.5, RST7.5 and TRAP. It describes the interrupt process where the microprocessor checks the INTR line at each instruction, saves the program counter to the stack if an interrupt is detected, and jumps to the interrupt service routine before returning using RET. It also lists the RST instructions and their binary codes and call locations. Finally, it raises issues regarding the minimum and maximum pulse widths of the INTR signal and whether interrupts can be nested.

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119 views6 pages

8085 Interrupts

The document discusses 8085 interrupts including maskable interrupts triggered by the INTR line, non-maskable interrupts triggered by the TRAP line, and vectored interrupts triggered by RST5.5, RST6.5, RST7.5 and TRAP. It describes the interrupt process where the microprocessor checks the INTR line at each instruction, saves the program counter to the stack if an interrupt is detected, and jumps to the interrupt service routine before returning using RET. It also lists the RST instructions and their binary codes and call locations. Finally, it raises issues regarding the minimum and maximum pulse widths of the INTR signal and whether interrupts can be nested.

Uploaded by

sramuk
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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8085 interrupts

8085 Interrupts
• Maskable
– INTR
– RST vectored
• Non-Maskable
– TRAP
• Vectored
– RST5.5, RST6.5, RST7.5, TRAP
Interrupt process
• enable by writing EI.
• mp checks INTR line at each instruction.
• if INTR is high, mp completes the current instr, disables
Interrupt Flip-flop, sends INTA signal.
• An RST instru is inserted by INTA through external
hardware.
• Mp saves the memory address of the next instru into
stack. Program control is transferred to CALL location.
The service routine starts at CALL location.
• At the end of the subroutine Int Flag is enabled again by
EI instru.
• The last instr of the subroutine is RET to trasfer back the
prog control to its orginal address.
RST instructions

• 8 RST instructions
Mnemon Binary code Hex Call
ics Lo
D7 D6 D D D D D D
cat
5 4 3 2 1 0
ion
+5v
RST0 1 1 0 0 0 1 1 1 C7 0000
RST1 1 1 0 0 1 1 1 1 CF 0008
RST2 1 1 0 1 0 1 1 1 D7 0010
1
RST3 1 1 0 1 1 1 1 1 DF 0018
1
EF to data bus

RST4 1 1 1 0 0 1 1 1 E7 0020
1
RST5 1 1 1 0 1 1 1 1 EF 0028
0
RST6 1 1 1 1 0 1 1 1 F7 0030
1
RST7 1 1 1 1 1 1 1 1 FF 0038
1
1
1

Enable
Write a program to count continuously in binary with one second delay between each
Count. Service routine at XX70H to flush FFH five times when the interrrupt occurs with
some appropriate delay between flash

Main program
Service routine
LXI SP, XX99H XX70: SERV: PUSH B
EI PUSH PSW
MVI A, 00H MVI B, 0AH
MVI A, 00H
NXTCNT: OUT PORT1
FLASH: OUT PORT1
MVI C, 01H MVI C, 01H
CALL DELAY CALL DELAY
INR A CMA
JMP NXTCNT DCR B
JNZ FLASH
POP PSW
POP B
Interrupt instr: EF EI
At 0028H JMP xx70H RET
Issues in implementing interrupts
• Is there a minimum pulse width required
for the INTR signals?
– MP checks INTR, one clk period before the
last-T state of an instruction cycle, therefore,
the INTR pulse should be high at least for
17.5 T-states.
• How long can the INTR pulse stay high?
• Can the MP be interrupted again before
the completion of the first interrupt service
routine?

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