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I/O Devices and Storage Performance Insights

The document discusses I/O devices, performance metrics like latency and throughput, connecting devices using buses and serial links, and techniques for communicating with I/O devices like I/O instructions, memory mapping, and DMA. Buses are being replaced by point-to-point serial links due to scaling issues as technologies get faster.

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0% found this document useful (0 votes)
52 views31 pages

I/O Devices and Storage Performance Insights

The document discusses I/O devices, performance metrics like latency and throughput, connecting devices using buses and serial links, and techniques for communicating with I/O devices like I/O instructions, memory mapping, and DMA. Buses are being replaced by point-to-point serial links due to scaling issues as technologies get faster.

Uploaded by

Dũng Nguyễn
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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I/O AND STORAGES

Contents
• I/O devices and performance
– Latency and throughput
• Connecting devices
– Busses
– Serial
• Talking to I/O devices
– How I/O instructions vs. memory mapped vs. DMA
I/O DEVICES AND PERFORMANCE
I/O today
• Devices:
– Disks
– Keyboard/Mouse
– Cameras
– Network
– Displays
• Interfaces
– USB
– PCIe
– SATA
– Ethernet
– Wireless (803.11n, bluetooth)
– Audio, video
Interface Technologies and speeds
Storage technologies, speeds, and costs

Throughput(Thông lượng): Total data per second (e.g media


processing)
Latency(độ trễ): Time to first data (database or web); e.g
facebook
NVRAM: Non-volatile Random Access Memory (retains data
Hard disks: Spinning Media

revolutions per
minute (rpm)
Throughput: Total data per
second (e.g media
processing)
Latency: Time to first data
(database or web); e.g
facebook
Desktop: Mixture
Cell phone?
Storage Prices
• Historical Cost of Computer Memory and Storage
NVRAM (Flash)
• Problems:
– Must write in large chunks
• 4096 bits at a time
• Have to read/write/update the whole chunk
– Wears out reasonably quickly
• Need to intelligently choose where to write
• Wear-leveling spreads out the writes to increase lifetime
• Spare blocks enable replacement of defective blocks
– Expensive (getting a lot cheaper)
• Benefits:
– Far faster (500MB/s vs 200MB/s)
– Far lower latency (μs vs. ms)
– Far lower power and heat (no spinning piece of metal)
• NVRAM will take over the world?
Check: Disk performance
• What is the slowest part of the disk to access?
– Center
– All the same
– Edge
Check: Latency vs. Throughput
• When you are starting an app on your phone,
what do you care most about?
– Latency
– Throughput
Busses and Serial links

CONNECTING DEVICES
Connecting Devices
• Two main ways to connect devices
• Buses
– Parallel: many bits at once (e.g 32 bits together in one clock)
– Use to be used everywhere
– Still used inside chips
• Serial links
– Serial: One bit at a time (e.g 32 clock cycles to send 32 bits)
– Used to be used only where distances were long (e.g
networks)
– Now used for most off-chip communications
The Bus
Busses
• Buses consist of data lines, control lines, and address lines.
• the data lines convey bits from one device to another,
• control lines determine the direction of data flow, and when each
device can access the bus.
• Address lines determine the location of the source or destination of
the data.

15
Busses
• Shared communications
– Many devices “on” the bus
– Run all wires to all devices
• Control
– Can have one “master” who controls access to
the bus
– Can arbitrate amount multiple devices for
who gets control
• How they work
– Master puts an address and
command(read/write) on the bus
– Slave (based on address): prepares to
receive/send data
– Next cycle(s) master puts data on the bus
(write) and slave stores it
– Or, slave puts data on the bus and master
reads it.
What is a bus? (lots of wires)
Problems with busses
• Wires are ugly
– And more so as things get smaller
• They have capacitance, inductance,
and resistance
– Slow
– The more devices on the bus, the slower
• Wires interfere with their neighbors
– Noisy
• It’s very hard to keep 32 wires
synchronized to the same clock
What happens if the signals are late?
Serial Communication
Benefits Downsides
• Send one bit at a time: Have • Much more
to determine when each bit complicated(calibration,
starts clock recovery, equalization,
• Point-to-Point: Not shared etc.)
• Can run much faster, don’t • Used wherever wires are
need to synchronize with long
other wires
Busses vs. Point-to-Point serial links
• Off-chip busses are going away
– PCI->PCIe, ATA->SATA, parallel port ->USB

• Why?
– Data is too fast for long wires
• Wire=capacitor, time to change
– Too hard to handle multiple devices on the same wire
• Wire=complex capacitor/inductor/resistor, each device complicates
– Too hard to keep wires synchronized
• Each wire is different and wires influence each other

• Replacement: SerDes
– Serial/Deserializer: Send bits one at a time
– No need to synchronize wires
Check:
• What is the main problem with busses today?
a) Hard to build lots of wires
b) Hard to synchronize lots of wires
c) Hard to put lots of devices on a shared wire
TALKING TO I/O DEVICES
Talking to I/O devices
• How does the CPU specify the device, data, and command?
• When does the CPU know the data is ready?
• What does the CPU communicate?
• How
– Special I/O instructions
– Special I/O memory addresses
– Special I/O hardware
• What:
– Data: send/receive data/address
– Control: Send commands/receive status
How: I/O instructions
• Format: device and command
– Device#: indicates the device
• E.g, keyboard input buffer is device#3
– Command:
• Sent to the I/O bus’s data lines
• From registers or memory
• Problem:
– Slow: One register at a time
– Limited: few devices, limited commands
How: Memory-mapped
• Map portions of the address space to I/O
devices
• Read and Write to those addresses to
access the device
• No special instructions needed
– Just need to know where your device is
“mapped” into memory
– Regular load and stores
– Special addresses for commands and status
• What’s the problems?
– Uses up some of our address space
Implementing memory-mapped I/O
How: Direct Memory Access (DMA)
• Wouldn’t it be better if we had special hardware that
can transfer data for us?
– No need to read and write ourselves
– No need to check status for every word
– Direct Memory Access (DMA)
• Setup the hardware to do the transfer:
– Which device
– Which command
– How much data
– Where to store/get it?
How: Direct Memory Access (DMA)
• Then let it do all the work
– E.g: Load 4096 bytes of data from the device at
address 128 and store it to address 384
– DMA will execute 1024 4-byte loads and write the
data into addresses 384-1408
• Everything is done this way these days
because the overhead of managing it
manually is too high
Check: Why DMA?
• What is the main benefit of DMA
– Easier to program
– Relieves the processor from having to manage the
I/O
Check: Memory-mapped I/O
• Why is memory mapped I/O potentially a
problem on a 32 bit machine but not a 64 bit
machine?
a) 64-bit machines are faster
b) 64 bit machines have larger words so the
transfer are faster
c) 32-bit machines have less address space so you
lose more of your memory

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