Basic Computer
Organization
Computer Organization and
Architecture
I/O Device Identification
To support multiple I/O devices there must be
a method to uniquely identify each device.
CPU designed two methods of how to interact
with I/O device.
Two methods of I/O addressing
Separate address space
Memory-mapped I/O – treat I/O device as
memory location
Separate Address Space
Each device is given an address different from
the address space for memory
Needs separate instructions for I/O
Ideal for separate CPU-memory and I/O busses
Memory-Mapped I/O
I/O devices are given addresses which are part
of the memory address space
I/O device make use of the same instructions
as that of memory
Ideal for single bus for CPU, memory and I/O
CPU-I/O Synchronization
I/O devices are slower than the CPU
Unless there is some synchronization, info may
be lost when the CPU sends data to a device
which is not yet ready
2 Methods of synchronization
Polling
Interrupts
Polling
CPU continuously tests if a device is ready to
receive information
Constantly polling a device until it is ready is
called busy waiting
Polling
Interrupts
Signal generated by SW or HW which tells the
CPU to immediately execute a priority operation
called an interrupt handler
An I/O device generates a HW interrupt when it
is ready to receive information
Interrupts
DMA (Direct Memory Access)
Interrupt-driven I/O relieves the CPU from
waiting for every I/O event, but there is still
wasted CPU cycles in transferring data
E.g. A transfer of 2048 words might need 2048
loads and 2048 stores
I/O events have a lot of block transfers, Direct
memory access (DMA) hardware is added
DMA: allows transfer of words without
intervention by CPU
DMA
Specialized processor that transfers data
between memory and I/O while the CPU is
busy doing something else.
The CPU initiates the transfer then leaves rest
to DMA controller which signals an interrupt
when it is done
Very useful for large I/O transfers
DMA
I/O Buses
There are 4 main I/O bus architectures in
the modern PC.
Industry Standard Architecture (ISA)
Peripheral Component Interconnect (PCI)
Accelerated Graphics Port (AGP)
Universal Serial Bus (USB)
Each may internal or external ports.
May be used to connect other I/O buses.
Internal vs. External Ports
Internal I/O ports
LPT, COM1, COM2, EIDE, etc.
External ports
Includes expansions slots in motherboard which
can accept various types of adapters
1. Internal Port)
LPT (Line Print Terminal) Parallel
Port
It was designed to operate a
text 8-BIT extended ASCI
character set
It was a industry standard
for many years, and was
finally standardized as IEEE
1284 in the late 1990s.
Today, the parallel port
interface is seeing
decreasing use because of
the rise of Universal Serial
Bus (USB) and FireWire
(IEEE 1394) devices; along
with network printing using
Ethernet.
Pin distribution (parallel port)
Internal Ports (Com1, Com2)
Most PC's have one or two serial
ports.
Each has a 9pin connector
(sometimes 25pin) on the back
of the computer. Computer
programs can send data (bytes)
to the transmit pin (output) and
receive bytes from the receive
pin (input).
The other pins are for control
purposes and ground.
Serial Port
1. Internal Port
EIDE (Enhanced Integrated
Drive Electronics)
EIDE (Enhanced
Integrated Drive
Electronics) is the
predecessor to SATA
(Serial Advanced
Technology Attachment).
In desktop PC's the
connector is a long
rectangular connect with
pins on the motherboard
used for connecting hard
drives and other (typical
drives
(CD/DVD/Zip/Jaz/PHDD).
Universal Serial Bus
Developed and
invented by Ajay
Bhatt while working
for Intel to replace
varies of serial and
parallel ports
Pins of USB
External port (Expansion
Slots)
is a printed circuit board that
can be inserted into an
expansion slot of a
computer motherboard to add
functionality to a computer
system.
The primary purpose of an
expansion card is to provide
or expand on features not
offered by the motherboard.
A graphics expansion card
and an ST-506 hard disk
controller card provided
graphics capability and hard
drive interface respectively.
I/O Buses in the PC
Industry Standard Architecture
( ISA)
introduced by IBM
originally an 8 bit
computer bus and was
later expanded to a 16
bit in 1984.
Introduced as propriety
bus which used for
peripheral and actual
interface.
In 1990’s Intel and
Microsoft introduced a
PnP technology of ISA
bus that allowed the
computer to automatically
detect and setup
computer ISA peripheral
used in modem and
sound Card.
ISA
16-bits wide, 8 MHz
Works synchronously with the CPU clock
If the system bus is faster than 10 MHz
then the ISA bus frequency is reduced to a
fraction of the system bus frequency.
5-8 MBps
ISA
16-bits wide, 8 MHz
Works synchronously with the CPU clock
If the system bus is faster than 10 MHz
then the ISA bus frequency is reduced to a
fraction of the system bus frequency.
5-8 MBps
ISA Internal and External Ports
ISA Disadvantages
16-bits, 8 MHz
too narrow and slow, not enough
bandwidth
No intelligence
every component requires a specific IRQ
and possibly a DMA channel
tuning of IRQ and DMA sometimes needs
to be done manually -- limited plug-and-
play features
ISA Development
No Future!! Outdated!
Intel (among with other manufacturers)
are continuing to push for the phasing
out of ISA.
Intel’s 810 chipset is the first not to
include any support for ISA.
Peripheral Component
Interconnect (PCI)
The computer bus is used by the computer to
connect to peripheral add-on devices, such
as network cards, sound cards, tv tuners,
firewire cards, graphics cards and many other
types of extension cards.
The PCI expansion slot was introduced by
Intel, but can be found in both PC's and Macs
Peripheral Component
Interconnect (PCI)
PCI
32 bits wide;
Running at 33 MHz, it has a maximum data
transfer rate of 132 MBps
Processor independent
can be used with any 32- or 64-bit CPU
Buffered architecture
Buffered Architecture
CPU delivers data to the buffer and proceeds
with other tasks; PCI bus handles the rest of the
operation
PCI adapters transmits data to the buffer,
regardless of whether the CPU is free to handle
request, i.e. requests are placed in a queue
Plug-and-play is supported in PCI specifications
PCI Internal and External
Source: www.mkdata.dk
PCI Development
PCI Express
Also known as 3GIO (Third generation I/O)
2.5 Gigabytes per second
PCI-X 2.0 for servers
266 MHz – 533 MHz
2.1 – 4.2 GBps
Backward compatible
Accelerated Graphics Port
(AGP)
The Accelerated Graphics Port (often
shortened to AGP) is a high-speed point-
to-point channel for attaching a video
card to a computer’s motherboard,
primarily to assist in the acceleration of
3D computer graphics.
Source: www.wikipedia.com
AGP Development
AGP8X
32-bit wide bus
Can work at 533 MHz
Can support up to 2.1 GB per second
ISA, PCI and AGP slots
ISA
PCI
AGP
USB
12 megabits per second (Mbps) bus
Can hold up to 127 devices in one long
chain
Devices can be plugged and unplugged
easily
USB
USB Devices
Meant to connect devices such as the keyboard,
mouse, joystick, speakers, printers, modems,
scanners, camera, etc.
Source: www.mkdata.dk
USB
12 megabits per second (Mbps) bus
Can hold up to 127 devices in one long
chain
Devices can be plugged and unplugged
easily
USB
USB Devices
Meant to connect devices such as the keyboard,
mouse, joystick, speakers, printers, modems,
scanners, camera, etc.
Source: www.mkdata.dk
USB Development
USB 2.0
Can reach speeds of up to 480 Mbps
Backward compatible with USB 1.1
Enhanced IDE (EIDE)
Also known as Advanced Technology Attachment (ATA)
Each channel has a master and slave device
Source: www.mkdata.dk
EIDE Devices
Hard disks Current EIDE hard
CDROM drives disks are in the 40-
CDR, CDR-W drives
80 GB range
DVD drives
Removables drives
(Zip, LS120, etc.)
Tape Backup units
EIDE Development
Serial ATA
150 Mbps
Uses 3-volt signals (compatible with new
low-power motherboard chip sets)
No master or slave designation
Drive capacities to reach 200GB or more
Because of drive-platter areal density from
40Gb to 60 Gb.
SCSI
Small Computer System Interface
Utilizes host adapter to control 7 (or 15)
devices using only one IRQ
SCSI has its own CPU system frees
the main CPU from the I/O workload
Read as: “skuh-see”
The SCSI Host Adapter
Intelligent controller at the heart of a SCSI
system
Controls several SCSI units including various
types of drives (hard disks, CDROM, Zip disks,
MO drives, etc.), backup tape units, scanners
Has its own BIOS
Some motherboards feature an on-board SCSI
host adapter
SCSI Chain
Regular SCSI systems can handle 8 devices
(including the adapter). Wide SCSI can handle
15 devices.
Each device has to be assigned a unique
number from ID0 to ID7 . The host adapter is
typically assigned ID7.
SCSI devices can be internal (inside the
computer casing) or external
SCSI Chain Example
SCSI Terminators
The devices at
both ends of a
SCSI chain must
be terminated.
The host adapter
is one end of the
chain.
Source: www.mkdata.dk
SCSI Intelligence
SCSI utilizes its own protocol to assure maximum
utilization of the bandwidth.
Basis of SCSI is a set of commands
Each device has its own intelligent controller which can
interpret these commands.
Source: www.mkdata.dk
SCSI Standards
Current standards include: Ultra 320 SCSI
which can send at 320 Mbps
I2O
a model for offloading I/O processing from the CPU
invented by Intel, developed by the I2O Special Interest Group
(SIG)
includes Microsoft, Adaptec, HP, Novell, Compaq, etc.
eliminates I/O bottlenecks by utilizing special I/O processors
(IOPs)
IOPs handle details of interrupt handling, buffering and data
transfer
an I2O driver consists of
an OS-specific module (OSM) that deals with higher-level
operating system details (such as accessing files)
a hardware device module (HDM) that understands how to
communicate with specific devices
OSM and HDM are autonomous (can perform a number of
tasks independently, without sending data over the I/O bus)
designed to work with PCI
proprietary specifications
7.2 Instruction Cycles
Instruction cycle is the procedure a
microprocessor goes through to process an
instruction.
1. Microprocessor fetches or reads, the
instruction from memory.
2. Then it decodes, the instructions, determine
whether which instruction it has fetched.
3. Finally, it performs the operation necessary
execute the instructions.
4. Include also the cycle of store the results.
FYI: Peripherals Components
Early IBM PC, starting with PC-AT used single
bus to interface with I/O devices using ISA
(Industry Standard Architecture)
ISA incorporate the address, data, control buses
into a single standard
Computer performance improve, this bus become
the bottleneck. Designers developed faster local
buses, separate from the main system bus.
PCI(Peripheral Component Interconnect)
commonly used in pc
FYI: Peripherals Components (cont..)
PCI bus transfers data at speeds of up to 66
MHZ and contains 100 signals.
32 of these signals are for address bus
information, and another 32 are multiplexed
address/data lines.
The remaining lines incorporate control bus
signals and signals used for error checking and
reporting, as well as signals to support cache
memory and interrupts.
How computer works
Microprocessor fetching the instruction from
memory
1. The microprocessor places the address of the
instruction on to the address bus. The memory
subsystem inputs this address and decodes it
to access the desired memory location.
2. After the microprocessor allows sufficient time
for memory to decode the address and access
the requested memory location, the
microprocessor assets a READ control signal.
How computer works (cont..)
READ signals is a signal on the control bus which the
microprocessor assets when it is ready to read data from
memory or an I/O device.
Some processor have different name for this signal, but all
microprocessor have a signal to perform (either in 0 or 1)
3. When the READ signal is asserted, the memory
subsystem places the instruction code to be fetched onto
the computer system’s data bus.
The microprocessor then inputs this data from the bus and
stores it in one of its internal register. At this point, the
microprocessor has fetched the instruction.
How computer works (cont..)
Next, the microprocessor decodes the
instruction. Each instruction may require a
different sequence of operations to execute the
instruction.
When the microprocessor decodes the
instruction, it determine which instruction it is in
order to select the correct sequence of
operations to perform. (Work exclusively by
microprocessor,not by the system buses.
How computer works (cont..)
Finally, the microprocessor executes the
instruction. The sequence of operations to
execute the instruction varies from instruction to
instruction.
The execute routine may:
read data from memory,
write data from memory,
Read data from or write data I/O device,
Perform only operations within the CPU
Or perform some combinations of these
operations.
How computer works (cont..)
To read data from memory
The microprocessor perform the same sequence
of operations: uses to fetch an instruction from
memory.
After fetching an instruction is reading it from
memory.
Timing diagram for a) memory read
Page 145 (figure 4.2)
The microprocessor uses the system clock to
synchronize its operations.
The microprocessor places the address onto the
bus at the beginning of a clock cycle, an I/O
sequence of the system clock.
