ASIC Design

Prabhavathi P
Associate Professor
Dept. of ECE, BNMIT
 Module-1 Introduction, CMOS
Logic:
 Module - 2 ASIC Library Design,
Programmable ASIC cells:
 Module – 3 Low level Design
Entry, Construction and
Partitioning:
 Module - 4 Floor planning and
Placement:
 Module – 5 Routing:

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This is a course in the field of Very
Large Scale Integration (VLSI)
circuit and systems design.
Design and analysis of VLSI
integrated circuits will be covered
from a system design perspective.
This course will focus exclusively
on digital CMOS Application
Specific Integrated Circuit (ASIC)
systems design and automation.
The ASIC physical design flow,
including logic synthesis, floor-
planning, placement, clock tree
synthesis and routing will be
presented.
These back-end physical design
flow steps will also be covered
through hands-on practice using
industrial VLSI CAD tools.

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 To learn the advanced concepts of
modern VLSI circuit and system
design, including differences
between ASICs and FPGAs,
standard cells, cell libraries, IPs etc.
 To have experience with a logic
synthesis tool for mapping RTL
onto a cell library,
 To understand the back-end
physical design flow, including
floor-planning, placement, CTS
and routing,
 To get accustomed to VLSI CAD
tools and their usability,
 To understand the standard cell
based ASIC design through the use
of test benches, timing constraints
and optimization tradeoffs for an
arbitrary sequential design with
FSM.

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1. M J S Smith,” Application
Specific Integrated Circuits”
Pearson Education 2003
2. Jose E. France, Yannis Tsividis,
“Design of Analog-Digital VLSI
circuits for Telecommunication
and signal processing” Prentice
Hall 1994
3. Malcolm R. Haskard, Lan C.
May”Analog VLSI Design –
NMOS and CMOS” Prentice Hall,
1998
4. Mohammed Ismail and Terry
Fiez, “Analog VLSI and signal
and Information Processing”
McGraw Hill, 1994

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 Understand the terminologies
associated with Standard cells and
FPGAs
 Design a moderately complex
sequential block with FSM using
HDL,
 Synthesize a complex digital
functional block using Cadence’s
RTL Compiler and Xilinx ISE.
 Demonstrate an understanding of
how to optimize the performance,
area, and power of a complex
digital functional block, and the
tradeoffs between these.
 Understand the issues involved in
ASIC design, including technology
choice, design management, tool-
flow, verification, debug and test,
as well as the impact of technology
scaling on ASIC design.

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Student at the end of the course will be able
to:
 Understand the terminologies associated
with Standard cells and FPGAs, the issues
involved in ASIC design, including
technology choice, design management,
tool-flow, verification, debug and test, as
well as the impact of technology scaling
on ASIC design.
 Describe the concepts of ASIC design
methodology, data path elements, logical
effort and FPGA architectures.
 Analyze the design of FPGAs and ASICs
suitable for specific tasks, perform design
entry and explain the physical design flow.
 Design data path elements for ASIC cell
libraries and compute optimum path delay.
 Create floor plan including partition and
routing with the use of CAD algorithms.
 To implement a design of medium
complexity (around 20K gates) using
ASIC Methodologies.

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Application-Specific Integrated Circuit

Introduction to ASICs
 ASIC - Application Specific Integrated Circuit
 In Integrated Circuit (IC) designed to perform a specific function for a specific
application
 As opposed to a standard, general purpose off-the-shelf part such as a
commercial microprocessor or a 7400 series IC
 Gate equivalent - a unit of size measurement corresponding to
a 4 transistor gate equivalent (e.g. a 2 input NOR gate)
 Levels of integration:
 SSI - Small scale integration
 MSI - Medium scale integration
 LSI - Large scale integration
 VLSI - Very large scale integration
 USLI - Ultra large scale integration
 Implementation technology
 TTL
 ECL
 MOS - NMOS, CMOS
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 An Integrated Circuit

Figure 1.1 A packaged Integrated Circuit (IC)

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 Full-Custom ASICs
 Semi-custom ASICs
– Standard-Cell–Based ASICs (CBIC)
– Gate-Array–Based ASICs (MPGA)
» Channeled Gate Array
» Channel less Gate Array
» Structured Gate Array

 Programmable ASICs
– Complex Programmable Logic Devices (CPLD)
– Field-Programmable Gate Arrays (FPGA)

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 All mask layers are customized in a full-custom ASIC
 Generally, the designer lays out all cells by hand
 Some automatic placement and routing may be done
 Critical (timing) paths are usually laid out completely by hand
 Full-custom design offers the highest performance and lowest part cost
(smallest die size) for a given design
 The disadvantages of full-custom design include increased design time,
complexity, design expense, and highest risk
 Microprocessors (strategic silicon) were exclusively full-custom, but
designers are increasingly turning to semicustom ASIC techniques in this
area as well
 Other examples of full-custom ICs or ASICs are requirements for high-
voltage (automobile), analog/digital (communications), sensors and
actuators, and memory (DRAM)
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 A cell-based ASIC ( CBIC —“sea-bick”)
Standard cells
 Possibly megacells , megafunctions , full-
custom blocks , system-level macros(
SLMs ), fixed blocks , cores , or Functional
Standard Blocks ( FSBs )
 All mask layers are customized -
transistors and interconnect
 Automated buffer sizing, placement and
routing
 Custom blocks can be embedded
 Manufacturing lead time is about eight
weeks. Figure 1.2 A cell-based ASIC (CBIC)

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 Standard Cell Layout

Figure 1.3 Layout of a standard cell

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 Standard Cell ASIC Routing
 A “wall” of standard cells forms a flexible block
 Metal2 may be used in a feedthrough cell to cross over cell rows that use metal1
for wiring
 Other wiring cells: spacer cells , row-end cells , and power cells

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Figure 1.4 Routing the CBIC
 In a gate-array-based ASIC, the transistors are predefined on the silicon
wafer
 The predefined pattern of transistors is called the base array
 The smallest element that is replicated to make the base array is called the
base or primitive cell
 The top level interconnect between the transistors is defined by the
designer in custom masks - Masked Programmable Gate Array (MPGA)
 Design is performed by connecting predesigned and characterized logic
cells from a library (macros)
 After validation, automatic placement and routing are typically used to
convert the macro-based design into a layout on the ASIC using primitive
cells
 Types of MPGAs:
 Channeled Gate Array
 Channelless Gate Array
 Structured Gate Array ASIC Design I
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 Types of MPGA
 Channeled Gate Array
 Only the interconnect is customized

 The interconnect uses predefined spaces

between rows of base cells
 Manufacturing lead time is between two days
and two weeks

Figure 1.5 Channel gate-array die

 Channelless Gate Array

 There are no predefined areas set aside for
routing - routing is over the top of the gate-
array devices
 Achievable logic density is higher than for
channeled gate arrays
 Manufacturing lead time is between two days
and two weeks
ASIC Design(SOG)
Figure 1.6 Sea-Of-Gates I array die
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 MPGA types
 Structured Gate Array
 Only the interconnect is customized

 Custom blocks (the same for each design)

can be embedded
 These can be complete blocks such as a
processor or memory array, or
 An array of different base cells better suited
to implementing a specific function
Figure 1.7 Gate array die with embedded block
 Manufacturing lead time is between two days
and two weeks.

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 Complex Programmable Logic Devices
 No customized mask layers or logic cells
 Fast design turnaround
 A single large block of programmable
interconnect
 Erasable PLD (EPLD)
 Mask-programmed PLD
 A matrix of logic macrocells that usually
consist of programmable array logic followed
by a flip-flop or latch Figure 1.8 Programmable Logic Device (PLD) die
 Field Programmable Gate Array
 None of the mask layers are customized
 A method for programming the basic logic cells
and the interconnect
 The core is a regular array of programmable basic
logic cells that can implement combinational as
well as sequential logic (flip-flops)
 A matrix of programmable interconnect surrounds
the basic logic cells
 Programmable I/O cells surround the core
 Design turnaround is a few hours
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Figure 1.9 Field-Programmable Gate Array
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1.Design entry - Using a hardware
description language ( HDL ) or
schematic entry
2.Logic synthesis - Produces a
netlist - logic cells and their
connections
3.System partitioning - Divide a
large system into ASIC-sized
pieces
4.Prelayout simulation - Check to
see if the design functions
correctly
5.Floorplanning - Arrange the
blocks of the netlist on the chip
6.Placement - Decide the locations
of cells in a block
7.Routing - Make the connections
between cells and blocks
8.Extraction - Determine the
resistance and capacitance of the
interconnect
9.Postlayout simulation - Check to
see the design still works with the Figure 1.10 ASIC design flow
added loads of the interconnect
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 Meet the market
requirement:
 Satisfying the customer need
 Beating the competition
 Increasing the functionality
 Reducing the cost
 Achieved by:
 Using the next generation
Silicon Technologies
 New Design concept and Tools
 High Level Integration

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 Examples of ICs that are not ASICs
include:
 Standard parts such as memory chips
(ROMs, RAMs)
 Microprocessors
 TTL-equivalent ICs at different levels
 Examples of ICs that are ASICs
include:
 A chip for a toy that talks
 A chip for a satellite
 A chip designed to handle the interface
between
memory and a MP for a workstation CPU
 A chip containing a MP as a cell together
with other
logic

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 Origin of ASICs:
The standard parts, initially used to design
microelectronic
systems, were gradually replaced with a
combination of glue
logic, custom ICs, dynamic random access
memory (DRAM) and
static RAM (SRAM).
 History of ASICs:
• The IEEE Custom Integrated Circuits
Conference (CICC)
and IEEE International ASIC Conference
document the
development of ASICs.
Application-specific standard
products (ASSPs) are
a cross between standard parts and
ASICs.

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 On a parts only basis, an FPGA is more expensive per-gate than an MGA, which is
in turn more expensive than a CBIC
 The key is that the fixed cost of the CBIC is higher than the MPGA which is higher
than the FPGA
 Design cost
 Fabrication cost
 Total product (or part) cost is a function of fixed cost, variable cost, and the number
of products (parts) sold:

total part cost = fixed part cost + variable cost per part X volume of parts

 Example, assume:
 FPGA fixed cost is $21,800, part cost is $39
 MGA fixed cost is $86,000, part cost is $10
 CIBC fixed cost is $146,000, part cost is $18
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 A library of cells is used by the designer to design the logic function for an ASIC
 Options for cell library:
 (1) Use a design kit from the ASIC vendor
 Usually requires the use of ASIC vendor approved tools

 Cells are “phantoms” - empty boxes that get filled in by the vendor when you deliver, or ‘hand
off” the netlist
 Vendor may provide more of a “guarantee” that design will work

 (2) Buy an ASIC-vendor library from a library vendor

 Library vendor is different from fabricator (foundry)

 Library may be approved by the foundry (qualified cell library)

 Allows the designer to own the masks (tooling) for the part when finished

 (3) You can build your own cell library

o involves a complex library development process
o Complex and very expensive
o Difficult and costly

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 A complete ASIC library (suitable
for commercial use) must include
the following for each cell and
macro:
 A physical layout
 A behavioral model
 A VHDL or Verilog model
 A detailed timing model
 A test strategy
 Timing model
 Test strategy
 Characterization
 Circuit extraction
 Process control monitors
 Cell schematic
 Cell icon
 LVS scheck
 Logic synthesis
 Retargeting
 Wire load model
 Routing model

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• Design entry & Simulation (Front
End)
• Schematic Entry
• HDL Entry
• State Machine Diagram Entry
• Synthesis
• Place & route (Back End)
• Verification
• Fabrication

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Faster time-to-market:
• No layout, masks or other manufacturing steps are
needed for FPGA design.
• Readymade FPGA is available and burn your HDL code to
FPGA ! Done !!
No NRE (Non Recurring Expenses):
• This cost is typically associated with an ASIC design.
• For FPGA this is not there.
• FPGA tools are cheap. (sometimes its free ! You need to
buy FPGA.... thats all !).
• ASIC you pay huge NRE and tools are expensive. "...Its in
crores....!!

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Simpler design cycle:
• This is due to software that handles much of the routing, placement, and
timing.
• Manual intervention is less.
• The FPGA design flow eliminates the complex and time consuming
floorplanning, place and route, timing analysis.
Field Reprogramability:
• A new bitstream ( i.e. your program) can be uploaded remotely,
instantly.
• FPGA can be reprogrammed in a snap while an ASIC can take
$50,000 and more than 4-6 weeks to make the same changes.
• FPGA costs start from a couple of dollars to several hundreds or more
depending on the hardware features.

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More predictable project cycle:
• The FPGA design flow eliminates potential re-spins, wafer
capacities, etc of the project since the design logic is already
synthesized and verified in FPGA device.
Reusability:
• Reusability of FPGA is the main advantage.
• Prototype of the design can be implemented on FPGA which
could be verified for almost accurate results so that it can be
implemented on an ASIC.
• If design has faults change the HDL code, generate bit stream,
program to FPGA and test again.
• Modern FPGAs are reconfigurable both partially and
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•FPGAs are good for prototyping and limited production. If you are going to
make 100-200 boards it isn't worth to make an ASIC.
• Generally FPGAs are used for lower speed, lower complexity and lower
volume designs.
• But today's FPGAs even run at 500 MHz with superior performance.
• With unprecedented logic density increases and a host of other features,
such as embedded processors, DSP blocks, clocking, and high-speed serial at
ever lower price, FPGAs are suitable for almost any type of design.
• FPGA sythesis is much more easier than ASIC.
• In FPGA you need not do floor-planning, tool can do it efficiently. In ASIC you
have do it.

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Unlike ASICs, FPGA's have special hardwares such as
Block-RAM, DCM modules, MACs, memories and
highspeed I/O, embedded CPU etc inbuilt, which can be
used to get better performace.
• Modern FPGAs are packed with features.
• Advanced FPGAs usually come with phase-locked
loops, low-voltage differential signal, clock data recovery,
more internal routing, high speed, hardware multipliers
for DSPs, memory,programmable I/O, IP cores and
microprocessor cores.
• Remember Power PC (hardcore), Microblaze (softcore)
in Xilinx and ARM (hardcore), Nios(softcore) in Altera.
• There are FPGAs available now with built in ADC ! Using
all these features designers can build a system on a
chip. Now, dou yo really need an ASIC ?
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Power consumption in FPGA is more.
– You don't have any control over the power
optimization. This is where ASIC wins the race !
• You have to use the resources available in the
FPGA.
– Thus FPGA limits the design size.
• Good for low quantity production.
– As quantity increases cost per product increases
compared to the ASIC implementation.

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Cost....cost....cost....Lower unit costs:
• For very high volume designs costs comes out
to be very less.
• Larger volumes of ASIC design proves to be
cheaper than implementing design using FPGA.
Speed...speed...speed....ASICs are faster than
FPGA:
• ASIC gives design flexibility.
• This gives enoromous opportunity for speed
optimizations.

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Low power....Low power....Low power:
• ASIC can be optimized for required low power.
• There are several low power techniques such as power
gating, clock gating, multi vt cell libraries, pipelining etc are
available to achieve the power target.
• This is where FPGA fails badly !!! Can you think of a cell
phone which has to be charged for every call.....never ..
.....low power ASICs helps battery live longer life !!
In ASIC you can implement analog circuit, mixed signal
designs.
This is generally not possible in FPGA.
In ASIC DFT (Design For Test) is inserted.
In FPGA DFT is not carried out (rather for FPGA no need of DFT !)

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Time-to-market:
• Some large ASICs can take a year or more to design.
• A good way to shorten development time is to make prototypes using
FPGAs and then switch to an ASIC.
Design Issues:
• In ASIC you should take care of DFM issues, Signal Integrity issues
and many more.
• In FPGA you don't have all these because ASIC designer takes care of
all these. (Don't forget FPGA is an IC and designed by ASIC
design engineer !!)
Expensive Tools:
• ASIC design tools are very much expensive.
– You spend a huge amount of NRE.

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We’ll compare the most popular types of ASICs: an
FPGA, an MGA, and a CBIC.
• Example of an ASIC part cost:
– A 0.5mm, 20k-gate array might cost 0.01–
0.02 cents/ gate (for more than 10,000
parts) or $2–$4 per part,
but an equivalent FPGA might be $20.
• When does it make sense to use a more
expensive part?
This is what we shall examine next.
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• In a product cost there are fixed costs and variable costs (number of
products sold is the sales volume):
total product cost = fixed product cost + variable product cost x products sold
• In a product made from parts the total cost for any part is
total part cost = fixed part cost + variable cost per part x volume of
parts
• For example, suppose we have the following costs:
– FPGA: $21,800 (fixed) $39 (variable)
– MGA: $86,000 (fixed) $10 (variable)
– CBIC $146,000 (fixed) $8 (variable)
• Then we can calculate the following break-even volumes:
– FPGA/MGA » 2000 parts
– FPGA/CBIC » 4000 parts
– MGA/CBIC » 20,000 parts

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Examples of fixed costs are:
– training cost for a new (EDA) system
– hardware and software cost
– productivity
– production test and design for test
– programming costs for an FPGA
– nonrecurring-engineering (NRE)
– test vectors and test-program development cost
– pass (turn or spin)
– profit model represents the profit
– flow during the product lifetime

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Factors affecting fixed costs are:
– wafer size and cost
– gate density and gate utilization
– die size and die cost
– die per wafer
– defect density
– yield
– profit margin (depends on fab or fabless)
– price per gate
– part cost

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• Scan insertion and clock tree synthesis are not required
in FPGA design flows because of the inherent design of
Altera FPGAs.
• In FPGA design flows, place-and-route is performed by
the customer using the FPGA vendor place-and-route
tools.
• In ASIC design, place-and-route and physical design
verification such as crosstalk analysis between internal
device signals may be performed by the customer or
handed off to an ASIC foundry for implementation.
• Developing ASICs requires careful design and
placement of I/O cells to support the latest complex I/O
standards with good signal integrity on all pins.

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• ASIC testing and fault coverage are important parts of
the ASIC development process.
• Testing involves the desired design functionality and the
design of the ASIC, and uses boundary scan insertion,
built-in-self-test (BIST), signature analysis, Iddq, and
automatic test pattern generation (ATPG) techniques.
• FPGAs already include boundary scan logic as opposed
to ASIC design flow where you must insert boundary
scan logic and simulate it on top of the actual design
logic.
• FPGAs have already been extensively tested during
manufacturing.
• In FPGA design flows, you can focus on testing design
functionality and timing requirements and do not need to
perform device design tests such as crosstalk analysis.
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• Altera’s FPGAs include advanced, low-skew clock
networks for clock distribution within the device.
• The FPGA designer must give up the ASIC designer's
freedom to implement fully custom clock networks;
• The pre-defined clock tree structure in an FPGA
enormously simplifies the design process and satisfies a
majority of applications.
• By using FPGA devices in place of ASICs, you can
potentially reduce the complexity of the design process
as well as significantly reduce cost.

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• The back-end design of an ASIC device involves a wide
variety of complex tasks, including placement, physical
optimization, clock tree synthesis, signal integrity analysis
and routing using different EDA software tools.
• When compared to ASIC devices, the physical, or backend
design of FPGA devices is very simple and is
accomplished with a single software tool (Quartus II).
• The Quartus II software is a fully integrated, architecture
independent package offering a full spectrum of logic design
capabilities for designing with FPGAs.
• The flow discusses and compares each of the tasks
involved in the design flows for both FPGA and ASIC
devices.
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Datapath Logic cells
• CMOS logic
• Logic levels
• Transmission Gates
• Sequential Logic Cells
• Datapath Logic Cells
• Adders
• Multipliers
• Other Arithmetic Systems
• Other Datapath Operators
• I/O Cells
• ESD

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Figure 2.5 CMOS logic levels. (a) A strong
‘0’. (b) A weak ‘1’. (c) A weak ‘0’. (d) A
strong ‘1’.

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Figure 2.1 CMOS transistors as switches. (a) An N-channel transistor. (b) A P-channel transistor. (c) A CMOS inverter

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Figure 2.2 CMOS logic. (a) A two-input NAND gate. (b) A two-input NOR gate.

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Figure 2.6 IC fabrication Grow crystalline silicon (1); make wafer (2-3); grow and oxide layer (4);
apply liquid photoresist (5); mask exposure (6); cross-section showing exposed
photoresist (7); etch the oxide layer (8); ion implantation (9-10); strip resist (11); strip
oxide (12); repeat steps similar to 4-12 for subsequent layers (12-20 times for a typical
CMOS process).
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Figure 2.7The drawn layers, final
layout, and phantom cell
view of the standard cell
shown in figure 1.3

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Figure 2.9 The transistor layers (a) a drawn P-channel layout. (b) The corresponding silicon cross-section.

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Figure 2.10 The interconnect layers. (a) The drawn layers. (b) The corresponding structure.
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Figure 2.11 The MOSIS SCMOS design
rules (rev. 7). Dimensions are
in l.

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Figure 2.12 Naming and numbering conventions for complex CMOS cells. (a) An
AND_OR_INVERT cell. (b) An OR-AND-INVERT cell
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Figure 2.13 Constructing a CMOS AOI221 cell. (a) Use Demorgan’s theorem to “push” inversion bubbles to
the inputs. (b) Build the pull-up and pull-down networks from PMOS and NMOS transistors. (c) Adjust
transistor sizes so that the n and p based networks have the same drive strength - to ensure equal rise and
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Figure 2.14 CMOS transmission gate (TG). (a) a P and N transistor implementation. (b) A
common symbol. (c) The charge sharing problem.

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Figure 2.15 A CMOS multiplexer (MUX). (a) A TG implementation without buffering. (b) The corresponding logic
symbol. (c) The IEEE standard symbol. (d) an alternate (non-standard) IEEE symbol. (e) An inverting,
buffered implementation and its logic symbol. (f) a non-inverting, buffered implementation and its symbol.

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Figure 2.16 An inverting 2:1 mux based on an OAI22 cell

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Figure 2.17 CMOS latch. (a) A positive-enable latch using transmission gates (b) Operation
when enable is high. (b) Operation when enable is low.

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Figure 2.18 CMOS flip-flop. (a) Negative
edge triggered master-slave. (b)
Master loads when clock is high.
(c) Slave loads output value of
master latch when clock goes
low. (d) Waveforms illustrating
setup, hold, and propagation
times.

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Figure 2.20 A datapath adder. (a) A full adder (FA) cell. (b) A 4-bit adder. (c) Wiring layout using 2 level metal. (d) The
datapath layout

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Figure 2.21 Symbols for a datapath adder. (a) A generic symbol. (b) An alternate symbol. (c) A symbol with control lines.

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Figure 2.22 The ripple carry adder (RCA). (a) A conventional RCA. (b) An implementation using ASIC
alternate
Design cells
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Figure 2.23 The carry-save adder (CSA). (a) A CSA cell. (b) A 4-bit CSA. (c) Symbol for a CSA. (d) A 4-input CSA. (e)
The datapath for a 4-bit adder using CSAs. (f) A pipelined adder. (g) The datapath for the pipelined
version. ASIC Design I
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CSA cell CSA(A1[i], A2[i], A3[i ], CIN, S1[i], S2[i], COUT) has
three outputs:

• In CSA the carries are saved at each stage and shifted

left onto the bus S1.
• There is thus no carry propagation and the delay of a
CSA is constant.
• At the output of a CSA we need to add the S1 bus (all
saved carries) and the S2 bus (all the sums) to get an n bit
result using a final stage. ASIC Design I
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Figure 2.24 The Brent-Kung carry-lookahead adder. (a) Carry generation. (b) Cell to generate look-ahead terms. (c)
Arrangement of cells. (d) and (e) Simplified representations of parts a and c. (f) The lookahead logic for
an 8 bit adder. (g) An 8 bit Brent-Kung CLA. ASIC Design I
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ASIC Design I
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Figure 2.25 The conditional-sum adder (a) A 1-bit conditional adder. (b) The multiplexer to select sums and carries. (c)
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• Carry-select adder duplicates two small adders
for the cases CIN='0' and CIN='1' and then uses
a MUX to select the case that we need
• A carry-select adder is often used as the fast
adder in a datapath library because its layout is
regular.
• Extending the idea of carry-select adder we can
design Conditional-sum adder.
• The n-bit conditional-sum adder that uses n
single-bit conditional adders, together with a tree
of 2:1 MUXs is as shown.

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Figure 2.26 Delay and area comparison for datapath adders. (a) Delay normalized to a two-input NAND logic cell
delay. (b) Adder area.

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Figure 2.27 A 6-bit array
multiplier using a
final carry-propagate
adder.

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Figure 2.32 Symbols for datapath elements. (a) An N-bit wide register. (b) An N-bit wide two-input NAND array. (c)
An N-bit wide two-input NAND array with a control input. (d) An N-bit wide MUX. (e) An N-bit wide
incrementer/decrementer. (f) An N-bit wide all zeros detector. (g) An N-bit wide all ones detector. (h) An
N-bit wide adder/subtracter.

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 I/O pads are specalized to connect to
the actual pins of the device
 Electrostatic discharge (ESD)
 High(er) drive capability to drive
larger capacitances (bonding pad,
bond wire, device pin, PCB trace >
20pF)
 Different types of I/O pads are
provided to perform different
functions
 Digital input
 Digital Output
Figure 2.33 A tri-state bidirectional output buffer with I/O pad.
 Digital Bi-directional
 Analog In/Output

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 • Transistors as Resistors
• Transistor Parasitic Capacitance
• Logical Effort
• Library-Cell Design
• Gate-Array Design
• Standard-Cell Design
• Cell Compilers
 ASIC design uses predefined and
pre-characterized cells from a
library.
 So we need to design or buy a cell
library.
 A knowledge of ASIC library
design is not necessary but makes it
easier to use library cells
effectively.

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Figure 3.3 Simulation of an inverter
driving a variable number of
gates on its output

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Junction Capacitance
 Overlap Capacitance
 Gate Capacitance
 Input Slew Rate

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Figure 3.4 Transistor parasitic
capacitance. (a) An N-
channel MOS transistor
with gate length L and
width W. (b) The
components of the gate
capacitance. (c)
Approximating
capacitances with planar
components. (d) The
components of the diffusion
capacitance. (e)-(h) The
dimensions of the gate,
overlap, and sidewall
capacitances.

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 V DD V DD

R Pon
VOH = VDD
V out
V out VOL = 0

R Non VM = f(RNon,RPon)

RNon  1/WN
V in = V DD V in = 0
RPon  1/WP
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Figures from material provided with Digital Integrated Circuits, A Design
Perspective, by Jan Rabaey, Prentice Hall, 1996
Vou t NMOS off
PMOS lin

5 NMOS sat
PMOS lin
4

NMOS sat
3

PMOS sat
2

NMOS lin
PMOS sat NMOS lin
1

PMOS off

1 2 3 4 5 Vin

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Figures from material provided with Digital Integrated Circuits, A Design
Perspective, by Jan Rabaey, Prentice Hall, 1996
Vout

Ri = 

Ro = 0
g= 

Vin

Vm = Vdd/2 ASIC Design I

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Figures from material provided with Digital Integrated Circuits, A Design
Perspective, by Jan Rabaey, Prentice Hall, 1996
Assume that due to differences in mp and mn, for a minimum
sized transistor, Rp = 2Rn
For a balanced inverter we want RP = RN, so in this case, WP
must be 2WN
VDD

WP/LP = 2/1

Vin Vout

CL

WN/LN = 2/1

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Figure 3.8 Logical effort. (a) The input capacitance looking into the input capacitance of a minimum size inverter. (b) Sizing a
logic cell’s transistors to have the same delay as a minimum size inverter. (c) The logical effort of a cell is C in/Cinv.

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Figure 3.10 An AOI221 cell with logical effort vector g=(8/3, 8/3, 7/3). ASIC Design I
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 to other gates (fanout)

to other gates (fanout)

Which is faster? buffer

to other gates (fanout)

to other gates (fanout)

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 The delay equation is the sum of
three terms,
d = f + p + q or
 delay = effort delay + parasitic
delay + non-ideal delay
 The effort delay f is the product of
logical effort, g, and
electrical effort, h:
f = gh
 Thus, delay = logical effort x
electrical effort + parasitic
delay +
nonideal delay.
 R and C will change as we scale a
logic cell, but the RC
product stays the same.
 Logical effort is independent of the
size of a logic cell.
 We can find logical effort by scaling a
logic cell to have
the same drive as a 1X minimum-size
inverter.

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 Then the logical effort, g, is the ratio
of the input
capacitance, Cin of the 1X logic cell
to Cinv.
 Inverter has the smallest logical effort
and
intrinsic delay of all static CMOS
gates.
 Logical effort of a gate presents the
ratio of its
input capacitance to the inverter
capacitance
when sized to deliver the same
current.
 Logical effort is the ratio of input
capacitance of
a gate to the input capacitance of an
inverter
with the same output current.
 Logical effort increases with the gate
complexity.
 Logical effort is a function of
topology,
independent of sizing.
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In ripple carry addition, the
critical path goes from C to
Cout through many full
adders.
 Carry ripple adder is compact and fast enough for many non
critical paths
 For high performance microprocessors where adders in the
critical path, a tree adder of logarithmic depth is desirable.
 Brent –Kung has extra logic levels
 Sklansky has large fanout
 Kogge-Stone has more wiring tracks-used in Ultra sparc III
 NAffziger adder is used in Itanium 2 and HP PA-RISC 64 bit
processors
 AMD29050 microprocessor uses hybrid valency -4 tree adder
driving 8 bit Carry select multiplexers
 The best depends on the implementation technology
carry-skip adder :
tpg + 2(n – 1) + (k-1)tAO + txor
carry-look-ahead adder:
tpg + tpg(n) + [(n – 1) + (k-1)]tAO + txor
carry-select adder :
tpg + [n + (k-2)]tAO + tmux
carry-increment adder:
tpg + tpg(n) + [k-1]tAO + txor
tree adder :
tpg + [log2N]tAO + txor
A CSA is effectively a 1’s Counter that adds the numbers of 1’s on the
A, B and C inputs and encodes the on the sum and carry outputs as
summarized in the table below
Designing and implementing a given CMOS chip is
largely affected by the availability of tools, the schedule
, the complexity of the system, and the final cost of the
chip
Simplest and least expensive approach that meets the
target goals should be chosen
This means synthesis and place and route is good
enough
Modern synthesis tools draw on a good library of adders
and multipliers with various area/speed tradeoffs