CMOS Fabrication

• CMOS transistors are fabricated on silicon

wafer
• Lithography process similar to printing press
• On each step, different materials are
deposited or etched
• Easiest to understand by viewing both top and
cross-section of wafer in a simplified
manufacturing process

Fabrication and Layout Slide 1

 Inverter Cross-section
• Typically use p-type substrate for nMOS transistor
– Requires n-well for body of pMOS transistors
– Several alternatives: SOI, twin-tub, etc.
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

Fabrication and Layout Slide 2

 Well and Substrate Taps

• Substrate must be tied to GND and n-well to VDD

• Metal to lightly-doped semiconductor forms poor connection
called Shottky Diode
• Use heavily doped well and substrate contacts / taps
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

Fabrication and Layout Slide 3

 Inverter Mask Set

• Transistors and wires are defined by masks

• Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

Fabrication and Layout Slide 4

 Detailed Mask Views
• Six masks n well

– n-well
– Polysilicon Polysilicon

– n+ diffusion n+ Diffusion

– p+ diffusion p+ Diffusion

– Contact Contact

– Metal
Metal

Fabrication and Layout Slide 5

 Fabrication Steps

• Start with blank wafer

• Build inverter from the bottom up
• First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate

Fabrication and Layout

 Oxidation
• Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

Fabrication and Layout

 Photoresist
• Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light

Photoresist
SiO2

p substrate

Fabrication and Layout

 Lithography
• Expose photoresist through n-well mask
• Strip off exposed photoresist

Photoresist
SiO2

p substrate

Fabrication and Layout Slide 9

 Etch
• Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been
exposed

Photoresist
SiO2

p substrate

Fabrication and Layout Slide 10

 Strip Photoresist
• Strip off remaining photoresist
– Use mixture of acids called piranah etch
• Necessary so resist doesn’t melt in next step

SiO2

p substrate

Fabrication and Layout Slide 11

 n-well

• n-well is formed with diffusion or ion implantation

• Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
• Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si

SiO2

n well

Fabrication and Layout Slide 12

 Strip Oxide
• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of
steps

n well
p substrate

Fabrication and Layout Slide 13

 Polysilicon

• Deposit very thin layer of gate oxide

– < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

Fabrication and Layout Slide 14

 Polysilicon Patterning
• Use same lithography process to pattern
polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

Fabrication and Layout Slide 15

 Self-Aligned Process
• Use oxide and masking to expose where n+
dopants should be diffused or implanted
• N-diffusion forms nMOS source, drain, and n-
well contact

n well
p substrate

Fabrication and Layout Slide 16

 N-diffusion

• Pattern oxide and form n+ regions

• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned gates because it doesn’t
melt during later processing

n+ Diffusion

n well
p substrate

Fabrication and Layout Slide 17

 N-diffusion
• Historically dopants were diffused
• Usually ion implantation today
• But regions are still called diffusion

n+ n+ n+

n well
p substrate

Fabrication and Layout Slide 18

 N-diffusion
• Strip off oxide to complete patterning step

n+ n+ n+
n well
p substrate

Fabrication and Layout Slide 19

 P-Diffusion
• Similar set of steps form p+ diffusion regions
for pMOS source and drain and substrate
contact

p+ Diffusion

p+ n+ n+ p+ p+ n+
n well
p substrate

Fabrication and Layout Slide 20

 Contacts
• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate

Fabrication and Layout Slide 21

 Metallization

• Sputter on aluminum over whole wafer

• Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

Fabrication and Layout Slide 22

 Layout
• Chips are specified with set of masks
• Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
• Feature size f = distance between source and drain
– Set by minimum width of polysilicon
• Feature size improves 30% every 3 years or so
• Normalize for feature size when describing design rules
• Express rules in terms of l = f/2
– E.g. l = 0.3 mm in 0.6 mm process

Fabrication and Layout Slide 23

 Simplified Design Rules

• Conservative rules to get you started

Fabrication and Layout Slide 24

 Inverter Layout

• Transistor dimensions specified as Width / Length

– Minimum size is 4l / 2l, sometimes called 1 unit
– For 0.6 mm process, W=1.2 mm, L=0.6 mm

Fabrication and Layout Slide 25