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VLSI Testing Unit 5

The document discusses VLSI testing at various levels from wafer to system. It covers the need for testing due to manufacturing defects and describes different types of testing like functionality and manufacturing testing. Manufacturing testing aims to identify good dies and verify gates and registers were made correctly. Stuck-at faults are a common fault model and different techniques for generating test vectors like path sensitization are described to exhaustively test circuits.

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kashi vissu
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1K views

VLSI Testing Unit 5

The document discusses VLSI testing at various levels from wafer to system. It covers the need for testing due to manufacturing defects and describes different types of testing like functionality and manufacturing testing. Manufacturing testing aims to identify good dies and verify gates and registers were made correctly. Stuck-at faults are a common fault model and different techniques for generating test vectors like path sensitization are described to exhaustively test circuits.

Uploaded by

kashi vissu
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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VLSI Design

VLSI Testing
• CMOS Testing
• Need for testing
• Test Principles
• Design Strategies for test
• Chip level Test Techniques
• System-level Test Techniques
• Design for testability (K. Eshraghian 308)
• Practical design for test guidelines (K. Eshraghian
314)
• Built-In-Self-Test. (K. Eshraghian 326)
CMOS TESTING
• Once a logic function has been designed, it
must be tested
– Faulty chips should be identified from good chips
– Test Engineers must develop test methodology
• If a die passes the testing it is packaged and
sold
• Fault in a chip may be a manufacturing defect
– It may be due to various mechanisms
– Ranging from crystalline defects to
– lithographic errors that causes bad etching of vias
IC Testing
“If you don’t test, it won’t work” - IBM

Circuit under
Test (CUT)
Input Output

Read Only
Comparator
Memory
Known good
Response
Good / Bad IC

Figure 1. Basic Testing Process

• Testing: Process of identifying the manufacturing defects


• Applying set of input patterns and verifying results
NEED FOR TESTING
• Due to complexity of manufacturing process
not all dice on a wafer operate correctly
– Bridged connections or missing features
• The aim of test procedure is to identify good
dice that are to be used in end systems
Levels of Testing
• Testing of a die can occur at
– wafer level
– Packaged chip level
– Board level
– System level
– In the field
• Detecting the fault at the earlier level the
manufacturing cost becomes low
Types of Testing
• Two types of testing
– Functionality Test – Before Fabrication
– Manufacturing Test – After Fabrication
• Functionality Test
– It verifies that the chip performs its intended
function
– This test asserts that all gates in the chip
achieve the desired function
– Functionality tests ensure that the circuit is
functionally equivalent to some specification
Manufacturing Test
• These tests verify that every gate and register
in the chip manufactured correctly
– Free from manufacturing defects
• Commonly observed defects and their results
Defect Result
1. Layer to layer short Nodes shorted to
(e.g., Metal to Metal) PWR or GND
2. Discontinues wires i/p floating or
o/p disconnected
3. Thin oxide shorts to I/p & o/p shorted
substrate or well
Manufacturing Test
• Apart from the verification of internal gates,
I/O integrity is tested using
– I/O level test (Noise margin of TTL, ECL & CMOS)
– Speed test (Operating at high or low speed clock)
– IDD Test (Output current level)
• Manufacturing test assumes that the chip is
functionally correct
– It identifies ways of exercising all gate inputs and
monitoring all gate outputs
Manufacturing Test principles
• Testing a circuit for exhaustively large
number of test vectors are needed
– Test time will become more
– Test engineer should identify minimum
number of test vectors to detect all faults
• To test combinational circuit exhaustively
2n Test patterns are required
Manufacturing Test principles
Testing sequential circuits requires 2n+m test
vectors required
FAULT MODELS
• STUCK-AT FAULTS: Most popular fault model

A model for how faults occur


and their impact on circuits
FAULT MODELS
• STUCK-AT FAULTS: Impact
Fault free and faulty function
FAULT MODELS
• STUCK-OPEN FAULTS

Stuck open or stuck-


off fault causes no
current flow in the
transistor regardless NOR gate
of VGS or VDS
FAULT MODELS
TEST VECTOR GENERATION
TECHNIQUES
• TEST VECTOR:
– A group of binary bits when applied as input to a
digital circuit, gives two different results when it is
faulty and good.
• TV Generation techniques
– Path sensitization method
– Boolean Difference method
PATH SENSITIZATION
TECHNIQUE
• Steps involved to find test vector
1 Fault Sensitization
2 Fault Propagation
3 Line Justification
Step1: Fault Sensitization
 Bring the Faulty node to opposite value of the
fault expected
- Making node h – value 1
Step2: Fault Propagation
 Try to propagate the faulty node value to the primary
output or some observable point in the circuit.
Step3: Line justification
• Back tracking from output node towards input nodes to
justify the values applied at fault y and output node
TEST VECTORS USING PATH
SENSITIZATION METHOD
Thank You

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